Transient voltage suppression protection device

Abstract

The utility model provides a transient voltage suppression protection device. The transient voltage suppression protection device comprises a substrate; the epitaxial layer is located on the substrate; the at least two isolation groove structures penetrate through the epitaxial layer and extend into the substrate, the epitaxial layer is divided into a first region and a second region which are isolated from each other, and the second region surrounds the first region; the first doped region and the third doped region are located in the first region, the first doped region penetrates through the epitaxial layer and extends into the substrate, the third doped region extends downwards from the surface of the epitaxial layer, and the first doped region surrounds the third doped region; the second doped region and the fourth doped region are located in the second region, the second doped region penetrates through the epitaxial layer and extends into the substrate, the fourth doped region extends downwards from the surface of the epitaxial layer, and the second doped region and the fourth doped region surround the first region; the second doped region is positioned on at least one side of the fourth doped region; the first doped trench structure is located in the first doped region; the second doped trench structure is located in the second doped region.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a transient voltage suppression protection device. Background Art

[0002] Transient Voltage Suppressor (TVS) device is a voltage clamping overvoltage protection device used to protect electronic equipment from damage caused by transient high-energy impact. It can convert the high impedance between its two poles into low impedance at a speed of picoseconds, absorbing surge power of up to several kilowatts, thereby avoiding damage to electronic equipment.

[0003] Current transient voltage suppression devices mainly use a planar structure, and directly form a PN junction on the substrate through heterogeneous doping. The anti-electrostatic discharge (ESD) capability of the planar structure transient voltage suppression device is limited by the size of the die. If you want to further improve the surge protection capability of the device, you can only further increase the die size, which is contrary to the trend of precision miniaturization of devices. In particular, the clamping voltage of the planar structure transient voltage suppression device working at a higher voltage is usually very high, and the surge protection capability is very low.

[0004] Therefore, how to improve the structure of transient voltage suppression protection devices to improve surge protection capabilities and reduce clamping voltage without increasing the die size is an urgent problem to be solved. Utility Model Content

[0005] The utility model aims to provide a transient voltage suppression protection device, which can improve the surge protection capability and reduce the clamping voltage without increasing the size of the tube core.

[0006] To achieve the above object, the utility model provides a transient voltage suppression protection device, comprising:

[0007] substrate;

[0008] an epitaxial layer, located on the substrate;

[0009] At least two isolation trench structures, penetrating the epitaxial layer and extending into the substrate, the at least two isolation trench structures dividing the epitaxial layer into a first region and a second region isolated from each other, the second region surrounding the first region;

[0010] A first doping region and a third doping region, located in the first region, the first doping region penetrates the epitaxial layer and extends into the substrate, the third doping region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, and the first doping region surrounds the third doping region;

[0011] A second doping region and a fourth doping region are located in the second region, the second doping region penetrates the epitaxial layer and extends into the substrate, the fourth doping region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, the second doping region and the fourth doping region surround the first region, and the second doping region is located on at least one side of the fourth doping region;

[0012] A first doped trench structure, wherein the first doped trench structure penetrates the epitaxial layer and extends into the substrate, and the first doped trench structure is located in the first doped region;

[0013] A second doped trench structure, wherein the second doped trench structure penetrates the epitaxial layer and extends into the substrate, and the second doped trench structure is located in the second doped region.

[0014] Optionally, the substrate, the first doping region, the first doping trench structure and the fourth doping region have the same doping type, the epitaxial layer, the second doping region, the second doping trench structure and the third doping region have the same doping type, and the substrate and the epitaxial layer have opposite doping types.

[0015] Optionally, the fourth doped region, the epitaxial layer and the substrate constitute a first transistor, the fourth doped region, the epitaxial layer, the second doped region and the substrate constitute a second triode, the third doped region, the epitaxial layer and the substrate constitute a first diode, the first diode is a Zener diode, and the third doped region, the epitaxial layer, the first doped region and the substrate constitute a second diode.

[0016] Optionally, the first transistor, the second transistor, the first diode and the second diode are connected in parallel, the collector of the first transistor, the collector of the second transistor, the cathode of the first diode and the cathode of the second diode are connected to the power supply end, and the emitter of the first transistor, the emitter of the second transistor, the anode of the first diode and the anode of the second diode are grounded.

[0017] Optionally, the transient voltage suppression protection device includes two second doping regions, wherein one of the second doping regions surrounds the fourth doping region, and the fourth doping region surrounds the other second doping region.

[0018] Optionally, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer from bottom to top.

[0019] Optionally, the resistivity of the substrate is smaller than the resistivity of the first epitaxial layer, and the resistivity of the first epitaxial layer is smaller than the resistivity of the second epitaxial layer.

[0020] Optionally, the isolation trench structure includes:

[0021] an isolation trench penetrating the epitaxial layer and extending into the substrate;

[0022] An isolation layer, located on the inner wall of the isolation trench;

[0023] A polysilicon layer is filled in the isolation trench.

[0024] Optionally, the first doped trench structure includes: a first trench, and a doped polysilicon layer or a doped amorphous silicon layer filling the first trench; the second doped trench structure includes: a second trench, and a doped polysilicon layer or a doped amorphous silicon layer filling the second trench.

[0025] Optionally, the transient voltage suppression protection device further includes:

[0026] an insulating dielectric layer, located on the epitaxial layer, the insulating dielectric layer covering the epitaxial layer, the first doped region, the second doped region and the isolation trench structure, and the insulating dielectric layer having a first opening exposing the third doped region and a second opening exposing the fourth doped region;

[0027] a first electrode, located on the insulating dielectric layer, the first electrode filling the first opening and the second opening, so that the first electrode is connected to the third doping region and the fourth doping region;

[0028] The second electrode is located on a surface of the substrate away from the epitaxial layer.

[0029] Optionally, the transient voltage suppression protection device further includes:

[0030] A passivation layer extends from the insulating dielectric layer to a portion of the first electrode.

[0031] Compared with the prior art, the transient voltage suppression protection device of the utility model comprises: a substrate; an epitaxial layer located on the substrate; at least two isolation trench structures penetrating the epitaxial layer and extending into the substrate, wherein the at least two isolation trench structures divide the epitaxial layer into a first region and a second region isolated from each other, wherein the second region surrounds the first region; a first doped region and a third doped region located in the first region, wherein the first doped region penetrates the epitaxial layer and extends into the substrate, wherein the third doped region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, wherein the first doped region surrounds the third doped region; a second doped region and a fourth doped region located in the second region, wherein the second doped region The doped region penetrates the epitaxial layer and extends into the substrate, the fourth doped region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, the second doped region and the fourth doped region surround the first region, and the second doped region is located on at least one side of the fourth doped region; a first doped trench structure, the first doped trench structure penetrates the epitaxial layer and extends into the substrate, and the first doped trench structure is located in the first doped region; a second doped trench structure, the second doped trench structure penetrates the epitaxial layer and extends into the substrate, and the second doped trench structure is located in the second doped region, so that the surge protection capability can be improved and the clamping voltage can be reduced without increasing the die size. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of a transient voltage suppression protection device according to an embodiment of the utility model;

[0033] Figure 2 yes Figure 1 A top view schematic diagram of a transient voltage suppression protection device shown;

[0034] Figure 3 yes Figure 1 The schematic diagram of the distribution of diodes and transistors in the transient voltage suppression protection device shown;

[0035] Figure 4a yes Figure 1 The circuit diagram of the transient voltage suppression protection device shown;

[0036] Figure 4b It is a circuit diagram of a transient voltage suppression protection device according to another embodiment of the utility model;

[0037] Figure 5a to Figure 5m It is a schematic diagram of various steps of a method for manufacturing a transient voltage suppression protection device according to an embodiment of the utility model.

[0038] Among them, Figure 1 to Figure 5m The reference numerals are described as follows:

[0039] 10-substrate; 11-epitaxial layer; 111-first epitaxial layer; 112-second epitaxial layer; 12-isolation trench structure; 121-mask layer; 13-first doping region; 131-first doping trench structure; 14-second doping region; 141-second doping trench structure; 15-third doping region; 151-injection masking layer; 16-fourth doping region; 17-insulating dielectric layer; 171-first opening; 172-second opening; 181-first electrode; 182-second electrode; 19 passivation layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, advantages and features of the utility model clearer, the transient voltage suppression protection device proposed by the utility model is further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.

[0041] The utility model provides a transient voltage suppression protection device in an embodiment, comprising: a substrate; an epitaxial layer located on the substrate; at least two isolation trench structures, penetrating the epitaxial layer and extending into the substrate, wherein the at least two isolation trench structures divide the epitaxial layer into a first region and a second region isolated from each other, wherein the second region surrounds the first region; a first doped region and a third doped region, located in the first region, wherein the first doped region penetrates the epitaxial layer and extends into the substrate, wherein the third doped region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, wherein the first doped region surrounds the third doped region; a second doped region and a fourth doped region, wherein the first doped region and the third doped region are disposed in the epitaxial layer and extend downward from the surface of the epitaxial layer, wherein the first doped region surrounds the third doped region; region, located in the second region, the second doped region penetrates the epitaxial layer and extends into the substrate, the fourth doped region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, the second doped region and the fourth doped region surround the first region, and the second doped region is located on at least one side of the fourth doped region; a first doped trench structure, the first doped trench structure penetrates the epitaxial layer and extends into the substrate, and the first doped trench structure is located in the first doped region; a second doped trench structure, the second doped trench structure penetrates the epitaxial layer and extends into the substrate, and the second doped trench structure is located in the second doped region.

[0042] See below Figure 1 to Figure 5m The transient voltage suppression protection device provided by this embodiment is described in more detail. Figure 1 and Figure 3 yes Figure 2 A schematic diagram of the longitudinal section along the AA' direction, and Figure 2 Only indicate Figure 1 Part of the structure.

[0043] The epitaxial layer 11 is located on the substrate 10 .

[0044] The substrate 10 and the epitaxial layer 11 may be made of at least one of semiconductor materials such as single crystal silicon, germanium, silicon carbide, and gallium arsenide, but are not limited thereto.

[0045] The epitaxial layer 11 includes a first epitaxial layer 111 and a second epitaxial layer 112 from bottom to top.

[0046] The doping concentration of the substrate 10 is greater than that of the first epitaxial layer 111, and the doping concentration of the first epitaxial layer 111 is greater than that of the second epitaxial layer 112. The substrate 10 and the first epitaxial layer 111 are heavily doped, and the second epitaxial layer 112 is lightly doped.

[0047] The heavily doped substrate 10 can reduce the clamping voltage of the transient voltage suppression protection device, the first epitaxial layer 111 can adjust the voltage of the voltage regulator, and the second epitaxial layer 112 can reduce the parasitic capacitance of the transient voltage suppression protection device. In some embodiments, the epitaxial layer 11 may only include the first epitaxial layer 111, but not the second epitaxial layer 112.

[0048] The resistivity of the substrate 10 is smaller than that of the first epitaxial layer 111, and the resistivity of the first epitaxial layer 111 is smaller than that of the second epitaxial layer 112. The resistivity ρ1 of the substrate 10 may be in the range of 0.001Ω·cm≤ρ1≤0.05Ω·cm, the resistivity ρ2 of the first epitaxial layer 111 may be in the range of 0.01Ω·cm≤ρ2≤1Ω·cm, and the resistivity ρ3 of the second epitaxial layer 112 may be in the range of 0.1Ω·cm≤ρ3≤1000Ω·cm.

[0049] The thickness of the first epitaxial layer 111 may be 3 μm to 8 μm, and the thickness of the second epitaxial layer 112 may be 5 μm to 12 μm.

[0050] At least two isolation trench structures 12 penetrate the epitaxial layer 11 and extend into the substrate 10 . The at least two isolation trench structures 12 divide the epitaxial layer 11 into a first region and a second region which are isolated from each other. The second region surrounds the first region.

[0051] At least one isolation trench structure 12 is used to isolate the second region from a region outside the second region, and at least one isolation trench structure 12 is used to isolate the second region from the first region. By increasing the number of the isolation trench structures 12, the isolation effect can be enhanced.

[0052] In one embodiment, the isolation trench structure 12 may include: an isolation trench (not shown), the isolation trench penetrating the epitaxial layer 11 and extending into the substrate 10; an isolation layer (not shown), located on the inner wall of the isolation trench; and a polysilicon layer (not shown), filling the isolation trench. The thickness of the isolation layer may be

[0053] Alternatively, in another embodiment, the isolation trench structure 12 may include: an isolation trench (not shown), the isolation trench penetrating the epitaxial layer 11 and extending into the substrate 10; and an isolation layer, the isolation layer filling the isolation trench.

[0054] The isolation layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.

[0055] The first doping region 13 and the third doping region 15 are located in the first area. The first doping region 13 penetrates the epitaxial layer 11 and extends into the substrate 10 . The third doping region 15 is located in the epitaxial layer 11 and extends downward from the surface of the epitaxial layer 11 . The first doping region 13 surrounds the third doping region 15 .

[0056] The third doping region 15 is located in the second epitaxial layer 112 .

[0057] The second doping region 14 and the fourth doping region 16 are located in the second area, the second doping region 14 penetrates the epitaxial layer 11 and extends into the substrate 10, the fourth doping region 16 is located in the epitaxial layer 11 and extends downward from the surface of the epitaxial layer 11, the second doping region 14 and the fourth doping region 16 surround the first area, and the second doping region 14 is located on at least one side of the fourth doping region 16.

[0058] The fourth doping region 16 is located in the second epitaxial layer 112 .

[0059] The transient voltage suppression protection device also includes:

[0060] A first doped trench structure 131, wherein the first doped trench structure 131 penetrates the epitaxial layer 11 and extends into the substrate 10, and the first doped trench structure 131 is located in the first doped region 13;

[0061] The second doped trench structure 141 penetrates the epitaxial layer 11 and extends into the substrate 10 . The second doped trench structure 141 is located in the second doped region 14 .

[0062] The first doped trench structure 131 may include: a first trench (not shown), a doped polysilicon layer or a doped amorphous silicon layer filling the first trench; the second doped trench structure 141 may include: a second trench (not shown), a doped polysilicon layer or a doped amorphous silicon layer filling the second trench.

[0063] By adopting an annealing process, the doping ions in the first doping trench structure 131 are diffused to form the first doping region 13 , and the doping ions in the second doping trench structure 141 are diffused to form the second doping region 14 .

[0064] The first doping region 13 , the second doping region 14 , the third doping region 15 and the fourth doping region 16 are heavily doped.

[0065] The depth of the isolation trench structure 12 may be greater than, less than, or equal to the depths of the first doping region 13 and the second doping region 14 .

[0066] Preferably, the isolation trench structure 12 is not in contact with the first doping region 13 and the second doping region 14 to enhance the isolation effect.

[0067] The substrate 10, the first doping region 13, the first doping trench structure 131 and the fourth doping region 16 have the same doping type, the epitaxial layer 11, the second doping region 14, the second doping trench structure 141 and the third doping region 15 have the same doping type, and the substrate 10 and the epitaxial layer 11 have opposite doping types. When the doping type of the substrate 10, the first doping region 13, the first doping trench structure 131 and the fourth doping region 16 is N-type, the doping type of the epitaxial layer 11, the second doping region 14, the second doping trench structure 141 and the third doping region 15 is P-type; when the doping type of the substrate 10, the first doping region 13, the first doping trench structure 131 and the fourth doping region 16 is P-type, the doping type of the epitaxial layer 11, the second doping region 14, the second doping trench structure 141 and the third doping region 15 is N-type.

[0068] like Figure 3 As shown, taking the doping type of the substrate 10, the first doping region 13, the first doping trench structure 131 and the fourth doping region 16 as N-type, and the doping type of the epitaxial layer 11, the second doping region 14, the second doping trench structure 141 and the third doping region 15 as P-type as an example, the fourth doping region 16, the epitaxial layer 11 and the substrate 10 constitute a first triode T1, and the fourth doping region 16, the epitaxial layer 11, the second doping region 14 and the substrate 10 constitute a second triode ( Figure 3 The second transistor shown includes a second transistor T2 and a second transistor T3), the third doped region 15, the epitaxial layer 11 and the substrate 10 constitute a first diode D1, the first diode D1 is a Zener diode, and the third doped region 15, the epitaxial layer 11, the first doped region 13 and the substrate 10 constitute a second diode D2.

[0069] like Figure 3 , Figure 4a and Figure 4b As shown, the first transistor T1 and the second transistor ( Figure 3 and Figure 4a The second transistor shown includes a second transistor T2 and a second transistor T3, Figure 4b The second transistor shown includes a second transistor T2), the first diode D1 and the second diode D2 are connected in parallel, the collector of the first transistor T1, the collector of the second transistor, the cathode of the first diode D1 and the cathode of the second diode D2 are connected to the power supply terminal Vcc, the emitter of the first transistor T1, the emitter of the second transistor, the anode of the first diode D1 and the anode of the second diode D2 are grounded GND, and the base of the first transistor T1 and the base of the second transistor are open.

[0070] The first epitaxial layer 111 can adjust the voltage of the first diode D1 .

[0071] The first doping region 13 is not in contact with the third doping region 15, so as to avoid causing the operating voltage of the second diode D2 to drop to less than the breakdown voltage of the first diode D1, thereby avoiding the breakdown position from changing from the inside of the transient voltage suppression protection device to the surface; the second doping region 14 is not in contact with the fourth doping region 16, so as to avoid affecting the operating voltage of the second transistor.

[0072] Preferably, Figure 3 and Figure 4a As shown, the transient voltage suppression protection device includes two second doping regions 14, one of which surrounds the fourth doping region 16, and the fourth doping region 16 surrounds the other second doping region 14. At this time, two second triodes are formed, namely the second triode T2 and the second triode T3. The second triode T2 and the second triode T3 are connected in parallel to make the current distribution more uniform, so that the device is not easy to burn. In other embodiments, the transient voltage suppression protection device may include one second doping region 14, and the second doping region 14 may be located on the inner side or the outer side of the fourth doping region 16. At this time, one second triode T2 (such as Figure 4b as shown) or the second transistor T3.

[0073] The isolation trench structure 12, the first doping region 13, the second doping region 14 and the fourth doping region 16 are all closed rings, and the shape of the ring can be rectangular, circular or polygonal, etc.; the cross-sectional shape of the third doping region 15 can be rectangular, circular or polygonal, etc.

[0074] In one embodiment, the first doped trench structure 131 may include at least one first trench, the second doped trench structure 141 may include at least one second trench, and the first trench and the second trench are closed rings, that is, the first doped trench structure 131 and the second doped trench structure 141 are closed rings.

[0075] In another embodiment, the first doped groove structure 131 may include a plurality of first grooves, and the plurality of first grooves are arranged at intervals to form a non-closed ring, that is, the first doped groove structure 131 is a non-closed ring, so that the first doped region 13 formed after the doped ions in the first doped groove structure 131 diffuse into a closed ring; the second doped groove structure 141 may include a plurality of second grooves, and the plurality of second grooves are arranged at intervals to form a non-closed ring, that is, the second doped groove structure 141 is a non-closed ring, so that the second doped region 14 formed after the doped ions in the second doped groove structure 141 diffuse into a closed ring; wherein the cross-sectional shapes of the first groove and the second groove may be rectangular, circular, polygonal, or the like.

[0076] The transient voltage suppression protection device also includes: an insulating dielectric layer 17, which is located on the epitaxial layer 11, and the insulating dielectric layer 17 covers the epitaxial layer 11, the first doping region 13, the second doping region 14 and the isolation trench structure 12, and the insulating dielectric layer 17 has a first opening 171 exposing the third doping region 15 and a second opening 172 exposing the fourth doping region 16.

[0077] The transient voltage suppression protection device may further include: an implantation masking layer 151 located between the epitaxial layer 11 and the insulating dielectric layer 17 , wherein the implantation masking layer 151 is used to protect the surface of the epitaxial layer 11 when ion implantation is performed to form the third doping region 15 and the fourth doping region 16 .

[0078] The thickness of the implantation masking layer 151 can be

[0079] The transient voltage suppression protection device also includes:

[0080] A first electrode 181 is located on the insulating dielectric layer 17 , and the first electrode 181 fills the first opening 171 and the second opening 172 , so that the first electrode 181 is connected to the third doping region 15 and the fourth doping region 16 ;

[0081] The second electrode 182 is located on a surface of the substrate 10 away from the epitaxial layer 11 .

[0082] The transient voltage suppression protection device also includes:

[0083] The passivation layer 19 extends from the insulating dielectric layer 17 to a portion of the first electrode 181 .

[0084] Since there are many particulate impurities in the environment when the tube core is packaged, the passivation layer 19 is extended from the insulating dielectric layer 17 to the first electrode 181, so that the junction between the edge of the first electrode 181 and the insulating dielectric layer 17 can be covered by the passivation layer 19, thereby preventing particulate impurities from entering the interior of the transient voltage suppression protection device from the junction.

[0085] The injection masking layer 151 and the insulating dielectric layer 17 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0086] In addition, to form Figure 1 For example, see the transient voltage suppression protection device shown in Figure 5a to Figure 5m , the manufacturing method of the transient voltage suppression protection device may include:

[0087] First, if Figure 5a As shown, a substrate 10 is provided;

[0088] Then, if Figure 5b As shown, a first epitaxial layer 111 and a second epitaxial layer 112 are sequentially formed on the substrate 10 by an epitaxial growth process, and the first epitaxial layer 111 and the second epitaxial layer 112 constitute an epitaxial layer 11;

[0089] Then, if Figure 5c As shown, a mask layer 121 is deposited on the second epitaxial layer 112 , and the thickness of the mask layer 121 may be 0.5 μm to 1 μm;

[0090] Then, a photolithography and etching process is performed to form a third opening (not shown) in the mask layer 121, and the epitaxial layer 11 and the substrate 10 exposed by the third opening are sequentially etched using the etched mask layer 121 as a mask to form an isolation trench, wherein the isolation trench penetrates the epitaxial layer 11 and extends into the substrate 10, and an isolation layer is grown on the inner wall of the isolation trench and a polysilicon layer is filled in the isolation trench, and then the polysilicon layer covering the surface of the mask layer 121 is removed by etching or chemical mechanical polishing, and the isolation layer and the polysilicon layer in the isolation trench constitute Figure 5d The isolation trench structure 12 shown, wherein the isolation trench structure 12 divides the epitaxial layer 11 into a first region and a second region isolated from each other;

[0091] Then, a photolithography and etching process is performed to form a fourth opening (not shown) in the mask layer 121 on the first region, and the epitaxial layer 11 and the substrate 10 exposed by the fourth opening are sequentially etched using the etched mask layer 121 as a mask to form a first trench, wherein the first trench penetrates the epitaxial layer 11 and extends into the substrate 10, and the first trench is filled with a doped polysilicon layer or a doped amorphous silicon layer, and then an etching or chemical mechanical polishing process is used to remove the doped polysilicon layer or the doped amorphous silicon layer covering the surface of the mask layer 121, and the doped polysilicon layer or the doped amorphous silicon layer in the first trench serves as a substrate. Figure 5e The first doped trench structure 131 is shown;

[0092] Then, a photolithography and etching process is performed to form a fifth opening (not shown) in the mask layer 121 on the second area, and the epitaxial layer 11 and the substrate 10 exposed by the fifth opening are sequentially etched using the etched mask layer 121 as a mask to form a second trench, wherein the second trench penetrates the epitaxial layer 11 and extends into the substrate 10, and the second trench is filled with a doped polysilicon layer or a doped amorphous silicon layer, and then an etching or chemical mechanical polishing process is used to remove the doped polysilicon layer or the doped amorphous silicon layer covering the surface of the mask layer 121, and the doped polysilicon layer or the doped amorphous silicon layer in the second trench serves as a substrate. Figure 5f The second doped trench structure 141 is shown;

[0093] Then, if Figure 5gAs shown, an annealing process is performed so that the doping ions in the first doped trench structure 131 are diffused to form a first doped region 13, and the doping ions in the second doped trench structure 141 are diffused to form a second doped region 14, the first doped region 13 wraps the first doped trench structure 131, and the second doped region 14 wraps the second doped trench structure 141, the annealing temperature may be 1050° C. to 1150° C., and the annealing time may be 2 h to 5 h;

[0094] Then, if Figure 5h As shown, the mask layer 121 and the isolation trench structure 12 , the first doped trench structure 131 and the second doped trench structure 141 above the surface of the second epitaxial layer 112 are removed;

[0095] Then, if Figure 5i As shown, a thermal oxidation process is performed to grow an implantation masking layer 151 on the surface of the second epitaxial layer 112 , the isolation trench structure 12 , the first doped trench structure 131 , and the second doped trench structure 141 ;

[0096] Then, if Figure 5j As shown, a patterned photoresist layer (not shown) is formed on the implantation masking layer 151, and selective ion implantation is performed into the second epitaxial layer 112 using the patterned photoresist layer as a mask and an annealing process is performed, so that the third doping region 15 is formed in the region surrounded by the first doping region 13 and the fourth doping region 16 is formed in the region surrounded by the second doping region 14, wherein the ion implantation dose can be 1E15cm -2 ~1E16cm -2 , the annealing temperature can be 1050℃~1150℃, and the annealing time can be 2h~5h;

[0097] Then, if Figure 5k As shown, an insulating dielectric layer 17 is deposited on the injection masking layer 151, and a first opening 171 and a second opening 172 are formed in the insulating dielectric layer 17 and the injection masking layer 151 by photolithography and etching processes, wherein the first opening 171 exposes the third doping region 15, and the second opening 172 exposes the fourth doping region 16;

[0098] Then, if Figure 5l As shown, a metal material is deposited on the insulating dielectric layer 17, and the metal material fills the first opening 171 and the second opening 172, and a photolithography and etching process is performed on the metal material to form a first electrode 181;

[0099] Then, if Figure 5mAs shown, a passivation layer 19 is formed by deposition, and the passivation layer 19 extends from the insulating dielectric layer 17 to a portion of the first electrode 181;

[0100] Then, if Figure 5m As shown, the surface of the substrate 10 away from the epitaxial layer 11 is thinned, and a second electrode 182 is formed on the surface of the substrate 10 away from the epitaxial layer 11 to prepare an integrated unidirectional low-capacitance transient voltage suppression protection device.

[0101] From the above content, it can be known that the transient voltage suppression protection device of the utility model, since the first area of ​​the epitaxial layer 11 forms the third doping area 15, and the second area of ​​the epitaxial layer 11 forms the fourth doping area 16, the transient voltage suppression protection device includes the first diode D1 and the first transistor T1; wherein, when the current flows from the second electrode 182, the substrate 10 and the epitaxial layer 11 are first broken down, the first diode D1 undergoes avalanche breakdown, and the current flows from the third doping area 15 into the first electrode 181 and is in the epitaxial layer 1 1, and at the same time, the collector junction of the first transistor T1 is turned on; when the current further increases, the holes swept into the base of the first transistor T1 also fill the collector junction space charge region at the same time, making it narrower, thereby reducing the reverse bias of the collector junction; when the parasitic voltage drop on the epitaxial layer 11 is greater than the turn-on voltage of the emitter junction of the first transistor T1, since the first transistor T1 is already turned on, the current at this time no longer needs to rely on the avalanche multiplication effect to generate, so the collector voltage will quickly drop to the turn-on voltage of the first transistor T1, and a negative resistance retrace phenomenon will occur.

[0102] Furthermore, since the first doping region 13 is formed on the periphery of the third doping region 15 and the second doping region 14 is formed on the periphery of the fourth doping region 16, the transient voltage suppression protection device adds the second diode D2 and the second transistor (i.e., the second transistor T2 and / or the second transistor T3) without increasing the core area, so that in addition to the above-mentioned current flow path, the current can also flow through the first doping region 13 and the second doping region 14, that is, the current is shunted through the first doping region 13 and the second doping region 14, and the first doping region 13 and the second doping region 14 have low resistivity and strong conductivity, which is equivalent to adding a low-resistance channel, thereby significantly enhancing the surge protection capability and significantly reducing the clamping voltage.

[0103] Under the condition of the same area, compared with setting a PN junction, by setting the first doped region 13 and the second doped region 14, the clamping voltage can be reduced by about 30%, and the reverse pulse peak current (Ipp) can be increased by 20-50%, which can significantly improve the reverse protection capability of the transient voltage suppression protection device.

[0104] Moreover, since the first doping region 13 is formed on the periphery of the third doping region 15, the forward surge capability can be significantly improved and the forward voltage drop can be reduced; by controlling the doping concentration of the first doping groove structure 131, the doping concentration of the first doping region 13 can be controlled, and then a sudden junction can be easily achieved, thereby better controlling the voltage breakdown characteristics.

[0105] Furthermore, when two unidirectional transient voltage suppression protection devices are sealed together (ie, the first electrodes 181 of the two unidirectional transient voltage suppression protection devices are electrically connected together via bonding wires) to form a bidirectional transient voltage suppression protection device, the advantages are particularly prominent.

[0106] In summary, the transient voltage suppression protection device of the utility model includes: a substrate; an epitaxial layer, located on the substrate; at least two isolation trench structures, penetrating the epitaxial layer and extending into the substrate, the at least two isolation trench structures dividing the epitaxial layer into a first region and a second region isolated from each other, the second region surrounding the first region; a first doped region and a third doped region, located in the first region, the first doped region penetrating the epitaxial layer and extending into the substrate, the third doped region located in the epitaxial layer and extending downward from the surface of the epitaxial layer, the first doped region surrounding the third doped region; a second doped region and a fourth doped region , located in the second region, the second doped region penetrates the epitaxial layer and extends into the substrate, the fourth doped region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, the second doped region and the fourth doped region surround the first region, and the second doped region is located on at least one side of the fourth doped region; a first doped trench structure, the first doped trench structure penetrates the epitaxial layer and extends into the substrate, and the first doped trench structure is located in the first doped region; a second doped trench structure, the second doped trench structure penetrates the epitaxial layer and extends into the substrate, and the second doped trench structure is located in the second doped region. The transient voltage suppression protection device of the utility model can improve the surge protection capability and reduce the clamping voltage without increasing the die size.

[0107] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of the utility model. Any changes and modifications made by ordinary technicians in the field of the utility model based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A transient voltage suppression protection device, characterized in that: include: substrate; an epitaxial layer, located on the substrate; At least two isolation trench structures, penetrating the epitaxial layer and extending into the substrate, the at least two isolation trench structures dividing the epitaxial layer into a first region and a second region isolated from each other, the second region surrounding the first region; A first doping region and a third doping region, located in the first region, the first doping region penetrates the epitaxial layer and extends into the substrate, the third doping region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, and the first doping region surrounds the third doping region; A second doping region and a fourth doping region are located in the second region, the second doping region penetrates the epitaxial layer and extends into the substrate, the fourth doping region is located in the epitaxial layer and extends downward from the surface of the epitaxial layer, the second doping region and the fourth doping region surround the first region, and the second doping region is located on at least one side of the fourth doping region; A first doped trench structure, wherein the first doped trench structure penetrates the epitaxial layer and extends into the substrate, and the first doped trench structure is located in the first doped region; A second doped trench structure, wherein the second doped trench structure penetrates the epitaxial layer and extends into the substrate, and the second doped trench structure is located in the second doped region.

2. The transient voltage suppression protection device according to claim 1, characterized in that: The substrate, the first doping region, the first doping trench structure and the fourth doping region have the same doping type, the epitaxial layer, the second doping region, the second doping trench structure and the third doping region have the same doping type, and the substrate and the epitaxial layer have opposite doping types.

3. The transient voltage suppression protection device according to claim 2, characterized in that: The fourth doped region, the epitaxial layer and the substrate constitute a first triode, the fourth doped region, the epitaxial layer, the second doped region and the substrate constitute a second triode, the third doped region, the epitaxial layer and the substrate constitute a first diode, the first diode is a Zener diode, and the third doped region, the epitaxial layer, the first doped region and the substrate constitute a second diode.

4. The transient voltage suppression protection device according to claim 3, characterized in that: The first transistor, the second transistor, the first diode and the second diode are connected in parallel, the collector of the first transistor, the collector of the second transistor, the cathode of the first diode and the cathode of the second diode are connected to the power supply end, and the emitter of the first transistor, the emitter of the second transistor, the anode of the first diode and the anode of the second diode are grounded.

5. The transient voltage suppression protection device according to claim 1, characterized in that: The transient voltage suppression protection device includes two second doping regions, wherein one of the second doping regions surrounds the fourth doping region, and the fourth doping region surrounds the other second doping region.

6. The transient voltage suppression protection device according to claim 1, characterized in that: The epitaxial layer includes a first epitaxial layer and a second epitaxial layer from bottom to top.

7. The transient voltage suppression protection device according to claim 6, characterized in that: The resistivity of the substrate is lower than that of the first epitaxial layer, and the resistivity of the first epitaxial layer is lower than that of the second epitaxial layer.

8. The transient voltage suppression protection device according to claim 1, characterized in that: The isolation trench structure comprises: an isolation trench penetrating the epitaxial layer and extending into the substrate; An isolation layer, located on the inner wall of the isolation trench; A polysilicon layer is filled in the isolation trench.

9. The transient voltage suppression protection device according to claim 1, characterized in that: The first doped trench structure includes: a first trench, and a doped polysilicon layer or a doped amorphous silicon layer filling the first trench; the second doped trench structure includes: a second trench, and a doped polysilicon layer or a doped amorphous silicon layer filling the second trench.

10. The transient voltage suppression protection device according to claim 1, characterized in that: The transient voltage suppression protection device also includes: an insulating dielectric layer, located on the epitaxial layer, the insulating dielectric layer covering the epitaxial layer, the first doped region, the second doped region and the isolation trench structure, and the insulating dielectric layer having a first opening exposing the third doped region and a second opening exposing the fourth doped region; a first electrode, located on the insulating dielectric layer, the first electrode filling the first opening and the second opening, so that the first electrode is connected to the third doping region and the fourth doping region; The second electrode is located on a surface of the substrate away from the epitaxial layer.

11. The transient voltage suppression protection device according to claim 10, characterized in that: The transient voltage suppression protection device also includes: A passivation layer extends from the insulating dielectric layer to a portion of the first electrode.

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