Semiconductor device

Abstract

A semiconductor device includes a stack of first nanostructures, a first gate structure, a plurality of stacks of second nanostructures, a second gate structure, and a first isolation structure. The first nanostructures each include a channel region of a first width; the first gate structure is located on the stack of the first nanostructures and surrounds each of the first nanostructures, and the distance from the first tail end of the first gate structure to the adjacent first nanostructure is a first distance; a stack of second nanostructures, the second nanostructures each comprising a channel region of a second width greater than the first width; a second gate structure on the stack of second nanostructures and surrounding each of the second nanostructures, the distance from the first end of the second gate structure to the adjacent second nanostructure being a second distance greater than the first distance; the first isolation structure continuously extends from a first end of the first gate structure to a first end of the second gate structure.

Description

Technical Field

[0001] The embodiments of the utility model relate to semiconductor technology, and more particularly to semiconductor devices. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography techniques to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest feature, so that more components can be integrated into a given area. However, when the size of the smallest feature is reduced, additional problems that should be solved emerge. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor device to solve at least one of the above problems.

[0005] In some embodiments, a semiconductor device is provided, which includes a stack of multiple first nanostructures located on a substrate, wherein each of the multiple first nanostructures includes a channel region having a first width; a first gate structure located on the stack of the multiple first nanostructures, wherein the first gate structure surrounds each of the multiple first nanostructures, wherein the distance from the first end of the first gate structure to an adjacent first nanostructure is a first distance; a stack of multiple second nanostructures located on the substrate, wherein each of the multiple second nanostructures includes a channel region having a second width greater than the first width; a second gate structure located on the stack of the multiple second nanostructures, wherein the second gate structure surrounds each of the multiple second nanostructures, wherein the distance from the first end of the second gate structure to an adjacent second nanostructure is a second distance, and the second distance is greater than the first distance; and a first isolation structure extending continuously from the first end of the first gate structure to the first end of the second gate structure.

[0006] According to one embodiment of the present invention, the first gate structure and the second gate structure are on the same side of the first isolation structure.

[0007] According to one embodiment of the present invention, it further includes: a second isolation structure located between the first gate structure and the second gate structure, wherein the second isolation structure is a dummy gate structure.

[0008] According to one embodiment of the present invention, it also includes: a stack of multiple third nanostructures, wherein the second gate structure surrounds each of the multiple third nanostructures, wherein the distance from the second end of the second gate structure to an adjacent third nanostructure is a third distance, and the third distance is greater than the first distance.

[0009] According to one embodiment of the present invention, the first gate structure extends along a first direction, and the first isolation structure extends along a second direction perpendicular to the first direction.

[0010] According to one embodiment of the present invention, a first portion of the first isolation structure at the first end of the first gate structure protrudes from a second portion of the first isolation structure at the first end of the second gate structure.

[0011] In some embodiments, a semiconductor device is provided, the semiconductor device comprising a first complementary metal oxide semiconductor device, comprising: a first nanostructure, wherein the first nanostructure is of a first type and has a first width; a second nanostructure adjacent to a first side of the first nanostructure, wherein the second nanostructure is of a second type and has a second width less than the first width; a third nanostructure adjacent to a second side of the first nanostructure, wherein the third nanostructure is of a second type and has a second width; and a first gate structure extending over and surrounding the first, second and third nanostructures; a second complementary metal oxide semiconductor device adjacent to the first complementary metal oxide semiconductor device, the second complementary metal oxide semiconductor device comprising: a fourth nanostructure having a third width less than the second width; and a second gate structure extending over and surrounding the fourth nanostructure; a plurality of isolation structures separating the first gate structure from the second gate structure; and a gate end isolation region physically contacting the first gate structure and the second gate structure, wherein the gate end isolation region is adjacent to the second and fourth nanostructures, wherein a first distance from the second nanostructure to the gate end isolation region is greater than a second distance from the fourth nanostructure to the gate end isolation region.

[0012] According to one embodiment of the present invention, the gate end isolation region extends to a depth below the first gate structure and the second gate structure in a range of 10 nm to 150 nm.

[0013] According to one embodiment of the present invention, the plurality of isolation structures are parallel to the first gate structure and the second gate structure.

[0014] According to one embodiment of the present invention, it further includes: a dummy fin located between adjacent pairs of isolation structures of the plurality of isolation structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0016] Figure 1 An example of a nanostructure field-effect transistor (nano-FET) is shown in a three-dimensional view according to some embodiments.

[0017] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B and Fig.24C FIG. 4 is a schematic cross-sectional view of an intermediate stage in the fabrication of a nanostructured field effect transistor according to some embodiments.

[0018] Fig.25 , Fig.26A and Fig.26B Schematic diagrams of a plan view and a cross-section of a device including a nanostructure field effect transistor according to some embodiments.

[0019] Fig. 27 FIG. 1 is a plan view of a device including a nanostructure field effect transistor according to some embodiments.

[0020] Fig.28 FIG. 1 is a plan view of a device including a nanostructure field effect transistor according to some embodiments.

[0021] Fig.29 , Fig. 30A , Fig. 30B , Fig.31A and Fig.31B Schematic diagrams of a plan view and a cross-section of a device including a nanostructure field effect transistor according to some embodiments.

[0022] Fig.32 FIG. 1 is a plan view of a device including a nanostructure field effect transistor according to some embodiments.

[0023] Fig.33 , Fig.34A and Fig.34B Schematic diagrams of a plan view and a cross-section of a device including a nanostructure field effect transistor according to some embodiments.

[0024] Fig.35 FIG. 4 is a schematic cross-sectional view of a device including a nanostructure field effect transistor according to some embodiments. DETAILED DESCRIPTION

[0025] It should be understood that the following disclosure provides many different embodiments or examples to implement different parts of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the utility model. For example, the size of the component is not limited to the scope or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed in direct contact, and may also include an additional component that can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the appearance structure.

[0026] Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used to conveniently describe the relationship of one element or component to another (plural) element or component in the drawings. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used would be interpreted accordingly.

[0027] Various embodiments describe forming a device including a plurality of nanostructure field effect transistors, the nanostructure field effect transistors having various channels of various widths and gate structures of various sizes. For example, the device may have a first nanostructure field effect transistor with a smaller channel width and a second nanostructure field effect transistor with a larger channel width. In some embodiments, the nanostructure field effect transistor is a complementary metal oxide semiconductor (CMOS) configuration, wherein an n-type nanostructure field effect transistor and a p-type nanostructure field effect transistor share a single continuous gate structure. The gate end distance between the channel and the end of the gate structure of the nanostructure field effect transistor can be controlled according to the channel width of the nanostructure field effect transistor. For example, a nanostructure field effect transistor with a smaller channel width can be formed with a smaller gate end distance to reduce capacitance, while a nanostructure field effect transistor with a larger channel width can be formed with a larger gate end distance to reduce resistance. The gate end distance can be controlled by controlling the size and position of the gate cut isolation region. The embodiments herein describe forming a device including different nanostructure field effect transistors with different gate end distances, which can allow for improved device performance.

[0028] Embodiments of dies including nanostructured field effect transistors are described below in a specific context. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in place of or in combination with nanostructured field effect transistors.

[0029] Figure 1An example of a nanostructure field effect transistor (e.g., a nanowire field effect transistor, a nanosheet field effect transistor (Nano-FETs), a gate-all-around (GAA) field effect transistor, or the like) in a three-dimensional view is shown in accordance with some embodiments. The alternative nanostructure field effect transistor includes a nanostructure 55 (e.g., a nanosheet, a nanowire, or the like) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nanostructure field effect transistor. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination of the foregoing. A shallow trench isolation region 68 is disposed between adjacent fins 66, and the fins 66 protrude above the adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 and the substrate 50 are described / shown separately, the term "substrate" as used herein may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. In addition, although the fins 66 and the substrate 50 are shown as a single, continuous material, the fins 66 / or the substrate 50 may include a single material or multiple materials. Herein, the fin 66 may refer to a portion extending between adjacent shallow trench isolation regions 68 .

[0030] The gate dielectric layer 100 is over the top surface of the fin 66 and extends along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is over the gate dielectric layer 100. The epitaxial source / drain regions 92 are disposed on the fin 66 on both sides of the gate dielectric layer 100 and the gate electrode 102. Depending on the context, the epitaxial source / drain regions 92 may represent a source or a drain, either individually or collectively.

[0031] Figure 1 Reference cross sections for subsequent figures are further shown. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanostructure field effect transistor. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanostructure field effect transistor and in a direction, for example, of current flow between epitaxial source / drain regions 92 of the nanostructure field effect transistor. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanostructure field effect transistor. For clarity, subsequent figures refer to these reference cross sections.

[0032] Some embodiments described herein are discussed in the context of nanostructured field effect transistors formed using a gate-first process. In other embodiments, a gate-last process may be used. Fig.35 Example embodiments are described that are fabricated using a gate-last process. Furthermore, some embodiments contemplate aspects for use in planar devices, such as planar field effect transistors or fin field effect transistors (FinFETs).

[0033] Figures 2 to 24C FIG. 4 is a schematic cross-sectional view of an intermediate stage in the fabrication of a nanostructured field effect transistor according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A show Figure 1 Reference section A-A'. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B and Fig. 24B show Figure 1 Reference section BB'. Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig. 22C , Fig.23C and Fig.24C show Figure 1 Reference section C-C'.

[0034] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate or the like, and the substrate 50 may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, a semiconductor-on-insulator substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer or the like. The insulating layer is provided on a substrate, generally a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP) or a combination of the foregoing.

[0035] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor (e.g., an n-type nanostructure field effect transistor). The p-type region 50P can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor (e.g., a p-type nanostructure field effect transistor). The n-type region 50N can be physically separated from the p-type region 50P (by the shown separation line 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. In other cases, the n-type region 50N can be adjacent to or continuous with the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0036] Furthermore, in Figure 2In the embodiment, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A, 51B, 51C (collectively referred to as first semiconductor layers) and second semiconductor layers 53A, 53B, 53C (collectively referred to as second semiconductor layers). For purposes of illustration, and as discussed in more detail below, the first semiconductor layers 51A, 51B, 51C are removed and the second semiconductor layers 53A, 53B, 53C are patterned to form a channel region of a nanostructure field effect transistor in an n-type region 50N and a channel region of a nanostructure field effect transistor in a p-type region 50P. In other embodiments, the second semiconductor layers 53A, 53B, 53C may be removed and the first semiconductor layers 51A, 51B, 51C may be patterned to form a channel region of a nanostructure field effect transistor in an n-type region 50N and / or a channel region of a nanostructure field effect transistor in a p-type region 50P. In some embodiments, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (eg, silicon or other semiconductor materials) and may be formed at the same time.

[0037] For illustration purposes, the multilayer stack 64 is shown as three layers of the first semiconductor layer and three layers of the second semiconductor layer. In other embodiments, the multilayer stack 64 may include other numbers of the first semiconductor layer and the second semiconductor layer. Each layer of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. Other deposition processes may also be used, such as low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), combinations of the foregoing, or the like. In various embodiments, the first semiconductor layer 51A, 51B, 51C may be formed of a first semiconductor material, such as silicon germanium or the like, and the second semiconductor layer 53A, 53B, 53C may be formed of a second semiconductor material, such as silicon, silicon carbon or the like. Other semiconductor materials or combinations of the foregoing may be possible. In some embodiments, the layers of the multilayer stack 64 may have a thickness in the range of about 4 nm to about 20 nm, but other thicknesses may also be possible. In some embodiments, different layers of the multilayer stack 64 may have different thicknesses.

[0038] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. In this way, the first semiconductor layer 51A, 51B, 51C of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53A, 53B, 53C of the second semiconductor material, thereby allowing the second semiconductor layer 53A, 53B, 53C to be patterned to form a channel region of the nanostructure field effect transistor.

[0039] Please refer to Figure 3 According to some embodiments, the fin 66 is formed in the substrate 50 and the nanostructure 55 is formed in the multilayer stack 64. In some embodiments, the nanostructure 55 and the fin 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching grooves in the multilayer stack 64 and the substrate 50. The etching can be any suitable etching process, such as reactive ion etching (RIE), neutron beam etching (NBE), the like, or a combination of the foregoing. The etching can be anisotropic. The nanostructure 55 formed by etching the multilayer stack 64 can further define a first nanostructure 52A, 52B, 52C (collectively referred to as a first nanostructure) from the first semiconductor layer 51A, 51B, 51C, and define a second nanostructure 54A, 54B, 54C (collectively referred to as a second nanostructure) from the second semiconductor layer 53A, 53B, 53C. The first nanostructures 52A, 52B, 52C and the second nanostructures 54A, 54B, 54C may be collectively referred to as nanostructures 55 .

[0040] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, the fins 66 and nanostructures 55 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0041] For display purposes, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or less than the fins 66 in the p-type region 50P. Again, each fin 66 and nanostructure 55 is shown to have a uniform width, but in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 increases continuously in a direction toward the substrate 50. In these embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape. In some embodiments, the fins 66 may have a width in the range of about 5 nm to about 100 nm, but other widths are possible.

[0042] exist Figure 4 , a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The shallow trench isolation region 68 may be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55 and between adjacent fins 66. The insulating material may be an oxide, such as silicon oxide, nitride, the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the embodiment shown, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. After the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, in some embodiments, multiple layers of insulating material may be used. For example, in some embodiments, a liner (not shown individually) may be first formed along the surface of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a fill material, such as those discussed above, may be formed over the liner.

[0043] Next, a removal process is performed on the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination of the foregoing, or the like. After the planarization process is completed, the planarization process exposes the nanostructure 55 so that the top surface of the nanostructure 55 is flush with the top surface of the insulating material.

[0044] Next, the insulating material is recessed to form shallow trench isolation regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent shallow trench isolation regions 68. Furthermore, the top surface of the shallow trench isolation region 68 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a recess), or a combination thereof. The top surface of the shallow trench isolation region 68 may be formed into a flat surface, a convex shape, and / or a concave shape by suitable etching. The shallow trench isolation region 68 may be recessed by using a suitable etching process, such as an etching process that is selective to the material of the insulating material (e.g., an etching rate for etching the insulating material is greater than an etching rate for etching the material of the fin 66 and the nanostructure 55). For example, oxide removal may be performed using, for example, dilute hydrofluoric (dHF).

[0045] refer to Figures 2 to 4 The process described is only one example of how to form the fin 66 and the nanostructure 55. In some embodiments, the fin 66 and / or the nanostructure 55 are formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or the nanostructure 55. The epitaxial structure may include alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may obviate the need for prior and / or subsequent implantation, although in situ and implantation doping may be used together.

[0046] In addition, the first semiconductor layers 51A, 51B, 51C (and the resulting first nanostructures 52A, 52B, 52C) and the second semiconductor layers 53A, 53B, 53C (and the resulting second nanostructures 54A, 54B, 54C) shown and discussed herein include the same material in the p-type region 50P and the n-type region 50N for illustrative purposes only. Thus, in some embodiments, the first semiconductor layers 51A, 51B, 51C and / or the second semiconductor layers 53A, 53B, 53C in the p-type region 50P and the n-type region 50N may be different materials or formed in a different order.

[0047] Furthermore, in Figure 4In the embodiment with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed above the fin 66 and the shallow trench isolation region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned by using a suitable photolithography technique. After the photoresist is patterned, n-type impurities are implanted into the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, or the like in the implanted region to a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist may be removed, for example, by a suitable ashing process.

[0048] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using a suitable photolithography technique. After the photoresist is patterned, a p-type impurity is implanted into the n-type region 50N, and the photoresist may serve as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, or the like in the implanted region to a concentration of about 10 13 cm -3 to about 10 14 cm -3 After implantation, the photoresist may be removed, for example, by a suitable ashing process.

[0049] After the implantation of the n-type region 50N and the p-type region 50P, an anneal may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fin may be doped in situ during growth, which may eliminate the need for implantation, but both in situ doping and implantation doping may be used together. In other embodiments, some or all of the implantation of the n-type region 50N and / or the p-type region 50P may be performed prior to forming the multilayer stack 64.

[0050] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to a suitable technique. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and planarized by, for example, chemical mechanical polishing. The mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polycrystalline-silicon, polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials that have high etch selectivity from the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that for illustration purposes, the dummy dielectric layer 70 is shown covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the shallow trench isolation region 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the shallow trench isolation region 68.

[0051] Fig. 6A Various additional steps in making an example device are shown through Figure 24C. Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig.13A , Fig. 13C , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig. 22C , Fig.23C , Fig.24C Components in the n-type region 50N or the p-type region 50P are shown. In FIGS. 6A and 6B, a mask layer 74 (see FIG. 5A ) may be formed by using suitable photolithography and etching techniques. Figure 5) is patterned to form a mask 78. Then, the patterning of the mask 78 can be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the channel region of the corresponding fin 66. The pattern of the mask 78 can be used to physically separate the dummy gate 76 and each of the adjacent dummy gates 76. The dummy gate 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0052] exist Fig. 7A and Figure 7B In the embodiment, the first spacer layer 80 and the second spacer layer 82 are respectively formed on Fig. 6A and Figure 6B Subsequently, the first spacer layer 80 and the second spacer layer 82 are patterned to serve as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7B In the embodiment of the present invention, a first spacer layer 80 is formed on the top surface of the shallow trench isolation region 68, on the top surface and sidewalls of the fin 66, the nanostructure 55 and the mask 78, and on the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon oxynitride and carbon nitride, a combination of the foregoing, or the like. In some embodiments, the first spacer layer 80 may include other suitable materials, such as a low-k material having a dielectric constant value of less than about 3.5. The first spacer layer 80 may be formed by using a technique such as thermal oxidation or by chemical vapor deposition, physical vapor deposition, or the like, or may be formed by using other suitable techniques. The second spacer layer 82 may be formed of a material having an etch rate different from that of the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by chemical vapor deposition, atomic layer deposition, or the like.

[0053] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above reference Figure 4As discussed above, a mask (e.g., photoresist) may be formed over the n-type region 50N, exposing the p-type region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Thereafter, a mask (e.g., photoresist) may be formed over the p-type region 50P, exposing the n-type region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the aforementioned n-type impurities, and the p-type impurity may be any of the aforementioned p-type impurities. The lightly doped source / drain regions may have an impurity concentration between 10 15 cm -3 Up to 10 19 cm -3 Annealing can be used to repair implant damage and activate implanted impurities.

[0054] exist Fig. 8A and Figure 8B , the first spacer 80 and the second spacer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are self-aligned to subsequently formed source / drain regions and also serve to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer 80 and the second spacer 82 can be etched by using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer 82 has a different etching rate than the material of the first spacer 80, such that the first spacer 80 can be used as an etch stop layer when the second spacer 82 is patterned, and such that the second spacer 82 can be used as a mask when the first spacer 80 is patterned. For example, the second spacer 82 can be etched using an anisotropic etching process, wherein the first spacer 80 is used as an etch stop layer, and wherein the remaining portion of the second spacer 82 forms the second spacer 83, such as Fig. 8A Thereafter, when etching the exposed portion of the first spacer layer 80, the second spacer 83 is used as a mask to form Fig. 8A A first spacer 81 is shown.

[0055] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8BAs shown, in some embodiments, the second spacer 82 may be removed from above the first spacer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, while the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer 82 may remain above the first spacer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0056] It should be noted that the above disclosure generally describes processes for forming spacers and lightly doped source / drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, air gaps may be formed, and / or the like. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0057] According to some embodiments, in Fig. 9A and Fig. 9B In the embodiment, a first recess 86 is formed in the fin 66, the nanostructure 55 and the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52A, 52B, 52C and the second nanostructure 54A, 54B, 54C and into the substrate 50. Fig. 9A As shown, the top surface of the shallow trench isolation region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the shallow trench isolation region 68; or similar methods. The first recess 86 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (e.g., reactive ion etching, neutron beam etching, or the like). The first spacer 81, the second spacer 83, and the mask 78 shield the fin 66, the nanostructure 55, and a portion of the substrate 50 during the etching process to form the first recess 86. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and / or the fin 66. After the first recess 86 reaches the desired depth, a timed etching process can be used to stop the etching of the first recess 86.

[0058] exist Fig. 10A and Fig. 10B In the embodiment, a portion of the sidewall of the layer of the multilayer stack 64 formed of the first semiconductor material (eg, the first nanostructures 52A, 52B, 52C) exposed by the first recess 86 is etched to form a sidewall recess 88 in the n-type region 50N and the p-type region 50P. Fig. 10BThe sidewalls of the first nanostructure 52A, 52B, 52C and the second nanostructure 54A, 54B, 54C in the sidewall recess 88 are shown to be straight, and these sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as a wet etch or the like. An etchant selective to the first semiconductor material may be used to etch the first nanostructure 52A, 52B, 52C, such that the second nanostructure 54A, 54B, 54C and the substrate 50 remain relatively unetched compared to the first nanostructure 52A, 52B, 52C. In one embodiment, where the first nanostructure 52A, 52B, 52C comprises, for example, silicon germanium, and the second nanostructure 54A, 54B, 54C comprises, for example, silicon or silicon carbide, a dry etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) may be used to etch the sidewalls of the first nanostructure 52A, 52B, 52C.

[0059] exist Figure 11A-11C In the embodiment of the present invention, a first internal spacer 90 is formed in the sidewall recess 88. The first internal spacer 90 can be formed by depositing an internal spacer layer (not shown separately) on the sidewall recess 88. Fig. 10A and Fig. 10B The first inner spacer 90 serves as an isolation member between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the gate structure will replace the first nanostructures 52A, 52B, 52C.

[0060] The inner spacer layer may be deposited by a conformal deposition process, such as chemical vapor deposition, atomic layer deposition, or the like. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low-k material having a dielectric constant value of less than about 3.5. Next, the inner spacer layer may be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructures 54A, 54B, 54C in the n-type region 50N and flush with the sidewalls of the first nanostructures 52A, 52B, 52C in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructures 54A, 54B, 54C and / or the first nanostructures 52A, 52B, 52C, respectively.

[0061] Furthermore, although Fig. 11B The outer sidewall of the first inner partition 90 is shown to be straight, but the outer sidewall of the first inner partition 90 can be concave or convex. For example, Fig. 11CAn embodiment is shown in which the sidewalls of the first nanostructures 52A, 52B, 52C are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed in the sidewalls of the second nanostructures 54A, 54B, 54C in the n-type region 50N. Furthermore, an embodiment is also shown in which the sidewalls of the second nanostructures 54A, 54B, 54C are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed in the sidewalls of the first nanostructures 52A, 52B, 52C in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process, such as reactive ion etching, neutron beam etching, or the like. The first inner spacer 90 can be used to prevent a subsequent etching process (such as an etching process for forming a gate structure) from affecting a subsequently formed source / drain region (such as a source / drain region formed by a subsequent etching process) Figure 12A-12C Damage to the epitaxial source / drain regions 92) discussed.

[0062] exist Figure 12A-12C In the embodiment, the epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructures 54A, 54B, 54C in the n-type region 50N and the first nanostructures 52A, 52B, 52C in the p-type region 50P, thereby improving performance. Fig. 12B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 so that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by a suitable lateral distance so that epitaxial source / drain regions 92 do not short circuit with a subsequently formed gate of a resulting nanostructure field effect transistor. In some embodiments, epitaxial source / drain regions 92 have a height in the range of about 30 nm to about 80 nm, but other heights are possible.

[0063] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an n-type metal oxide semiconductor region) can be formed by shielding the p-type region 50P (e.g., a p-type metal oxide semiconductor region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any suitable material suitable for an n-type nanostructure field effect transistor. For example, if the second nanostructure 54A, 54B, 54C is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54A, 54B, 54C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, arsenic-doped silicon, or the like. There may be other materials. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55, and may have a facet.

[0064] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a p-type metal oxide semiconductor region) can be formed by masking the n-type region 50N (e.g., an n-type metal oxide semiconductor region). Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any suitable material suitable for a p-type nanostructure field effect transistor. For example, if the first nanostructure 52A, 52B, 52C is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive strain to the first nanostructure 52A, 52B, 52C, such as silicon germanium, boron-doped silicon germanium, germanium, boron-doped silicon germanium carbide, germanium tin, boron-doped silicon, or the like. Other materials are possible. The epitaxial source / drain region 92 may have a surface that protrudes from the corresponding upper surface of the multilayer stack 56 and may have facets.

[0065] The epitaxial source / drain region 92, the first nanostructures 52A, 52B, 52C, the second nanostructures 54A, 54B, 54C and / or the substrate 50 may be implanted with dopants to form source / drain regions, in a process similar to the process described above for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have an impurity concentration of about 10 19 cm -3 With about 10 21 cm -3 The n-type impurities and / or p-type impurities used in the source / drain regions may be any of the impurities described above or other impurities. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0066] Due to the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of nanostructure 55. In some embodiments, these facets result in the merging of adjacent epitaxial source / drain regions 92 of the same nanostructure field effect transistor, such as Fig. 12A In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, such as Fig. 12C As shown. Fig. 12A and Fig. 12C In the illustrated embodiment, the first spacer 81 may be formed to the top surface of the shallow trench isolation region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 may be adjusted to remove the spacer material to allow the epitaxial growth region to extend to the surface of the shallow trench isolation region 68.

[0067] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped with different impurity concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0068] Fig.12D An embodiment is shown, wherein the sidewalls of the first nanostructures 52A, 52B, 52C in the n-type region 50N and the sidewalls of the second nanostructures 54A, 54B, 54C in the p-type region 50P are concave, the outer sidewall of the first inner spacer 90 is concave, and the first inner spacer 90 is respectively recessed in the sidewalls of the second nanostructures 54A, 54B, 54C and the first nanostructures 52A, 52B, 52C. Fig.12DAs shown, epitaxial source / drain regions 92 may be formed contacting first inner spacers 90 and may extend through sidewalls of second nanostructures 54A, 54B, 54C in n-type region 50N and through sidewalls of first nanostructures 52A, 52B, 52C in p-type region 50P.

[0069] exist Figure 13A-13C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 12A , Fig. 12B Above the displayed structure ( FIG. 7A to FIG. 12D The process does not change Fig. 6A ). The first interlayer dielectric 96 may be formed of a dielectric material and may be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced CVD (PECVD), or flowable chemical vapor deposition. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any suitable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The contact etch stop layer 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material of the overlying first interlayer dielectric 96 .

[0070] exist Figure 14A-14B In the process, a planarization process (e.g., chemical mechanical polishing) may be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, or the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first interlayer dielectric 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0071] According to some embodiments, in Figure 15A-15B and Fig.16A and Fig. 16B In the process, an isolation structure 99 is formed (see Fig.16A and Fig. 16B ). One or more isolation structures 99 may be formed to electrically isolate adjacent nanostructure field effect transistors or adjacent devices including nanostructure field effect transistors. In some embodiments, isolation structure 99 may also "cut" a single fin or a single fin structure into individual fins 66 of individual nanostructure field effect transistors. In some cases, fin 66 is formed by patterning a continuous fin structure and fin 66 is cut into individual fins 66 to allow for improved patterning of fin 66, such as individual fins 66 having different widths. In some embodiments, isolation structure 99 may be considered a "dielectric dummy gate," "dummy gate structure," or "gate isolation structure."

[0072] According to some embodiments, in Figure 15A-15B In the embodiment of the present invention, a recess 97 is formed in the dummy gate 76, the dummy gate dielectric 71, the fin 66, the nanostructure 55, and the substrate 50. An isolation structure 99 will be subsequently formed in the recess 97. The recess 97 may extend through the first nanostructure 52A, 52B, 52C, the second nanostructure 54A, 54B, 54C, and may extend into the substrate 50. The recess 97 may be formed by forming a photoresist 95 or other mask structure and patterning the photoresist 95 using a suitable photolithography technique. Then, the recess 97 may be formed by etching the dummy gate 76, the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (e.g., reactive ion etching, neutron beam etching, or the like) using the patterned photoresist 95 as an etching mask. A single etching process or multiple etching processes may be used to etch various materials or layers when forming the recess 97. After the recess 97 reaches the desired depth, a timed etching process may be used to stop etching of the recess 97. In some embodiments, the recess 97 may extend to a depth D0 below the epitaxial source / drain region 92, with the depth D0 being in the range of about 5 nm to about 150 nm, but other depths are possible. In some embodiments, etching of the recess 97 may remove some or all of the second nanostructures 54A, 54B, 54C, the first inner spacer 90, and / or the first spacer 81. In some embodiments, after forming the recess 97, a portion of the second nanostructure 54A, 54B, 54C, the first inner spacer 90, and / or the first spacer 81 may remain, such as Fig. 15BAs shown. The recess 97 may extend between the corresponding pair of first spacers 81 and may have a length L0 that is substantially the same as the length of the replacement gate (see FIGS. 19A-19B ). After forming the recess 97, the photoresist may be removed using a suitable technique. This is an example process for forming the recess 97, but other processes are possible. For example, in other embodiments, some or all of the recess 97 and other components, such as the second recess 98 (see FIG. 19A-19B ), may be etched simultaneously. Figures 17A-18B ) or notch 104 (see Figure 20A-20B ).

[0073] According to some embodiments, in Fig.16A and Fig. 16B In the embodiment of the present invention, a dielectric material is deposited in the recess 97 to form an isolation structure 99. In some cases, the dielectric material may include one or more layers of one or more different materials. In some embodiments, the dielectric material includes one or more materials, such as silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbon nitride, metal oxides (such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, yttrium oxide or the like), combinations of the foregoing, or the like. There may be other materials or combinations of materials. The dielectric material may be deposited using one or more suitable techniques, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. In some embodiments, the dielectric material may be different from the material of the first interlayer dielectric 96. After filling the recess 97 with the dielectric material, excess dielectric material may be removed using, for example, a chemical mechanical polishing process or the like, which may leave a substantially flush isolation structure 99 and the top surface of the first interlayer dielectric 96.

[0074] In other embodiments, isolation structure 99 may be formed by depositing a conductive material in recess 97. The conductive material may then be electrically connected to a suitable voltage to provide electrical isolation for the nanostructured field effect transistor or device. The conductive material may include, for example, polysilicon, metal, or the like. In some embodiments, the conductive material may be the same as the gate electrode that is subsequently formed (see Figure 19A-19B ) and can be deposited using the same deposition steps as the gate electrode.

[0075] exist Fig.17A and Fig. 17BIn the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form the second recess 98. The portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a rate greater than that of etching the first interlayer dielectric 96 or the first spacer 81. Each second recess 98 exposes the nanostructure 55 and / or is above a portion of the nanostructure 55. The nanostructure 55 is disposed between adjacent pairs of epitaxial source / drain regions 92 as part of the channel region. During the removal, the dummy gate dielectric 71 may be used as an etch stop layer when etching the dummy gate 76. After removing the dummy gate 76, the dummy gate dielectric 71 may then be removed. In other embodiments, the second recess 98 is formed as part of forming the recess 97, or vice versa.

[0076] exist Fig.18A and Fig.18B , the first nanostructures 52A, 52B, 52C in the n-type region 50N and the p-type region 50P are removed, and the second recess 98 is extended. The first nanostructures 52A, 52B, 52C can be removed by performing an isotropic etching process, such as wet etching or a similar method using an etchant that is selective to the material of the first nanostructures 52A, 52B, 52C, while the second nanostructures 54A, 54B, 54C, the substrate 50, and the shallow trench isolation regions 68 remain relatively unetched relative to the first nanostructures 52A, 52B, 52C. In an embodiment where the first nanostructures 52A, 52B, 52C include, for example, silicon germanium and the second nanostructures 54A, 54B, 54C include, for example, silicon or silicon carbide, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructures 52A, 52B, 52C in the n-type region 50N. Other materials or etchants are possible.

[0077] The remaining second nanostructures 54A, 54B, 54C are used to provide channel regions for the n-type region 50N and the p-type region 50P, so the second nanostructures 54A, 54B, 54C may also be referred to herein as channel regions or channels. In some embodiments, the channel region may have a width W0 (e.g., "channel width") in the range of about 5 nm to about 100 nm, but other widths are possible. The channel region may have a thickness in the range of about 4 nm to about 10 nm, but other thicknesses are possible. Adjacent channel regions may have a vertical separation distance in the range of about 6 nm to about 20 nm, and may have a vertical spacing in the range of about 10 nm to about 30 nm, but other distances are possible.

[0078] exist Fig.19Aand Fig.19B In the embodiment of the present invention, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate electrode 102 includes a gate electrode 102N formed in the n-type region 50N and a gate electrode 102P formed in the p-type region 50P. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N and the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls and bottom surface of the second nanostructures 54A, 54B, 54C. The gate dielectric layer 100 may also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the first spacer 81 and the shallow trench isolation region 68.

[0079] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant value greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or the like.

[0080] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.19A and Fig.19B A single layer of gate electrode 102 is shown, but gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting gate electrode 102 may be deposited between adjacent second nanostructures 54A, 54B, 54C in n-type region 50N and p-type region 50P, and between second nanostructure 54A and substrate 50.

[0081] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, so that the gate dielectric layer 100 in each region is formed of the same material. The formation of the gate electrode 102N and the gate electrode 102P may occur simultaneously, so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, so that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by different processes, so that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0082] After filling the second recess 98, a planarization process (e.g., chemical mechanical polishing) may be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are above the top surface of the first interlayer dielectric 96. The remaining portions of the gate electrode 102 and the gate dielectric layer 100 material then form a replacement gate structure of the final nanostructure field effect transistor. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate stack" or "gate structure."

[0083] According to some embodiments, in Figure 20A-20B and Figure 21A-21B In the process, a gate cutting region 107 is formed (see Figure 21A-21B ). One or more gate cut regions 107 may be formed to electrically isolate adjacent nanostructure field effect transistors or adjacent devices including nanostructure field effect transistors. In some embodiments, the gate cut region 107 may also "cut" a single gate structure into separate gate structures of the corresponding nanostructure field effect transistor. The gate cut region 107 may also be referred to as a "gate end dielectric", "gate end isolation structure" or "gate end structure". The area of ​​the gate structure between the channel region and the gate cut region 107 may be referred to as a "gate end" or "gate cap".

[0084] According to some embodiments, in Figure 20A-20BIn the embodiment of the present invention, a recess 104 is formed in a gate structure (e.g., in a gate electrode 102 and a gate dielectric layer 100) and a shallow trench isolation region 68. A gate cut region 107 will be subsequently formed in the recess 104. The recess 104 may extend through the gate electrode 102 and the gate dielectric layer 100 and extend into the shallow trench isolation region 68. The recess 104 may be formed by forming a photoresist 103 or other mask structure and then patterning using a suitable photolithography technique. The recess 104 may then be formed by etching the gate structure and the shallow trench isolation region 68 using an anisotropic etching process (e.g., reactive ion etching, neutron beam etching, or the like) using the patterned photoresist 103 as an etching mask. A single etching process or multiple etching processes may be used to etch various materials or layers when forming the recess 104. After the recess 104 reaches a desired depth, a timed etching process may be used to stop etching of the recess 104. In some embodiments, the recess 104 may extend below the gate structure and into the shallow trench isolation region 68 to a depth D1 in the range of about 10 nm to about 150 nm, although other depths are possible. In some embodiments, the recess 104 may be separated from the adjacent channel region by a separation distance G0 (e.g., a "gate end distance") in the range of about 3 nm to about 60 nm, although other separation distances are possible. After forming the recess 104, the photoresist 103 may be removed using a suitable technique. This is an example process for forming the recess 104, and other processes are possible.

[0085] According to some embodiments, in Figure 21A-21BIn the embodiment of the present invention, a dielectric material is deposited in the recess 104 to form a gate cut region 107. In some cases, the dielectric material may include one or more layers of one or more different materials. In some embodiments, the dielectric material includes one or more materials, such as silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride and carbon nitride, metal oxides (such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, yttrium oxide or the like), a combination of the foregoing or the like. There may be other materials or combinations of materials. The dielectric material may be deposited using one or more suitable techniques, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition or the like. In some embodiments, the dielectric material may be different from the material of the first interlayer dielectric 96 and / or the material of the isolation structure 99. After filling the recess 104 with the dielectric material, the excess dielectric material may be removed using, for example, a chemical mechanical polishing process or the like, which may leave a substantially flush gate cut region 107 and the top surface of the gate structure. In some embodiments, the gate cut region 107 may have a width W1 in the range of about 5nm to about 60nm, but may have other widths. The gate cut region 107 may be separated from the channel region by a gate end distance (separation distance G0). In some embodiments, the gate end distance (separation distance G0) may be controlled by controlling the width W1 and / or the position of the corresponding gate cut region 107. In some cases, the gate end distance (separation distance G0) may affect the characteristics of the gate structure, such as the capacitance and resistance of the gate structure. Figure 25 to Figure 35 Embodiments are described for controlling gate tip distances of different nanostructure field effect transistors to control specific characteristics of the nanostructure field effect transistors.

[0086] exist Figure 22A-22C In the embodiment, the gate structure (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed so that a notch is formed directly above each gate structure and between the two side portions of the first spacer 81. A gate mask 105 including one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled in the notch, and then a planarization process is performed to remove the excess portion of the dielectric material extending above the first interlayer dielectric 96. The gate contacts (such as the gate contacts 114, hereinafter referred to as gate contacts) formed subsequently are Figure 24A-24C Discussion) penetrates the gate mask 105 to contact the top surface of the recessed gate electrode 102.

[0087] pass Figure 22A-22CFurther shown, the second interlayer dielectric 106 is deposited over the first interlayer dielectric 96 and over the gate mask 105. In some embodiments, the second interlayer dielectric 106 is a flowable film formed by flowable chemical vapor deposition. In some embodiments, the second interlayer dielectric 106 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or the like.

[0088] exist Figure 23A-23C In the embodiment of the present invention, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94 and the gate mask 105 are etched to form a third recess 108 exposing the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., reactive ion etching, neutron beam etching, or the like). In some embodiments, the third recess 108 can be etched through the second interlayer dielectric 106 and the first interlayer dielectric 96 using a first etching process; the gate mask 105 can be etched using a second etching process; and the contact etch stop layer 94 can be etched using a third etching process. A mask (e.g., a photoresist) can be formed and patterned over the second interlayer dielectric 106 to shield a portion of the second interlayer dielectric 106 from the first and second etching processes. In some embodiments, the etching process may over-etch, so that the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom surface of the third recess 108 may be flush (e.g., at the same level or having the same distance to the substrate) or lower (e.g., closer to the substrate) than the epitaxial source / drain region 92 and / or the gate structure. Fig. 23B The third recess 108 is shown to expose the epitaxial source / drain region 92 and the gate structure at the same cross-section. In various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed at different cross-sections to reduce the risk of shorting of subsequently formed contacts. After the third recess 108 is formed, a silicide region 110 is formed above the epitaxial source / drain region 92. In some embodiments, a silicide or germanide region is formed above the exposed portion of the epitaxial source / drain region 92 by first depositing a metal (not shown) that is reactive with the semiconductor material of the underlying epitaxial source / drain region 92 (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys of the foregoing), followed by a thermal annealing process to form the silicide region 110. Next, the unreacted portion of the deposited metal is removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region or a silicon-germanide region (a region including silicide and germanide). In one embodiment, the silicide region 110 includes TiSi and has a thickness in a range of about 2 nm to about 10 nm.

[0089] Then, in Figure 24A-24C , contacts 112 and 114 (which may be referred to as contact plugs) are formed in the third recess 108. The contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive component (such as the gate structure and / or the silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the gate structure and may be referred to as a gate contact, while the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, or the like. A planarization process (such as chemical mechanical polishing) may be performed to remove excess material from the surface of the second interlayer dielectric 106. Further processing may be performed, such as forming an inter-metal dielectric (IMD) over the contacts 112 / 114 , and vias or other conductive features may be formed through the IMD to electrically connect the contacts 112 / 114 .

[0090] Figures 25 to 34B Schematic diagrams of plan view and cross-section of devices 200, 300, and 400 are shown according to some embodiments, each of which includes a plurality of nanostructure field effect transistors having different gate end distances. Devices 200 / 300 / 400 include devices that may be similar to Fig. 24B The n-type nanostructure field effect transistor of the n-type region 50N and the p-type nanostructure field effect transistor of the p-type region 50P are shown as n-type nanostructure field effect transistors and p-type nanostructure field effect transistors. Device 200 / 300 / 400 includes a nanostructure field effect transistor formed in a "complementary metal oxide semiconductor" configuration, wherein the gate structure of the n-type nanostructure field effect transistor physically and electrically contacts the gate structure of the p-type nanostructure field effect transistor. In this way, device 200 / 300 / 400 includes a "complementary metal oxide semiconductor device", which includes one or more groups of nanostructure field effect transistors in a complementary metal oxide semiconductor configuration. In some cases, one complementary metal oxide semiconductor device may be formed by a nanostructure field effect transistor having a different channel width from another complementary metal oxide semiconductor device. For example, a first complementary metal oxide semiconductor device may have a relatively large channel width, while a second complementary metal oxide semiconductor device may have a relatively small channel width. In some embodiments, the first complementary metal oxide semiconductor device may have a channel width in the range of about 1.1 to about 5 times the channel width of the second complementary metal oxide semiconductor device.

[0091] The CMOS devices of the device 200 / 300 / 400 may be separated and isolated by one or more isolation structures 99 and / or one or more gate cut regions 107. In some embodiments, the gate cut regions 107 may have sidewall offsets (e.g., jogs) and / or width variations to allow the nanostructure field effect transistor of one CMOS device to have a different gate end width than the nanostructure field effect transistor of another CMOS device. The gate cut regions 107 may be as described above with reference to FIG. 20A to FIG. 21B The formation has an offset or width variation determined by the pattern of the notches 104. In some embodiments, the first CMOS device can have a gate end distance greater than the channel width of the second CMOS device in the range of about 2 nm to about 20 nm. In some cases, the gate end distance can also be controlled by controlling the position of the channel region relative to the gate cut region 107.

[0092] As mentioned previously, in some cases, some nanostructure field effect transistor characteristics can be controlled by controlling the gate end distance (e.g. Fig.24A For example, reducing the gate end distance of the gate structure also reduces the size of the gate structure, which can reduce the capacitance of the gate structure. In some cases, having a smaller channel width (e.g. Fig.24A Nanostructure field effect transistors with a separation distance G0 (shown in FIG. 1 ) are more sensitive to gate structure capacitance, so reducing the gate end distance can reduce gate structure capacitance and improve performance. In addition, increasing the gate end distance of the gate structure can reduce current crowding in the gate end region of the gate structure, which can reduce the resistance of the gate structure. In some cases, nanostructure field effect transistors with larger channel widths (e.g., high current nanostructure field effect transistors) are more sensitive to gate structure resistance, so increasing the gate end distance can reduce gate structure resistance and improve performance. The embodiments described herein (e.g., with reference to Figures 25 to 34B The embodiments described herein allow the formation of devices including nanostructured field effect transistors with smaller channel widths and smaller gate end distances and nanostructured field effect transistors with larger channel widths and larger gate end distances. In this way, the overall performance of these devices can be improved by forming nanostructured field effect transistors with different gate end distances. These embodiments are for illustrative purposes, and other numbers, appearances, or arrangements of nanostructured field effect transistors or complementary metal oxide semiconductor devices are possible and are also within the scope of the embodiments of the present invention.

[0093] Fig.25 , Fig.26A and Fig.26BSchematic diagrams of a plan view and a cross-section of a device 200 are shown according to some embodiments. The device 200 includes a first complementary metal oxide semiconductor device 202A and an adjacent second complementary metal oxide semiconductor device 202B. In some cases, the first complementary metal oxide semiconductor device 202A can be considered as a "first unit" of the device 200, and the second complementary metal oxide semiconductor device 202B can be considered as a "second unit" of the device 200. Fig.25 A plan view (e.g., a “top view”) of the display device 200 is shown for clarity. Fig.25 Omit some parts. Fig.26A The cross-sectional view of the first complementary metal oxide semiconductor device 202A along the cross-sectional view AA-AA′ and the cross-sectional view of the second complementary metal oxide semiconductor device 202B along the cross-sectional view AB-AB′ are shown. The cross-sectional view AA-AA′ and the cross-sectional view AB-AB′ are similar to Figure 1 Section A-A'. Fig.26B A schematic cross-sectional view of the first complementary metal oxide semiconductor device 202A and the second complementary metal oxide semiconductor device 202B along the cross-sectional line BB′ is shown. The cross-sectional line BB′ is similar to Figure 1 Section B-B'.

[0094] According to some embodiments, the first complementary metal oxide semiconductor device 202A includes an n-type nanostructure field effect transistor 250NA and a p-type nanostructure field effect transistor 250PA, and the second complementary metal oxide semiconductor device 202B includes an n-type nanostructure field effect transistor 250NB and a p-type nanostructure field effect transistor 250PB. The n-type nanostructure field effect transistor 250NA is formed on the fin 266NA and has a channel width WNA, while the p-type nanostructure field effect transistor 250PA is formed on the fin 266PA and has a channel width WPA. The n-type nanostructure field effect transistor 250NB is formed on the fin 266NB and has a channel width WNB, while the p-type nanostructure field effect transistor 250PB is formed on the fin 266PB and has a channel width WPB. In this way, the channel widths WNA and WPA of the first complementary metal oxide semiconductor device 202A are smaller than the channel widths WNB and WPB of the second complementary metal oxide semiconductor device 202B. Channel widths WNA and WPA may be the same width or different widths, and channel widths WNB and WPB may be the same width or different widths. In some embodiments, fins 266NA and 266NB may be formed as a single fin structure that is cut by isolation structures 99 that separate first CMOS device 202A from second CMOS device 202B. Fins 266PA and 266PB may be similarly formed as a single fin structure that is subsequently cut by isolation structures 99 into separate fins 66. In other embodiments, first CMOS device 202A is isolated from second CMOS device 202B by more than one isolation structure 99.

[0095] In the first complementary metal oxide semiconductor device 202A, the n-type nanostructure field effect transistor 250NA has a gate end distance GNA, and the p-type nanostructure field effect transistor 250PA has a gate end distance GPA. In the second complementary metal oxide semiconductor device 202B, the n-type nanostructure field effect transistor 250NB has a gate end distance GNB, and the p-type nanostructure field effect transistor 250PB has a gate end distance GPB. In other words, in some embodiments, the gate end distances GNA and GPA of the first complementary metal oxide semiconductor device 202A are smaller than the gate end distances GNB and GPB of the second complementary metal oxide semiconductor device 202B. In some embodiments, the gate end distances GNB and / or GPB may be greater than the gate end distances GNA and / or GPA by between about 2 nm and about 20 nm. In this way, because the channel width of the first complementary metal oxide semiconductor device 202A is smaller than the channel width of the second complementary metal oxide semiconductor device 202B, the performance of the device 200 can be improved by using the above-mentioned different gate end distances. The gate end distances GNA and GPA may be approximately the same distance or different distances, and the gate end distances GNB and GPB may be approximately the same distance or different distances.

[0096] Different gate end distances in the device 200 can be achieved by forming the gate cut region 107 with an offset region. A larger offset region of the gate cut region 107 corresponds to a smaller gate end distance. For example, the gate cut region 107 of the first complementary metal oxide semiconductor device 202A includes offset regions 207N and 207P protruding from the gate cut region 107 of the second complementary metal oxide semiconductor device 202B. The offset region 207N of the n-type nanostructure field effect transistor 250NA has an offset distance DGN (relative to the gate cut region 107 of the n-type nanostructure field effect transistor 250NB), and the offset region 207P of the p-type nanostructure field effect transistor 250PA has an offset distance DGP (relative to the gate cut region 107 of the p-type nanostructure field effect transistor 250PB). The offset distances DGN and DGP may be in the range of about 2 nm to about 20 nm, but other distances are possible. The offset distances DGN and DGP may be similar or different. The offset region may have a width WG in the range of about 15 nm to about 900 nm, and other widths are possible. In some embodiments, the width WG may be similar to the width of the adjacent gate structure, or may be greater than the width of the adjacent gate structure, such as Fig.25In some cases, the offset region can be formed by forming the gate cut region 107 with a varying width, so that the offset region 207 corresponds to a portion of the gate cut region 107 with a relatively large width. In other embodiments, the gate cut region 107 of the second CMOS device 202B also has an offset region, but has a smaller offset distance than the offset region of the first CMOS device 202A.

[0097] Fig. 27 A plan view of the display device 200, Fig. 27 The device 200 is similar to Fig.25 The device 200, except in Fig. 27 In the embodiment, the offset regions of the gate cutting region 107 have different positions, widths and offset distances. Fig. 27 The offset regions shown are provided as examples and other appearances, arrangements or sizes of offset regions are possible. Fig. 27 , one side of the offset region 207N is aligned with the sidewall of the first spacer 81 adjacent to the gate structure, and the opposite side of the offset region 207N is aligned with the sidewall of the first spacer 81 adjacent to the isolation structure 99. As another example, the offset region 207P is wide enough to partially extend into the adjacent isolation structure 99.

[0098] Fig.28 A plan view of the display device 200, Fig. 27 The device 200 is similar to Fig.25 The device 200, except in Fig.28 In the embodiment, the gate cut region 107 is formed as a plurality of segments rather than a continuous structure. Individual gate cut regions 107 may have different widths than those in the drawings. For example, in other embodiments, the sidewalls of individual gate cut regions 107 may be covered by the first spacer 81 or may protrude beyond the first spacer 81. The gate end distance may be controlled by controlling the size of the individual gate cut regions 107. For example, if Fig.28 As shown, the gate cut region 107 at the nanostructure field effect transistor of the first complementary metal oxide semiconductor device 202A is larger than the gate cut region 107 at the nanostructure field effect transistor of the second complementary metal oxide semiconductor device 202B.

[0099] Fig.29 , Figure 30A-Figure 30B and Figure 31A-Figure 31BA schematic plan view and cross-sectional view of a device 300 are shown according to some embodiments. The device 300 includes two first CMOS devices 302A and an adjacent second CMOS device 302B. The first CMOS device 302A is separated from the second CMOS device 302B by two isolation structures 99, but in other embodiments, more than two isolation structures 99 may be used. The first CMOS devices 302A are separated from each other by a gate cut region 107. In some cases, the first CMOS device 302A and the second CMOS device 302B may be considered a "unit" of the device 300. In some embodiments, the length of the second CMOS device 302B along a direction parallel to the gate structure may be about twice the length of the first CMOS device 302A along the same direction, but other lengths are possible. In some embodiments, the nanostructure field effect transistor of the first CMOS device 302A has a smaller channel width and a smaller gate end distance than the nanostructure field effect transistor of the second CMOS device 302B.

[0100] Fig.29 The plan view (eg, top view) of the display device 300 omits some components for clarity. Fig. 30A A schematic cross-sectional view of the first complementary metal oxide semiconductor device 302A along the cross section AA-AA′ is shown. Fig. 30B The cross-sectional view of the second CMOS device 302B along the cross-sectional view AB-AB′ is shown. The cross-sectional view AA-AA′ and the cross-sectional view AB-AB′ are similar to Figure 1 Section A-A'. Fig.31A A schematic cross-sectional view of the first complementary metal oxide semiconductor device 302A and the second complementary metal oxide semiconductor device 302B along the cross section BA-BA′ is shown. Fig.31B A schematic cross-sectional view of the second CMOS device 302B along the cross-sectional line BB-BB′ is shown. The cross-sectional lines BA-BA′ and BB-BB′ are similar to Figure 1 Section B-B'.

[0101] According to some embodiments, the first complementary metal oxide semiconductor device 302A each includes an n-type nanostructure field effect transistor 350NA and a p-type nanostructure field effect transistor 350PA. The nanostructure field effect transistor 350NA has a channel width WNA, and the p-type nanostructure field effect transistor 350PA has a channel width PNA. The channel widths WNA and WPA may be approximately the same width or different widths. The n-type nanostructure field effect transistor 350NA has a gate end distance GNA, and the p-type nanostructure field effect transistor 350PA has a gate end distance GPA. According to some embodiments, the gate end distances GNA and GPA may be controlled by controlling the size and / or offset of the various gate cut regions 107.

[0102] The second complementary metal oxide semiconductor device 302B includes an n-type nanostructure field effect transistor 350NB and a p-type nanostructure field effect transistor 350PB. Each n-type nanostructure field effect transistor 350NB is located between two p-type nanostructure field effect transistors 350PB, such that the gate structure of the n-type nanostructure field effect transistor 350NB is located between the gate structures of the p-type nanostructure field effect transistors 350PB. In some cases, each n-type nanostructure field effect transistor 350NB can be considered as a single n-type nanostructure field effect transistor formed by two "merged" n-type nanostructure field effect transistors. In this way, in some cases, the second complementary metal oxide semiconductor device 302B includes a configuration of two "merged" n-type nanostructure field effect transistors between two p-type nanostructure field effect transistors, with the gate structures of the two "merged" n-type nanostructure field effect transistors physically and electrically contacting the gate structures of the p-type nanostructure field effect transistors.

[0103] The n-type nanostructure field effect transistor 350NB has a channel width WNB, and the p-type nanostructure field effect transistor 350PB has a channel width WPB. The channel widths WNB and WPB may be approximately the same width or different widths. The channel widths WNA and WPA of the first complementary metal oxide semiconductor device 302A are smaller than the channel widths WNB and WPB of the second complementary metal oxide semiconductor device 302B. In some embodiments, the channel width WNB may be greater than twice the channel width WNA or WPA. For example, in some embodiments, the channel width WNB may be in the range of about 1.2 times to about 10 times the channel width WNA. In some embodiments, the channel width WNB may be about twice the channel width WPB. There may be other ratios of channel widths.

[0104] In the second CMOS device 302B, because the gate structure of each n-type nanostructure field effect transistor 350NB is located between the gate structures of two p-type nanostructure field effect transistors 350PB, only the p-type nanostructure field effect transistor 350PB has a gate end distance GPB. In some embodiments, the gate end distance GPB is greater than the gate end distance GNA and / or the gate end distance GPA. In some embodiments, the gate end distance GPB can be greater than the gate end distance GNA and / or GPA by between about 2 nm and about 20 nm. In this way, because the channel width of the first CMOS device 302A is smaller than the channel width of the second CMOS device 302B, the performance of the device 300 can be improved by forming a smaller gate end distance of the first CMOS device 302A than the second CMOS device 302B.

[0105] In some embodiments, the fin 66 of the device 300 may be formed as a single fin structure that is cut through by an isolation structure 99 that separates the first CMOS device 302A from the second CMOS device 302B. In some embodiments, a dummy fin 367 and / or a dummy epitaxial region 392 may be formed between the isolation structures 99. In other embodiments, the first CMOS device 302A is separated from the second CMOS device 302B by more than two isolation structures 99. In some cases, using two or more isolation structures 99 to separate adjacent CMOS devices may improve electrical isolation of the CMOS devices and reduce leakage or parasitic capacitance. Fig.31B As shown, in some cases, the contact 112 may be formed in the gate cut region 107. The contact 112 may also extend over one or more epitaxial source / drain regions 92 adjacent to the gate cut region 107 and be electrically connected to the epitaxial source / drain region 92.

[0106] Fig.32 A plan view of an apparatus 300 is shown in accordance with some embodiments. Fig.32 The device 300 is similar to Fig.29 The device 300, except in Fig.32 In the embodiment, the n-type nanostructure field effect transistor is changed into a p-type nanostructure field effect transistor, and the p-type nanostructure field effect transistor is changed into an n-type nanostructure field effect transistor. For example, Fig.32The second complementary metal oxide semiconductor device 302B includes a p-type nanostructure field effect transistor between two n-type nanostructure field effect transistors, such that the gate structure of each p-type nanostructure field effect transistor is located between the gate structures of the n-type nanostructure field effect transistors. In some cases, each p-type nanostructure field effect transistor of the second complementary metal oxide semiconductor device 302B can be regarded as a single p-type nanostructure field effect transistor formed by two "merged" p-type nanostructure field effect transistors. Other configurations are possible. In some embodiments, the nanostructure field effect transistor of the first complementary metal oxide semiconductor device 302A has a smaller channel width and a smaller gate end distance than the second complementary metal oxide semiconductor device 302B.

[0107] Fig.33 and Figure 34A-Figure 34B Schematic diagrams of a plan view and a cross-section of a device 400 are shown according to some embodiments. The device 400 includes three first complementary metal oxide semiconductor devices 402A and adjacent second complementary metal oxide semiconductor devices 402B. The device 400 also includes two separate nanostructure field effect transistors: an n-type nanostructure field effect transistor 450NC and a p-type nanostructure field effect transistor 450PC. The first complementary metal oxide semiconductor device 402A is separated from the second complementary metal oxide semiconductor device 402B and the n-type nanostructure field effect transistor 450NC and the p-type nanostructure field effect transistor 450PC by two isolation structures 99, but in other embodiments, more than two isolation structures 99 may be used. The first complementary metal oxide semiconductor devices 402A are separated from each other by a gate cut region 107, and the second complementary metal oxide semiconductor device 402B is separated from the n-type nanostructure field effect transistor 450NC and the p-type nanostructure field effect transistor 450PC by a gate cut region 107. In some embodiments, the nanostructure field effect transistor of the first CMOS device 402A has a smaller channel width and a smaller gate end distance than the nanostructure field effect transistor of the second CMOS device 402B.

[0108] Fig.33 The diagram is a plan view (eg, top view) of the display device 400 , with some components omitted for clarity. Fig.34A A schematic cross-sectional view of the first complementary metal oxide semiconductor device 402A along the cross section AA-AA′ is shown. Fig.34B The cross-sectional view of the second CMOS device 402B, the n-type nanostructure field effect transistor 450NC and the p-type nanostructure field effect transistor 450PC along the cross-sectional view AB-AB′ is shown. The cross-sectional view AA-AA′ and the cross-sectional view AB-AB′ are similar to Figure 1 Section A-A'.

[0109] According to some embodiments, the first complementary metal oxide semiconductor device 402A each includes an n-type nanostructure field effect transistor 450NA and a p-type nanostructure field effect transistor 450PA. The nanostructure field effect transistor 450NA has a channel width WNA, and the p-type nanostructure field effect transistor 450PA has a channel width PNA. The channel widths WNA and WPA may be approximately the same width or different widths. The n-type nanostructure field effect transistor 450NA has a gate end distance GNA, and the p-type nanostructure field effect transistor 450PA has a gate end distance GPA. According to some embodiments, the gate end distances GNA and GPA may be controlled by controlling the size and / or offset of the various gate cut regions 107.

[0110] The second CMOS device 402B includes an n-type nanostructure field effect transistor 450NB and a p-type nanostructure field effect transistor 450PB. In some cases, each n-type nanostructure field effect transistor 450NB can be considered as a single n-type nanostructure field effect transistor formed by two “merged” n-type nanostructure field effect transistors, and each p-type nanostructure field effect transistor 450PB can be considered as a single p-type nanostructure field effect transistor formed by two “merged” p-type nanostructure field effect transistors.

[0111] The n-type nanostructure field effect transistor 450NB has a channel width WNB, and the p-type nanostructure field effect transistor 450PB has a channel width WPB. The channel widths WNB and WPB may be approximately the same width or different widths. The channel widths WNA and WPA of the first complementary metal oxide semiconductor device 402A are smaller than the channel widths WNB and WPB of the second complementary metal oxide semiconductor device 402B. In some embodiments, the channel width WNB or the channel width WPB may be greater than three times the channel width WNA or WPA. For example, in some embodiments, the channel widths WNB and WPB may be in a range of about 3 times to about 10 times the channel widths WNA and WPA.

[0112] In the second CMOS device 402B, the n-type nanostructure FET 450NB has a gate end distance GNB, and the p-type nanostructure FET 450PB has a gate end distance GPB. In some embodiments, the gate end distances GNB and GPB are greater than the gate end distances GNA and GPA. In some embodiments, the gate end distances GNB and / or GPB may be between about 2 nm and about 20 nm greater than the gate end distances GNA and / or GPA. In this way, because the channel width of the first CMOS device 402A is smaller than the channel width of the second CMOS device 402B, the performance of the device 400 may be improved by forming a smaller gate end distance of the first CMOS device 402A than the second CMOS device 402B.

[0113] In some embodiments, the selective nanostructure field effect transistors (e.g., n-type nanostructure field effect transistor 450NC and p-type nanostructure field effect transistor 450PC) may be formed adjacent to the second CMOS device 402B. In other embodiments, the selective nanostructure field effect transistors may have a different appearance or size than shown in the figures, or the selective nanostructure field effect transistors may be part of other devices (e.g., other CMOS devices). In some embodiments, the selective nanostructure field effect transistors may have a channel width that is approximately the same as the nanostructure field effect transistors of the first CMOS device 402A, but may have other channel widths.

[0114] In some embodiments, the fin 66 of the device 400 may be formed as a single fin structure that is cut by an isolation structure 99 that separates the first CMOS device 402A, the second CMOS device 402B, and the optional nanostructure field effect transistors (e.g., the n-type nanostructure field effect transistor 450NC and the p-type nanostructure field effect transistor 450PC). In some embodiments, the dummy fin 467 and / or the dummy epitaxial region may be formed between the isolation structures 99. In other embodiments, the first CMOS device 402A is separated from the second CMOS device 402B by more than two isolation structures 99. In some cases, the use of two or more isolation structures 99 to separate adjacent CMOS devices may improve the electrical isolation of the CMOS devices and reduce leakage or parasitic capacitance.

[0115] Fig.35 A schematic cross-sectional view of a device 201 formed using a gate-last process according to some embodiments is shown. Fig.35 The device 201 is similar to Figure 25 to Figure 26BThe device 200 is formed by a gate-first process, except that the device 200 is formed by a gate-last process, and the device 201 is formed by a gate-last process. Fig.35 The cross-sectional diagram is similar to Fig.26A For example, in a gate last process, before forming a replacement gate structure, a gate cut region 107 of the device 201 may be formed. Because the gate cut region 107 is formed before the replacement gate structure, the gate dielectric layer 100 may be deposited on the sidewalls of the gate cut region 107, such as Fig.35 In some embodiments, a gate-last process may be used to form the devices, complementary metal oxide semiconductor devices, or nanostructure field effect transistors described herein.

[0116] Embodiments of the utility model can achieve many advantages. For example, the embodiments described herein allow the formation of nanostructure field effect transistors of narrower and wider widths in a device or circuit array, with improved performance, such as improved speed, improved current, reduced leakage, or reduced power consumption. The embodiments described herein include a variable gate end cutting scheme, which allows the gate structures of different nanostructure field effect transistors in the same device to have different gate end distances depending on the characteristics of the nanostructure field effect transistor. For example, a nanostructure field effect transistor with a narrower channel width may have a smaller gate end distance to reduce capacitance and improve speed, while a nanostructure field effect transistor with a wider channel width may have a larger gate end distance to reduce resistance and improve drive current. The embodiment technology described herein allows the formation of nanostructure field effect transistors used in complementary metal oxide semiconductor device configurations. In this way, the embodiments described herein allow the performance of nanostructure field effect transistors with a wide range of channel widths in the same device to be improved.

[0117] In some embodiments of the present invention, the device includes a stack of first nanostructures, located on a substrate, wherein each of the first nanostructures includes a channel region having a first width; a first gate structure, located on the stack of the first nanostructures, the first gate structure surrounds each of the first nanostructures, wherein the distance from the first end of the first gate structure to the adjacent first nanostructure is a first distance; a stack of second nanostructures, located on the substrate, wherein each of the second nanostructures includes a channel region having a second width greater than the first width; a second gate structure, located on the stack of the second nanostructures, wherein the second gate structure surrounds each of the second nanostructures, wherein the distance from the first end of the second gate structure to the adjacent second nanostructure is a second distance, and the second distance is greater than the first distance; and a first isolation structure, extending continuously from the first end of the first gate structure to the first end of the second gate structure. In one embodiment, the second distance is greater than the first distance by between 2nm and 20nm. In one embodiment, the first gate structure and the second gate structure are on the same side of the first isolation structure. In one embodiment, the device includes a second isolation structure, located between the first gate structure and the second gate structure, wherein the second isolation structure is a dummy gate structure. In one embodiment, the second width is between 1.1 times and 10 times the first width. In one embodiment, the device comprises a stack of third nanostructures, wherein the second gate structure surrounds each of the third nanostructures, wherein the distance from the second end of the second gate structure to the adjacent third nanostructure is a third distance, and the third distance is greater than the first distance. In one embodiment, the stack of second nanostructures is doped n-type, and the stack of third nanostructures is doped p-type. In one embodiment, the first gate structure extends along a first direction, and the first isolation structure extends along a second direction perpendicular to the first direction. In one embodiment, a first portion of the first isolation structure at the first end of the first gate structure protrudes from a second portion of the first isolation structure at the first end of the second gate structure.

[0118] In some embodiments of the present invention, a semiconductor device includes a first complementary metal oxide semiconductor device, including: a first nanostructure, wherein the first nanostructure is of a first type and has a first width; a second nanostructure adjacent to a first side of the first nanostructure, wherein the second nanostructure is of a second type and has a second width smaller than the first width; a third nanostructure adjacent to a second side of the first nanostructure, wherein the third nanostructure is of a second type and has a second width; and a first gate structure extending over and surrounding the first, second and third nanostructures; a second complementary metal oxide semiconductor device adjacent to the first complementary metal oxide semiconductor device, the second complementary metal oxide semiconductor device including: a fourth nanostructure having a third width smaller than the second width; and a second gate structure extending over and surrounding the fourth nanostructure; a plurality of isolation structures separating the first gate structure from the second gate structure; and a gate end isolation region physically contacting the first gate structure and the second gate structure, wherein the gate end isolation region is adjacent to the second nanostructure and the fourth nanostructure, wherein a first distance from the second nanostructure to the gate end isolation region is greater than a second distance from the fourth nanostructure to the gate end isolation region. In one embodiment, the gate end isolation region extends to a depth below the first gate structure and the second gate structure in a range of 10 nm to 150 nm. In one embodiment, the first type is n-type and the second type is p-type. In one embodiment, the fourth nanostructure is the second type. In one embodiment, the first width is at least twice the third width. In one embodiment, the isolation structure is parallel to the first gate structure and the second gate structure. In one embodiment, the semiconductor device includes a dummy fin located between adjacent pairs of isolation structures.

[0119] In some embodiments of the present invention, a method includes forming a fin on a substrate, wherein a first portion of the fin has a first width and a second portion of the fin has a second width greater than the first width; forming a first nanostructure on the first portion of the fin and forming a second nanostructure on the second portion of the fin; forming a first isolation structure perpendicular to the fin, wherein the first isolation structure separates the first portion of the fin from the second portion of the fin; forming a first gate stack on the first nanostructure and forming a second gate stack on the second nanostructure; and forming a second isolation structure, the second isolation structure including a first region in the first gate stack and a second region in the second gate stack, wherein the first region is a first distance from the first portion of the fin and the second region is a second distance from the second portion of the fin, wherein the first distance is less than the second distance. In one embodiment, the second isolation structure is parallel to the fin. In one embodiment, the first isolation structure includes a first dielectric material, and the second isolation structure includes a second dielectric material different from the first dielectric material. In one embodiment, the method includes forming a third nanostructure on the second portion of the fin adjacent to the second nanostructure.

[0120] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the utility model from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the utility model, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the embodiments of the utility model. Various changes, substitutions or modifications can be made to the embodiments of the utility model without departing from the spirit and scope of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: A stack of a plurality of first nanostructures is disposed on a substrate, wherein each of the plurality of first nanostructures comprises a channel region having a first width; a first gate structure located on the stack of the plurality of first nanostructures, wherein the first gate structure surrounds each of the plurality of first nanostructures, wherein a distance from a first end of the first gate structure to an adjacent first nanostructure is a first distance; A stack of a plurality of second nanostructures disposed on the substrate, wherein each of the plurality of second nanostructures comprises a channel region having a second width greater than the first width; a second gate structure located on the stack of the plurality of second nanostructures, wherein the second gate structure surrounds each of the plurality of second nanostructures, wherein a distance from a first end of the second gate structure to an adjacent second nanostructure is a second distance, and the second distance is greater than the first distance; as well as A first isolation structure continuously extends from the first end of the first gate structure to the first end of the second gate structure. 2 . The semiconductor device of claim 1 , wherein the first gate structure and the second gate structure are on a same side of the first isolation structure.

3. The semiconductor device according to claim 1, further comprising: A second isolation structure is located between the first gate structure and the second gate structure, wherein the second isolation structure is a dummy gate structure.

4. The semiconductor device according to any one of claims 1 to 3, further comprising: A stack of a plurality of third nanostructures, wherein the second gate structure surrounds each of the plurality of third nanostructures, wherein the distance from the second end of the second gate structure to an adjacent third nanostructure is a third distance, and the third distance is greater than the first distance. 5 . The semiconductor device according to claim 1 , wherein the first gate structure extends along a first direction, and the first isolation structure extends along a second direction perpendicular to the first direction. 6 . The semiconductor device of claim 1 , wherein a first portion of the first isolation structure at the first end of the first gate structure protrudes from a second portion of the first isolation structure at the first end of the second gate structure.

7. A semiconductor device, characterized in that: include: A first complementary metal oxide semiconductor device, comprising: a first nanostructure, wherein the first nanostructure is of a first type and has a first width; a second nanostructure adjacent to a first side of the first nanostructure, wherein the second nanostructure is of a second type and has a second width smaller than the first width; a third nanostructure adjacent to a second side of the first nanostructure, wherein the third nanostructure is of the second type and has the second width; and a first gate structure extending over the first nanostructure, the second nanostructure and the third nanostructure and surrounding the first nanostructure, the second nanostructure and the third nanostructure; a second complementary metal oxide semiconductor device, adjacent to the first complementary metal oxide semiconductor device, the second complementary metal oxide semiconductor device comprising: a fourth nanostructure having a third width smaller than the second width; and a second gate structure extending above the fourth nanostructure and surrounding the fourth nanostructure; a plurality of isolation structures, isolating the first gate structure from the second gate structure; and A gate end isolation region physically contacts the first gate structure and the second gate structure, wherein the gate end isolation region is adjacent to the second nanostructure and the fourth nanostructure, wherein a first distance from the second nanostructure to the gate end isolation region is greater than a second distance from the fourth nanostructure to the gate end isolation region. 8 . The semiconductor device of claim 7 , wherein the gate end isolation region extends to a depth below the first gate structure and the second gate structure in a range of 10 nm to 150 nm. 9 . The semiconductor device as claimed in claim 7 , wherein the plurality of isolation structures are parallel to the first gate structure and the second gate structure.

10. The semiconductor device according to claim 7 or 8, further comprising: A dummy fin is located between adjacent pairs of the plurality of isolation structures.

Images