Semiconductor device

Abstract

A semiconductor device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of a plurality of nanostructures disposed in a plurality of first semiconductor layers, and a gate structure wrapping the plurality of nanostructures surrounding the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device, and at least one diode electrically connected between a collector and a base of the bipolar junction device. At least one implantation region extends through the plurality of first semiconductor layers and the plurality of second semiconductor layers, wherein the plurality of second semiconductor layers are disposed between the corresponding vertically adjacent and paired plurality of first semiconductor layers. The backside interconnect structure is electrically connected to the source / drain region of the nanostructure device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an electrostatic discharge (ESD) protection device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line segment) that can be created using a manufacturing process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. This miniaturization also increases the complexity of processing and manufacturing the IC. Utility Model Content

[0003] The disclosed embodiment provides a semiconductor device, comprising a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of multiple nanostructures arranged in multiple first semiconductor layers, and a gate structure that wraps around the vertical stack of multiple nanostructures. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device, and at least one diode electrically connected between the collector and the base of the bipolar junction device. At least one implantation region extends through multiple first semiconductor layers and multiple second semiconductor layers, wherein the multiple second semiconductor layers are arranged between corresponding vertically adjacent and paired multiple first semiconductor layers. The back-side interconnect structure is electrically connected to the source / drain region of the nanostructure device.

[0004] In some embodiments, the semiconductor device further comprises: a first pad for data communication with the nanostructure device; and an electrostatic discharge (ESD) circuit electrically connected to the first pad, wherein the electrostatic discharge circuit comprises the bipolar junction device and the at least one diode.

[0005] In some embodiments, the bipolar junction device includes: a first implanted region, including multiple first impurities of a first type; a second implanted region, including multiple second impurities of a second type; a third implanted region, including multiple third impurities of the above-mentioned second type; and a first intrinsic region, located between the above-mentioned first implanted region and the above-mentioned second implanted region.

[0006] In some embodiments, the bipolar junction device includes: a second implanted region including a plurality of second impurities of a second type; a third implanted region including a plurality of third impurities of the second type; and an intrinsic region between the second implanted region and the third implanted region.

[0007] The present disclosure provides a semiconductor device, comprising: an input pad; an output pad; a first power pad; a circuit that communicates data with the input pad and the output pad and is electrically connected to the first power pad, the circuit comprising at least one nanostructure device, the at least one nanostructure device having a vertical stack of multiple semiconductor channels; an electrostatic discharge (ESD) protection circuit coupled between the first power pad and the input pad or the output pad, the electrostatic discharge protection circuit comprising: a snapback device having at least two first implanted regions, each of which extends through a multilayer lattice of alternating multiple first semiconductor layers and multiple second semiconductor layers, wherein the multiple first semiconductor layers are of a first type, the first type being different from the second type of the multiple second semiconductor layers; and at least one diode having at least two second implanted regions, each of which extends through the multilayer lattice; and a back-side interconnect structure in contact with the first nanostructure device of the at least one nanostructure device.

[0008] In some embodiments, the at least one diode includes a first diode and a second diode, and the semiconductor device further includes a second isolation region between the first diode and the second diode.

[0009] In some embodiments, the circuit includes an isolation region adjacent to the first nanostructure device.

[0010] In some embodiments, the height of an upper surface of the isolation region is substantially the same as the height of a lower surface of a lowest second semiconductor layer of the above-mentioned second semiconductor layer, and the height of an upper surface of the above-mentioned second isolation region is coplanar with the height of an upper surface of a topmost first semiconductor layer of the above-mentioned first semiconductor layer.

[0011] In some embodiments, the electrostatic discharge protection circuit includes multiple electrostatic discharge protection circuit areas, each of the above-mentioned electrostatic discharge protection circuit areas includes: a bipolar junction device having a collector implantation area and an emitter implantation area; and at least one PIN diode, each having a cathode implantation area and an anode implantation area.

[0012] In some embodiments, at least one PIN diode includes a first PIN diode and a second PIN diode, the anode implantation region of the first PIN diode is connected to the input pad or the output pad, the cathode implantation region of the second PIN diode is connected to a base implantation region of the bipolar junction device, and the cathode implantation region of the first PIN diode is connected to the anode implantation region of the second PIN diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The aspects of the present disclosure can be better understood from the subsequent embodiments and drawings. It should be noted that, according to standard industry practices, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased to make the discussion clear and understandable.

[0014] Figures 1A to 1C Schematic diagram of a circuit of a portion of an IC device according to an embodiment of the present disclosure.

[0015] FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3D , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , FIG. 7A to FIG. 7C , FIG. 8A to FIG. 8C , 9A to 9C , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11B as well as Fig.12 are diagrams of various embodiments of IC devices at various manufacturing stages according to various aspects of the present disclosure.

[0016] Figures 13 to 15 is a schematic cross-sectional side view of a portion of an IC device according to an embodiment of the present disclosure.

[0017] Fig.16 is a flow chart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure.

[0018] The reference numerals are described as follows:

[0019] 10: IC chip

[0020] 21: First semiconductor layer

[0021] 21A-21C: First semiconductor layer

[0022] 22: Nanostructures

[0023] 22A-22C: First Nanostructure

[0024] 23: Second semiconductor layer

[0025] 23A-23C: Second semiconductor layer

[0026] 24: Nanostructures

[0027] 24A-24C: Second nanostructure

[0028] 25: Multi-layer stacking

[0029] 26: Vertical Stacking

[0030] 32: Fins

[0031] 36: Isolation Area

[0032] 36A: Second isolation area

[0033] 40: Virtual gate structure

[0034] 41: Spacer layer

[0035] 45: Virtual gate layer

[0036] 47: Mask layer

[0037] 64: Groove

[0038] 74: Internal spacer

[0039] 82: Source / drain region

[0040] 92: Groove

[0041] 100: The first ESD protection circuit

[0042] 100A: Second ESD protection circuit

[0043] 100C: Power supply ESD protection circuit

[0044] 100R: ESD protection device area

[0045] 110: Substrate

[0046] 111: Input pad

[0047] 112: Output pad

[0048] 113: VDD pad

[0049] 114: VSS pad

[0050] 120: Contact

[0051] 121: Input buffer

[0052] 122: Output buffer

[0053] 130: Interlayer dielectric

[0054] 131: Etch stop layer

[0055] 150: Protected circuit

[0056] 150R: Internal circuit device area

[0057] 160: First planting area

[0058] 160A: First implantation area

[0059] 162: Second planting area

[0060] 162A: Second planting area

[0061] 170: Area

[0062] 200: Gate structure

[0063] 210: Interface layer

[0064] 250: The first ESD protection circuit

[0065] 250A: Second ESD protection circuit

[0066] 252: PIN diode

[0067] 252': PIN diode

[0068] 252A: First implantation area

[0069] 252C: Second planting area

[0070] 252i: Essential Area

[0071] 254: PIN diode

[0072] 254': PIN diode

[0073] 254A: First implantation area

[0074] 254C: Second implantation area

[0075] 254i: Essential Area

[0076] 256: Bipolar Junction Device

[0077] 256A: Bipolar Junction Device

[0078] 256B: Base implantation area

[0079] 256C: Collector implantation area

[0080] 256D: Bipolar Junction Device

[0081] 256E: Emitter implantation area

[0082] 256i: Essential area

[0083] 290: Gate filling layer

[0084] 350: ESD protection circuit area

[0085] 600: Gate dielectric layer

[0086] 800: Backside interconnect structure

[0087] 810: First rear ILD

[0088] 820: Second rear ILD

[0089] 830: First rear contact

[0090] 840: First rear trace

[0091] 900: Work function metal layer

[0092] 1000: Methods

[0093] 1100-1800: Action

[0094] B-B': Reference cross section

[0095] C-C': Reference cross section

[0096] CD1: Distance

[0097] D-D': Section line segment

[0098] VB: Base voltage DETAILED DESCRIPTION

[0099] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these are merely examples and are not intended to limit the present disclosure. For example, if the description has a first feature formed on or above a second feature, it may include an embodiment in which the first feature and the second feature are formed in direct contact, and it may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in multiple examples. The purpose of this repetition is to simplify and clarify, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0100] Further, the present disclosure may use spatially relative terms, such as "below," "below," "below," "above," "above," and the like, to describe the relationship of one element or feature to other elements or features in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein interpreted accordingly.

[0101] The present disclosure relates to electronic devices, and more particularly to electronic devices including field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as gate-all-around (GAA) FETs, nanosheet FETs, nanowire FETs, and the like. In advanced technology nodes, a backside interconnect structure may include a power rail (or "super power rail (SPR)") that is included in an integrated circuit (IC) chip to reduce routing density on the front side of the IC chip. The device substrate may be removed during the process to form the backside interconnect structure. This may increase the difficulty of including an electrostatic discharge (ESD) device for internal circuit protection of the IC chip.

[0102] In some silicon-on-insulator (SOI) applications, ESD devices may include intrinsic bipolar junction transistors (iBJTs) and P-intrinsic-N (PiN) diodes (or "PIN diodes"). "iBJTs" may refer to NiPiN and PiNiP structures, where "i" represents an intrinsic semiconductor region between N-type and P-type implants. PiN diodes with an intrinsic semiconductor layer between N and P regions or between P and P regions may be implemented with a flexible bottom insulator (FBI) process. In some semiconductor process nodes, ESD snapback devices may be formed in the device substrate. In processes where the device substrate is removed, the FBI process does not work. The limited bulk current in the back-side interconnect process may cause a high trigger voltage (or "Vt1") in the ESD snapback device. The trade-off between “SOI application” and “ESD snapback performance” may tend to reduce one or more of the performance, power, area and cost of the IC chip.

[0103] An embodiment of the present disclosure provides an IC chip, in which there is no device substrate, and an ESD snapback device is arranged in a nanosheet of the IC chip. A PIN diode string is inserted between the base and collector of an iBJT, which reduces the snapback trigger voltage Vt1 and improves the uniformity of the turn-on characteristics. The iBJT can be expanded into an array, thereby improving ESD immunity and enhancing the on-resistance Ron. In the PIN diode string, the number of PIN diodes can be adjusted for different base biases. Different iBJT structures, such as NiN, NiPN, etc., can have a PIN diode string connected thereto to promote the trigger voltage Vt1.

[0104] Embodiments achieve various advantages. Both iBJT and PIN diode strings are compatible with backside power processes and non-backside (or frontside) power processes. The intrinsic area of ​​the ESD snapback device has low leakage current. The thin bulk of the ESD snapback device improves metal routing on the front side and / or back side and improves performance, power, and area of ​​the IC chip. The array size of the iBJT can be expanded for improvement of on-resistance Ron.

[0105] The nanostructure device structure can be patterned by any suitable method. For example, the structure can be patterned using one or more lithography processes, including double-patterning or multiple patterning. Generally speaking, double patterning or multiple patterning combines lithography with a self-aligned process, allowing the created pattern to have a smaller pitch, such as a pitch that is smaller than that which can be obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate using a lithography process and patterned. Spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the nanostructure device structure.

[0106] Figures 1A to 1C is a circuit diagram of a portion of an IC chip 10 according to various embodiments. Figure 1A The schematic diagram of a circuit of a portion of an IC die 10 shows input / output (I / O) pads connected to internal circuits, and ESD circuits for protecting the internal circuits. Figure 1B is a detailed circuit diagram of a first ESD circuit according to various embodiments. Figure 1C is a detailed circuit diagram of a second ESD circuit according to various embodiments.

[0107] exist Figure 1A , a portion of an IC chip 10 is shown. The IC chip 10 includes an internal circuit or "protected circuit" 150, which is protected by the ESD protection circuit (100, 100A, 100C) to prevent damage from ESD. The protected circuit 150 may include a memory circuit, a logic circuit, or both. The logic circuit may include a processor or a processing circuit, and the processing circuit may include an application processor circuit, an image processor circuit, a graphics processor circuit, a combination thereof, etc. The protected circuit 150 may include one or more transistors, one or more diodes, and one or more passive components, such as integrated resistors, integrated capacitors, integrated inductors, etc. The protected circuit 150 may have a smaller device size (e.g., channel width), less than Figure 1A Other circuits of the IC die 10 are shown. For example, the transistors included in the protected circuit 150 may have a smaller channel width than the transistors of the input buffer 121, the output buffer 122, or both.

[0108] The protected circuit 150 may have one or more inputs for data communication with one or more input pads 111. Figure 1A 1 shows a single input pad 111. In some embodiments, the protected circuit 150 is connected to dozens or hundreds of input pads 111. The input pad 111 is connected to an input buffer 121, which is connected to one or more inputs of the protected circuit 150. In some embodiments, the input buffer 121 is not present.

[0109] The protected circuit 150 may have one or more outputs for data communication with one or more output pads 112. Figure 1A A single output pad 112 is shown. In some embodiments, the protected circuit 150 is connected to dozens or hundreds of output pads 112. The output pads 112 are connected to output buffers 122, which are connected to one or more outputs of the protected circuit 150. In some embodiments, the output buffers 122 are not present.

[0110] The protected circuit 150 may be connected to two or more power supply pads (113, 114), which may include a high voltage (VDD) pad 113 and a low voltage (VSS) pad 114. The VSS pad 114 may be connected to a ground voltage or other suitable voltage.

[0111] The ESD protection circuit (100, 100A, 100C) may include a first ESD protection circuit 100, a second ESD protection circuit 100A, and a power supply ESD protection circuit 100C. The first ESD protection circuit 100 may be connected to the input pad 111 or the output pad 112 and to the VSS pad 114. The second ESD protection circuit 100A may be connected to the input pad 111 or the output pad 112 and to the VDD pad 113. The power supply ESD protection circuit 100C may be connected to the VDD pad 113 and the VSS pad 114.

[0112] The protected circuit 150 can generate an output signal based on the input signal received through the input pad 111. The protected circuit 150 can output the output signal to the output pad 112. ESD events, such as the presence of high voltage, can be mitigated by the first ESD protection circuit 100 and / or the second ESD protection circuit 100A. For example, the high voltage at the input pad 111 can "turn on" the first ESD protection circuit 100 connected thereto, which can route the current associated with the high voltage to the VSS pad 114 (e.g., ground), so that the high voltage is quickly reduced to a level that will not harm the input buffer 121 and / or the protected circuit 150.

[0113] Figure 1B Detailed circuit diagram of the first ESD protection circuit 250 according to various embodiments. In some embodiments, the first ESD protection circuit 250 may be the first ESD protection circuit 100. The first ESD protection circuit 250 includes a bipolar junction device 256, which may be a bipolar junction transistor. The bipolar junction device 256 may include a NiPiN device, a PiNiP device, a NiPN device, a NiN device, a combination thereof, and the like. The bipolar junction device 256 may be turned on in the presence of a voltage higher than a trigger voltage Vt1, which may be much higher than the high power supply voltage VDD applied to the VDD pad 113. For example, the high power supply voltage VDD may be in the range of about 0.1 volts to about 10 volts, and the trigger voltage Vt1 may be greater than the high power supply voltage VDD, such as in the range of about 1 volt to several thousand volts or more.

[0114] The first ESD protection circuit 250 includes a PIN diode string having one or more PIN diodes 252 , 254 connected in series between a collector of a bipolar junction device 256 and a base of the bipolar junction device 256 . Figure 1B Two PIN diodes 252 and 254 are shown in FIG. In some embodiments, fewer or more PIN diodes may be included. Increasing the number of PIN diodes in the PIN diode string increases the trigger voltage Vt1 of the bipolar junction device 256 .

[0115] Figure 1C Detailed circuit diagram of the second ESD protection circuit 250A according to various embodiments. In some embodiments, the second ESD protection circuit 250A may be the second ESD protection circuit 100A. The second ESD protection circuit 250A includes a bipolar junction device 256A, which may be a bipolar junction transistor. The second ESD protection circuit 250A is similar to the first ESD protection circuit 250 in many aspects, except that the polarity of the bipolar junction device 256A and the direction of the PIN diodes 252', 254' are opposite to the polarity of the bipolar junction device 256 and the direction of the PIN diodes 252, 254, respectively.

[0116] Figures 2A to 12 2 is a diagram of various embodiments of an IC device at various manufacturing stages according to various aspects of the present disclosure. Fig.16 is a flow chart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure. Figures 2A to 12 The various manufacturing stages of the IC device shown can be based on Fig.16 method execution. Fig.161 is a flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present disclosure. The method 1000 is merely an example and is not intended to limit the present disclosure to the content explicitly described in the method 1000. Additional actions may be provided before, during, or after the method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the method. For the sake of simplicity of description, not all actions are described in detail herein. The method 1000 is described below in conjunction with Figures 2A to 12 The workpiece is described in partial perspective and / or cross-sectional views, wherein Figures 2A to 12 At various stages of fabrication according to an embodiment of method 1000. For the avoidance of doubt, throughout the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction. It should be noted that because the workpiece can be manufactured as a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0117] Figures 2A to 12 are perspective and cross-sectional views of intermediate stages in the fabrication of a FET, such as a nanosheet FET, according to some embodiments of the present disclosure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A and Fig. 10A Displays a perspective view. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B Display along Figure 2A , Figure 3A and Figure 4A A side view taken along reference section BB' (gate cutting) is shown. Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C and Fig. 10C Display shows along Figure 4A A side view taken along reference section CC' is shown (channel / fin cut). A further side view taken along reference section BB' is shown at Figure 2C and Figure 3C .

[0118] exist Figure 2A and Figure 2BIn the embodiment of the present invention, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, and may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may also be used, such as single-layer, multi-layer, or gradient substrates.

[0119] Further, in Figure 2A and Figure 2B In the embodiment, a multilayer stack 25 (or "lattice") is formed on the substrate 110, wherein the multilayer stack 25 is an alternating layer of first semiconductor layers 21A-21C (collectively referred to as the first semiconductor layer 21) and second semiconductor layers 23A-23C (collectively referred to as the second semiconductor layer 23), corresponding to Fig.16 In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for n-type nano FETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for p-type nano FETs, such as silicon germanium, etc. Each layer in the multilayer stack 25 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0120] Each of the first semiconductor layer 21 and the second semiconductor layer 23 is shown as three layers. In some embodiments, the first semiconductor layer 21 and the second semiconductor layer 23 may each include one or two layers, or may each include four or more layers in the multilayer stack 25. Although the multilayer stack 25 is shown as including the second semiconductor layer 23C as the bottommost thin layer, in some embodiments, the bottommost thin layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0121] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of the nanostructure FET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of the nanostructure FET.

[0122] exist Figure 2C In the embodiment, the internal circuit device region 150R is laterally offset from the ESD protection device region 100R. The internal circuit device region 150R may be a region of an IC chip (e.g., IC chip 10) in which an internal circuit (e.g., protected circuit 150) is disposed. The ESD protection device region 100R may be a region of an IC chip (e.g., IC chip 10) in which an ESD protection circuit (e.g., first ESD protection circuit 100, second ESD protection circuit 100A, power supply ESD protection circuit 100C) is disposed.

[0123] exist Figure 2C In the embodiment, after forming the multilayer stack 25, one or more implant operations may be performed in the ESD protection device region 100R, while the internal circuit device region 150R is protected, for example, by a photoresist mask, corresponding to Fig.16 Action 1200 of the present invention. The implantation operation may form a first implantation region 160 of a first type by a first implantation operation, and may form a second implantation region 162 of a second type by a second implantation operation. The first type may be different from the second type. For example, the first type may be N-type and the second type may be P-type. The first implantation operation may implant N-type dopants or impurities in the first implantation region 160, wherein the first implantation region 160 may be exposed by a first patterned mask (e.g., a first photoresist mask). The second implantation operation may implant P-type dopants or impurities in the second implantation region 162, wherein the second implantation region 162 may be exposed by a second patterned mask (e.g., a second photoresist mask). The implantation of the first implantation region 160 may be earlier than the implantation of the second implantation region 162, or the implantation of the second implantation region 162 may be earlier than the implantation of the first implantation region 160. The N-type dopant may include one or more of phosphorus, arsenic, antimony, or other suitable N-type dopants. The P-type dopant may include one or more of gallium, boron, boron fluoride, indium, or other suitable P-type dopants. The concentration of each of the N-type and P-type dopants may be about 10 13 cm-3 Up to 10 18 cm -3 The concentration of the N-type dopant in the first implanted region 160 may be different from the concentration of the P-type dopant in the second implanted region 162. The configuration of the first implanted region 160 and the second implanted region 162 will be described with reference to Figures 13 to 15 Discuss in more detail.

[0124] Annealing may be performed after implantation to repair implantation damage and activate P-type and / or N-type impurities. In some embodiments, in-situ doping during epitaxial growth of fins 32 and nanostructures 22, 24 may avoid additional implantation, although in-situ doping and implantation doping may be used together.

[0125] exist Figure 3A and Figure 3B In the embodiment, the vertical stack 26 of the fin 32 and the nanostructures 22 and 24 is formed in the substrate 110 and the multilayer stack 25, corresponding to Fig.16 Action 1300. In some embodiments, the formation of the nanostructures 22, 24 and the fins 32 can be formed by etching grooves in the multilayer stack 25 and the substrate 110. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. The first nanostructure 22A-22C (hereinafter also referred to as "channel") is formed by the first semiconductor layer 21, and the second nanostructure 24A-24C is formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 can be between about 18 nanometers (nm) and about 100 nm. A portion of the IC chip 10 is shown in Figure 3A and Figure 3B In the figure, two fins 32 are included to simplify the description. Figures 2A to 12 The method 1000 shown can be extended to any number of fins and is not limited to FIG. 3A to FIG. 11B Two fins 32 are shown.

[0126] The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) may be used to form the fins 32 and nanostructures 22, 24. In general, double patterning or multiple patterning processes combine lithography with self-alignment processes, allowing a pitch that is smaller than that otherwise obtainable using a direct, single lithography process. As an example of a multiple patterning process, a sacrificial layer may be formed on a substrate and patterned using a lithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may be used to pattern the fins 32.

[0127] Figure 3A and Figure 3B The fin 32 is shown with tapered sidewalls such that the width of the fin 32 and / or each of the nanostructures 22, 24 continuously increases in a direction toward the substrate 110. In these embodiments, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the widths of the fin 32 and nanostructures 22, 24 are substantially similar and each of the nanostructures 22, 24 is rectangular in shape.

[0128] exist Figure 3A and Figure 3B In the embodiment, an isolation region 36, which may be a shallow trench isolation (STI) region, is formed adjacent to the fin 32, corresponding to Fig.16 Action 1300. The formation of the isolation region 36 can be performed by depositing an insulating material over the substrate 110, the fins 32, and the nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fins 32, and the nanostructures 22, 24. Thereafter, a filling material such as those discussed above may be formed on the liner.

[0129] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material above the nanostructures 22 and 24. After the removal process is completed, the top surfaces of the nanostructures 22 and 24 may be exposed and flush with the insulating material.

[0130] The insulating material is then recessed to form the isolation regions 36. After the recessing, the nanostructures 22, 24 and upper portions of the fins 32 may protrude from between adjacent isolation regions 36. The isolation regions 36 may have a top surface that is flat, convex, concave, or a combination thereof as shown. In some embodiments, the isolation regions 36 are recessed by a suitable etching process, such as oxide removal, such as using dilute hydrofluoric acid (dHF), which is selective to the insulating material and leaves the fins 32 and nanostructures 22, 24 substantially unchanged.

[0131] FIG. 2A to FIG. 3B One embodiment of forming the fin 32 and the nanostructures 22, 24 is shown (e.g., etch last). In some embodiments, the fin 32 and / or the nanostructures 22, 24 are epitaxially grown in the trenches of the dielectric layer (e.g., etch first). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0132] In some embodiments, the spacing between the first nanostructures 22A-22C (e.g., the spacing between the first nanostructure 22B and the first nanostructure 22A or the first nanostructure 22C) is in a range between about 8 nm and about 12 nm. In some embodiments, the thickness of each of the first nanostructures 22A-22C (e.g., measured in the Z direction) is in a range between about 5 nm and about 8 nm. In some embodiments, the width of each of the first nanostructures 22A-22C (e.g., measured in the Y direction) is at least about 8 nm.

[0133] exist Figure 3C, the inner circuit device region 150R is laterally offset from the ESD protection device region 100R. In the inner circuit device region 150R, the isolation region 36 is located between the vertical stacks 26 of adjacent pairs of nanostructures 22, 24, or adjacent to a single vertical stack 26. The isolation region 36 is dug as described so that the upper surface of the isolation region 36 is located at or around the upper surface of the fin 32 and / or the lower surface of the vertical stack 26 (e.g., the lower surface of the bottom-most second nanostructure 24C).

[0134] In the ESD protection device region 100R, one or more isolation regions 36A (or “second isolation regions 36A”) are located between corresponding adjacent pairs of first implant regions 160 and second implant regions 162. For example, Figure 3C As shown, the second isolation region 36A is disposed between the first implantation region 160 on its right side and the second implantation region 162 on its left side. Figure 3C In the embodiment, the first implanted region 160A and the second implanted region 162A are "directly adjacent" to the second isolation region 36A. In this context, directly adjacent may mean adjacent to each other without an additional first implanted region 160 or second implanted region 162 interposed therebetween. In some embodiments, the second isolation region 36A may be disposed between (e.g., directly adjacent to) two first implanted regions 160, or disposed between (e.g., directly adjacent to) two second implanted regions 162.

[0135] The second isolation region 36A may be formed in the same process as the isolation region 36 of the internal circuit device region 150R, and may be made of the same material as the isolation region 36. When the isolation region 36 is dug in, the second isolation region 36A may be protected, for example, by a photoresist mask. The second isolation region 36A is higher than the isolation region 36. The upper surface of the second isolation region 36A is located at a height higher than the upper surface of the isolation region 36. Figure 3C The upper surface of the second isolation region 36A is shown to be substantially coplanar with the upper surface of the uppermost first nanostructure 22A and / or the first semiconductor layer 21A. The second isolation region 36A extending to the uppermost first semiconductor layer 21A of the first semiconductor layer 21 is advantageous for providing physical and electrical isolation between devices on both sides of the second isolation region 36A. For example, the second isolation region 36A can be located between the PIN diode 252 and the PIN diode 254, which improves the electrical isolation between the two PIN diodes 252 and 254 via the first semiconductor layer 21 and the second semiconductor layer 23.

[0136] exist Figure 2C and Figure 3CIn the description of FIG. 1 , the first implanted region 160 and the second implanted region 162 are formed earlier than the isolation region 36 and the second isolation region 36A. In some embodiments, the first implanted region 160 and the second implanted region 162 are formed after the isolation region 36 and the second isolation region 36A are formed. For example, the first implanted region 160 and the second implanted region 162 may be formed after the isolation region 36 and the second isolation region 36A are formed, and in reference to FIG. Figure 4A and Figure 4C Before the formation of the dummy gate structure 40. In some embodiments, no epitaxial structure (e.g., source / drain region) is formed when implantation is present in the BJT structure, for example, because an epitaxial barrier layer is present in the layout including the structure shown in the figure. The first implantation region 160 and the second implantation region 162 can be in reference to Figure 4C The processes are then formed without performing strained source / drain (SSD) etching in the nanostructures 22. The ESD protection device region 100R may be protected by a mask (e.g., a photoresist mask) before and after forming the first implanted region 160 and the second implanted region 162, for example, during the process of forming features (e.g., source / drain regions, gate structures, etc.) of the internal circuit device region 150R.

[0137] Further, in Figure 3A and Figure 3B In the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24 and / or isolation regions 36. By using a mask, N-type impurity implantation may be performed in the P-type region of the substrate 110, and P-type impurity implantation may be performed in the N-type region of the substrate 110. Exemplary N-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary P-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate P-type and / or N-type impurities. In some embodiments, in-situ doping during the epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid additional implantation, but in-situ doping and implantation doping may be used together.

[0138] Figure 3D For IC chip 10 along Figure 3CA cross-sectional plan view of the cross-sectional line segment D-D'. In some embodiments, the IC chip 10 may include one or more ESD protection circuit areas 350. Each of the first ESD protection circuit 100, the second ESD protection circuit 100A, the first ESD protection circuit 250, and the second ESD protection circuit 250A may include one or more ESD protection circuit areas 350. For example, the first ESD protection circuit 100 may include an array of ESD protection circuit areas 350, and the array may include two or more ESD protection circuit areas 350. The electrical interconnection between the ESD protection circuit area 350 and the input pad 111, the output pad 112, the VDD pad 113, and the VSS pad 114 will be referred to Figures 13 to 15 A more detailed description is given in Figure 3D , the second isolation regions 36A are shown to be separated from each other in the X-axis direction.

[0139] exist FIG. 4A to FIG. 4C In the embodiment of the present invention, a dummy or sacrificial gate structure 40 is formed over the fin 32 and / or the nanostructures 22, 24. A dummy gate layer 45 is formed over the fin 32 and / or the nanostructures 22, 24. The dummy gate layer 45 may be made of a material having a high etch selectivity to the isolation region 36. The dummy gate layer 45 may be a conductive, semi-conductive or non-conductive material and may be selected from a group including amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide and metal. The deposition of the dummy gate layer 45 may be performed by physical vapor deposition (PVD), CVD, sputtering deposition or other techniques for depositing the selected material. A mask layer 47 is formed over the dummy gate layer 45 and may include, for example, silicon nitride, silicon oxynitride, etc. The mask layer 47 may include one or more thin layers, such as a first mask layer and a second mask layer. The first mask layer may be formed in a first deposition process, and the second mask layer may be formed in a second deposition process after the first deposition process. In some embodiments, before the dummy gate layer 45, a gate dielectric layer is formed between the dummy gate layer 45 and the fins 32 and / or the nanostructures 22 and 24.

[0140] The spacer layer or sidewall spacer 41 is formed on the sidewalls of the mask layer 47 and the dummy gate layer 45, and covers the mask layer 47 and the dummy gate layer 45. The spacer layer 41 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., and according to some embodiments, the spacer layer 41 may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The spacer layer 41 may be formed by depositing a spacer material layer (not shown) above the mask layer 47 and the dummy gate layer 45. In some embodiments, the spacer layer 41 includes one or more material layers. For example, the spacer layer 41 may include a first spacer layer in contact with the dummy gate structure 40, and a second spacer layer in contact with the first spacer layer. The first spacer layer may be formed in a first deposition process, and the second spacer layer may be formed in a second deposition process after the first deposition process. According to some embodiments, some portions of the spacer material layer between the dummy gate structures 40 are removed by an anisotropic etching process.

[0141] FIG. 4A to FIG. 4C A process for forming the spacer layer 41 is shown. In some embodiments, the formation of the spacer layer 41 may alternatively or additionally be arranged after the removal of the dummy gate layer 45. In these embodiments, the dummy gate layer 45 is removed, leaving an opening, and the spacer layer 41 may be formed by conformally coating the material of the spacer layer 41 along the sidewalls of the opening. Then, before forming an active gate such as the gate structure 200, the conformally coated material may be removed from the bottom of the opening corresponding to the top surface of the uppermost channel (e.g., the first nanostructure 22A).

[0142] exist FIG. 5A to FIG. 5C In the embodiment, an etching process is performed to etch the protruding fins 32 and / or the portions of the nanostructures 22 and 24 that are not covered by the dummy gate structure 40, and to bring about the structure as shown. The digging may be anisotropic, so that the portions of the fins 32 directly below the dummy gate structure 40 and the spacer layer 41 are protected and not etched. According to some embodiments, the top surface of the dug fins 32 may be substantially coplanar with the top surface of the isolation region 36, as shown. According to some other embodiments, the top surface of the dug fins 32 may be lower than the top surface of the isolation region 36. To simplify the description, Figure 5C Two vertical stacks of nanostructures 22 , 24 are shown after the etching process. In general, the etching process may be used to form any suitable number of vertical stacks of nanostructures 22 , 24 over the fin 32 .

[0143] FIG. 6A to FIG. 6C and 7A to 7CThe formation of the internal spacers 74 is shown. A selective etching process is performed to dig into the end portions of the nanostructures 24 exposed by the openings in the spacer layer 41 while substantially leaving the nanostructures 22 undamaged. After the selective etching process, recesses 64 are formed in the nanostructures 24 at the locations where the removed end portions were previously located. The resulting structure is shown in FIG. Fig. 6A To Figure 6D.

[0144] Next, an inner spacer layer is formed to fill the recess 64 in the nanostructure 24 formed by the previous selective etching process. The inner spacer layer can be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), etc., and is formed by a suitable deposition method, such as PVD, CVD, ALD, etc. An etching process such as an anisotropic etching process is performed to remove the portion of the inner spacer layer disposed outside the recess in the nanostructure 24. The remaining portion of the inner spacer layer (e.g., the portion disposed within the recess 64 in the nanostructure 24) forms an inner spacer 74. The resulting structure is shown in FIG. FIG. 7A to FIG. 7C middle.

[0145] FIG. 8A to FIG. 8C The formation of source / drain regions 82 is shown, corresponding to Fig.16 Action 1400. The source / drain region may refer to the source or the drain, whether individually or collectively depending on the context. In the illustrated embodiment, the source / drain region 82 is epitaxially grown from an epitaxial material. In some embodiments, the source / drain region 82 applies stress in the corresponding channel (first nanostructure 22A-22C) to improve performance. The formation of the source / drain region 82 allows each virtual gate structure 40 to be disposed between corresponding adjacent and paired source / drain regions 82. In some embodiments, the spacer layer 41 separates the source / drain region 82 from the virtual gate layer 45 at an appropriate lateral distance to prevent electrical bridging to a gate subsequently formed in the obtained device.

[0146] The source / drain region 82 may include any acceptable material, such as a material suitable for an N-type or P-type device. In some embodiments, for an N-type device, the source / drain region 82 includes a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. According to some embodiments, when a P-type device is formed, the source / drain region 82 includes a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 82 may have a surface raised from a corresponding surface of the fin and may have a facet. In some embodiments, adjacent source / drain regions 82 may merge to form a single source / drain region 82 adjacent to two adjacent fins 32.

[0147] The source / drain regions 82 may be implanted with dopants and then annealed. The source / drain regions may have a thickness between about 10 19 cm -3 With about 10 21 cm -3 The N-type and / or P-type impurities used in the source / drain regions 82 may be any of the impurities discussed previously. In some embodiments, the source / drain regions 82 are in-situ doped during growth. Next, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) may be formed to cover the dummy gate structure 40 and the source / drain regions 82, wherein the CESL and ILD are not shown in the figure for simplicity of illustration. FIG. 8A to FIG. 8C middle.

[0148] exist 9A to 9C In the embodiment, the second nanostructures 24A-24C, the mask layer 47 and the dummy gate layer 45 are removed to release the fin channel (the first nanostructures 22A-22C), corresponding to Fig.16 Action 1500. A planarization process such as CMP is performed to planarize the top surface of the dummy gate layer 45 and the gate spacer layer (spacer layer 41). The planarization process may also remove the mask layer 47 (see FIG. 4 ) on the dummy gate layer 45. Fig. 8A ), and a portion of the spacer layer 41 along the sidewall of the mask layer 47. Therefore, the top surface of the dummy gate layer 45 is exposed.

[0149] Next, the dummy gate layer 45 is removed in an etching process to form the recess 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, wherein the reactive gas selectively etches the dummy gate layer 45 while not etching the spacer layer 41. When the dummy gate dielectric is present, the dummy gate dielectric may be used as an etch stop layer when etching the dummy gate layer 45. Then, the dummy gate dielectric may be removed after removing the dummy gate layer 45.

[0150] The nanostructure 24 is removed to release the nanostructure 22. After the nanostructure 24 is removed, the nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of the substrate 110) and stacked vertically. The nanosheets may be collectively referred to as a channel (nanostructure 22) of a nanostructure device (e.g., a nanosheet FET (NSFET)). During the removal of the nanostructure 24, the ESD protection device region 100R is protected, for example, by a mask including a photoresist, so that the second semiconductor layer 23 is retained after the nanostructure 24 is removed.

[0151] In some embodiments, the selective etching process for removing the nanostructure 24 uses an etchant that is selective to the material of the nanostructure 24, so that the nanostructure 24 is removed without substantially damaging the nanostructure 22. In some embodiments, the etching process is an isotropic etching process, using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, or a combination thereof.

[0152] In some embodiments, nanostructures 24 are removed and nanostructures 22 are patterned to form channel regions for both PFETs and NFETs. However, in some embodiments, nanostructures 24 may be removed and nanostructures 22 may be patterned to form channel regions for a first nanostructure device, and nanostructures 22 may be removed and nanostructures 24 may be patterned to form channel regions for a second nanostructure device. In some embodiments, nanostructures 22 may be removed and nanostructures 24 may be patterned to form channel regions for a first nanostructure device, and nanostructures 24 may be removed and nanostructures 22 may be patterned to form channel regions for a second nanostructure device. In some embodiments, nanostructures 22 may be removed and nanostructures 24 may be patterned to form channel regions for both PFETs and NFETs.

[0153] In some embodiments, the nanosheet (nanostructure 22) of the nanostructure device is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping can be performed by an isotropic etching process that is selective to the nanosheet (nanostructure 22). After the reshaping, the nanosheet (nanostructure 22) can exhibit a dog bone shape, wherein the central portion of the nanosheet (nanostructure 22) is thinner than the peripheral portion of the nanosheet (nanostructure 22) along the X direction.

[0154] Then, in FIG. 10A to FIG. 10C In the embodiment, a replacement gate such as gate structure 200 is formed, corresponding to Fig.16 Each gate structure 200 generally includes an interfacial layer (IL) 210, a gate dielectric layer 600, and a gate fill layer 290. In some embodiments, the gate structure 200 further includes a work function metal layer. The formation of the gate structure 200 will refer to Fig.12 A more detailed description is given.

[0155] Fig.11AA semiconductor device including an interlayer dielectric (ILD) 130 and an etch stop layer (ESL) 131 is shown. The interlayer dielectric 130 provides electrical isolation between various components of the semiconductor device previously described, such as between the gate structure 200 and subsequently formed source / drain contacts. The etch stop layer 131 may be formed prior to the formation of the interlayer dielectric 130 and may be laterally located between the interlayer dielectric 130 and the spacer layer 41 and vertically located between the interlayer dielectric 130 and the source / drain regions 82. In some embodiments, the insulating material forming the interlayer dielectric 130 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low dielectric constant (low-k value) dielectrics such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxide or porous oxide (e.g., xerogel / aerogel), etc., or a combination thereof. The dielectric material used to form the interlayer dielectric 130 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), sub-atmospheric pressure chemical vapor deposition (SACVD), FCVD, spin-on, etc., or a combination thereof. In some embodiments, the etch stop layer 131 is or includes a dielectric material, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, or other suitable materials. The dielectric material used to form the etch stop layer 131 can be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or a combination thereof. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1 nm to about 5 nm.

[0156] Fig. 11B According to various embodiments, a semiconductor device including a backside interconnect structure 800 is shown. For clarity of description, Fig. 11B In some embodiments, the front-side interconnection features are formed (corresponding to Fig.16 After the substrate 110 and optionally the fins 32 are thinned or removed, a backside interconnect structure 800 is formed, corresponding to Fig.161800. A first backside ILD 810 may be formed on the backside of the semiconductor device. The materials and formation processes may be similar to those described with reference to the interlayer dielectric 130. Next, a first removal operation, such as an etching operation, may be performed to pattern the first backside ILD 810 and optionally the fins 32 to form a first opening exposing one or more source / drain regions 82. A first backside contact 830 (or via) is formed in one of the openings and contacts the backside of the source / drain region 82. In some embodiments, silicide is formed between the first backside contact 830 and the source / drain region. A second backside ILD 820 is formed on the first backside ILD 810. The materials and formation processes may be similar to those described with reference to the interlayer dielectric 130. A second opening is formed in the second backside ILD 820 by a second removal process (e.g., a second etching operation) of patterning the second backside ILD 820. A first backside trace or line 840 is formed in the second opening. The formation of the first backside contact 830 may be similar to the formation of the contact 120 in many respects.

[0157] Fig.12 According to various embodiments, Fig. 10B The gate structure 200 is disposed above and between the channels (first nanostructures 22A-22C), respectively. In some embodiments, the gate structure 200 is disposed above and between the channels (first nanostructures 22A-22C), wherein the channels (first nanostructures 22A-22C) are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interface layer (IL) 210, one or more gate dielectric layers 600, one or more work function tuning layers (work function metal layers 900), and a metal filling layer 290.

[0158] The interface layer 210 may be an oxide of the material of the channel (first nanostructures 22A-22C) and is formed on the exposed areas of the channel (first nanostructures 22A-22C) and the top surface of the fin 32. The interface layer 210 promotes adhesion of the gate dielectric layer 600 to the channel (first nanostructures 22A-22C). In some embodiments, the interface layer 210 has a thickness of about 5 angstroms. ) to a thickness of about 50 angstroms. In some embodiments, the interface layer 210 has a thickness of about 10 angstroms. Too thin a thickness of the interface layer 210 may result in voids or insufficient adhesion. Too thick an interface layer 210 may consume the gate fill window, which is related to the threshold voltage tuning and resistance described previously. In some embodiments, the interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage tuning.

[0159] The gate dielectric layer 600 may be formed on the interface layer 210. In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 angstroms to about 100 angstroms.

[0160] In some embodiments, the gate dielectric layer 600 may include a concentration of dopants to achieve threshold voltage tuning, such as metal ions driven into the high-k gate dielectric from La2O3, MgO, Y2O3, TiO2, Al2O3, Nb2O5, etc., or boron ions driven into the high-k gate dielectric from B2O3. As an example, for an N-type transistor device, a higher concentration of lanthanum ions can reduce the threshold voltage relative to a layer with a lower concentration or no lanthanum ions, and vice versa for a P-type device. In some embodiments, the gate dielectric layer 600 of certain transistor devices (e.g., input-output (IO) transistors) does not contain dopants that are present in certain other transistor devices (e.g., N-type core logic transistors or P-type IO transistors). For example, in an N-type IO transistor, a relatively high threshold voltage is required, so the high-k dielectric layer of the IO transistor is preferably free of lanthanum ions, which would otherwise reduce the threshold voltage.

[0161] In some embodiments, the gate structure 200 further includes one or more work function metal layers, collectively represented by the work function metal layer 900. When configured as an NFET, the work function metal layer 900 of the GAA device 20 may include at least an N-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. In some embodiments, the N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The in-situ capping layer is formed on the N-type work function metal layer and may include TiN, TiSiN, TaN, or other suitable materials. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which may cause an undesirable shift in the threshold voltage. The oxygen barrier layer may be formed of a dielectric material that prevents oxygen from penetrating into the N-type work function metal layer and may protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or other suitable materials. In some embodiments, the work function metal layer 900 includes more or less thin layers than the thin layers described.

[0162] The work function metal layer 900 may further include one or more barrier layers, the barrier layers including metal nitrides such as TiN, WN, MoN, TaN, etc. Each of the one or more barrier layers may have a thickness ranging from about 5 angstroms to about 20 angstroms. Including one or more barrier layers can provide additional threshold voltage tuning flexibility. Generally, each additional barrier layer increases the threshold voltage. Thus, for NFETs, higher threshold voltage devices (e.g., IO transistor devices) may have at least one or more additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have fewer or no additional barrier layers. For PFETs, higher threshold voltage devices (e.g., IO transistor devices) may have fewer or no additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have at least one or more additional barrier layers. In the previous discussion, the threshold voltage is described in terms of magnitude. As an example, an NFET IO transistor and a PFET IO transistor may have threshold voltages that are similar in magnitude, but opposite in polarity, e.g., +1 volt for the NFET IO transistor and -1 volt for the PFET IO transistor. Thus, because each additional barrier layer increases the threshold voltage in absolute value (e.g., +0.1 volt / layer), this increase imparts an increase in the threshold voltage (magnitude) of the NFET transistor and a decrease in the threshold voltage (magnitude) of the PFET transistor.

[0163] The gate structure 200 also includes a metal fill layer 290. The metal fill layer 290 may include a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. Between the channels (first nanostructures 22A-22C), the metal fill layer 290 is circumferentially surrounded (in the cross-sectional view) by one or more work function metal layers 900, which are then circumferentially surrounded by a gate dielectric layer 600, which is circumferentially surrounded by an interface layer 210. The gate structure 200 may also include a glue layer formed between the one or more work function metal layers 900 and the metal fill layer 290 to increase adhesion. To simplify the description, the glue layer is not specifically shown in FIG. Fig.12 In some embodiments, a conductive layer is formed over the gate structure 200 and contacts the metal fill layer 290, the one or more work function metal layers 900, and the gate dielectric layer 600. The conductive layer may include fluorine-free tungsten (FFW) or other suitable materials. In some embodiments, a dielectric cap layer is present over the conductive layer.

[0164] Additional processes may be performed after the semiconductor device is manufactured. For example, a gate contact electrically coupled to the gate structure 200 may be formed, and a source / drain contact electrically coupled to the source / drain region 82 may be formed. Additional contacts (or "implantation contacts") electrically coupled to the first implant region 160 and the second implant region 162 may be formed. An interconnect structure may then be formed over the source / drain contacts, the gate contacts, and the implant contacts. The interconnect structure may include a plurality of interconnect layers, each of which may include one or more dielectric layers and metal features embedded therein, such as conductive traces and conductive vias, which form electrical connections between devices of the IC chip 10. In some embodiments, a conductive layer or conductive cap is present over the gate structure 200. In some embodiments, a dielectric cap layer is present over the gate structure 200 and / or over the source / drain contacts. The configuration where the dielectric capping layer is only present over the gate structure 200 (e.g., no second capping layer is present over the source / drain contacts) may be referred to as a “single self aligned contact (SAC)” structure, while the configuration where the capping layer is present over both the gate structure 200 and the source / drain contacts may be referred to as a “double SAC” structure.

[0165] Figures 13 to 15 is a cross-sectional side view of a first ESD protection circuit 250 according to various embodiments. Fig.13 FIG. 2 is a side view of a first ESD protection circuit 250 including a bipolar junction device 256 .

[0166] Fig.14is a side view of a bipolar junction device 256A according to another embodiment. Fig.15 FIG. 2 is a side view of a bipolar junction device (NiN device) 256D according to yet other embodiments.

[0167] exist Fig.13 In the embodiment, the ESD protection circuit 250 includes a bipolar junction device 256 and PIN diodes 252 and 254 electrically connected thereto. Fig.13 The bipolar junction device 256 shown may be a NiPiN or PiNiP intrinsic bipolar junction transistor (iBJT), and may be referred to as an iBJT 256. The bipolar junction device 256 includes a collector implant region 256C and an emitter implant region 256E separated by a base implant region 256B. The base implant region 256B is separated from the corresponding collector implant region 256C or emitter implant region 256E on either side by an intrinsic region 256i. Each intrinsic region 256i may be substantially free of dopant impurities. In some embodiments, the intrinsic region 256i may be very lightly doped with one or more dopant impurities. In some embodiments, the collector implant region 256C and the emitter implant region 256E are N-type implant regions, while the base implant region 256B is a P-type implant region, which may be connected to the base implant region 256B. Figure 2C and Figure 3C The first implant region 160 and the second implant region 162 are shown to be the same or similar. In some embodiments, the collector implant region 256C and the emitter implant region 256E are P-type implant regions, and the base implant region 256B is an N-type implant region. The width of each of the base implant region 256B, the emitter implant region 256E, and the collector implant region 256C can be different or the same. For example, in Fig.13 In some embodiments, the collector implant region 256C and the emitter implant region 256E may be wider than the base implant region 256B. In some embodiments, the widths of the collector implant region 256C and the emitter implant region 256E are substantially the same as each other. The impurity concentration in each of the base implant region 256B, the collector implant region 256C, and the emitter implant region 256E may be substantially the same, or one or more of the base implant region 256B, the collector implant region 256C, and the emitter implant region 256E may have a higher or lower concentration than another one or more of the base implant region 256B, the collector implant region 256C, and the emitter implant region 256E.

[0168] Each of the PIN diodes 252, 254 includes a corresponding first implanted region 252A, 254A and a corresponding second implanted region 252C, 254C. The first implanted regions 252A, 254A may be referred to as anode implanted regions, and the second implanted regions 252C, 254C may be referred to as cathode implanted regions. The PIN diodes 252, 254 are separated from each other by a second isolation region 36A, as shown. Each of the first (anode) implanted regions 252A, 254A is separated from the second (cathode) implanted region 252C, 254C by a corresponding intrinsic region 252i, 254i, which may be similar to the intrinsic region 256i described with reference to the bipolar junction device 256. The second implanted region 252C and the first implanted region 252A may be separated from the second isolation region 36A by an intrinsic region, which is shown but not specifically labeled to simplify the diagram. In some embodiments, the first (anode) implanted regions 252A, 254A are P-type implanted regions, and the second (cathode) implanted regions 252C, 254C are N-type implanted regions.

[0169] The IC chip 10 may further include a contact 120 formed over the source / drain region 82 in the internal circuit device region 150R and over the base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the first implant region 254A, the second implant region 252C, the second implant region 254C, the intrinsic region 256i, the intrinsic region 252i, and the intrinsic region 254i in the ESD protection device region 100R. The contact 120 may include a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The contact 120 may be surrounded by a barrier layer (not shown) such as SiN or TiN, which helps prevent or reduce diffusion of material from or into the contact 120. A silicide layer may also be formed between the source / drain region 82 and the contact 120 to reduce the source / drain contact resistance. The silicide layer includes nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. In some embodiments, the thickness of the silicide layer (in the Z direction) is in the range of about 0.5 nm to about 5 nm. In some embodiments, the height of the contact 120 may be in the range of about 1 nm to about 50 nm.

[0170] The electrical interconnections between the illustrated components of the ESD protection circuit 250 are shown in FIG. Fig.13The collector implant region 256C and the first (anode) implant region 252A may be electrically connected to each other and to one of the input pad 111 or the output pad 112. The base implant region 256B is electrically connected to the cathode implant region of the PIN diode 254. The emitter implant region 256E is electrically connected to the VSS pad 114 (or the VDD pad 113). The second (cathode) implant region 252C is electrically connected to the first (anode) implant region 254A.

[0171] In some embodiments, the base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C may extend to substantially the same depth (eg, see FIG. 1 ). Figure 2C ). In some embodiments, one or more of the base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C extend to a different depth than the others of the base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C. For example, Fig.13As shown, the collector implant region 256C extends to a depth deeper than the base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C. For example, the base implant region 256B and the collector implant region 256C may extend to a shallower depth than the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C of the PIN diodes 252 and 254. In some embodiments, the collector implant region 256C partially extends into the fin 32. In some embodiments, each of the base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C partially extends through the bottommost second semiconductor layer 23. The base implant region 256B, the collector implant region 256C, the emitter implant region 256E, the first implant region 252A, the second implant region 252C, the first implant region 254A, and the second implant region 254C are disposed deeper than the bottommost region of the nanostructure (the first semiconductor layer 21, the second semiconductor layer 23), which is beneficial for carriers to mostly move through SiGe when the bipolar junction device (iBJT) 256 is turned on.

[0172] During an ESD event, the voltage at the input pad 111 or the output pad 112 may exceed the trigger voltage Vt1 of the bipolar junction device 256, causing the bipolar junction device 256 to snap back and conduct current to the VSS pad 114 or the VDD pad 113. The bipolar junction device (iBJT) 256 does not require a large volume and can be formed of SiGe instead of a nanosheet channel, such as Fig.13As shown. Both the Si layer (first semiconductor layer 21) and the SiGe layer (second semiconductor layer 23) conduct electrons, providing a discharge path. When used as the base implant region 256B, the P+ implant can be biased or connected to a trigger circuit. When an ESD event occurs, the diode string including the PIN diodes 252 and 254 turns on and uniformly raises the potential at the base implant region 256B to trigger the bipolar junction device (iBJT) 256. Generally speaking, during an ESD event, a larger current is conducted through the SiGe layer (second semiconductor layer 23) than through the Si layer (first semiconductor layer 21). It may be advantageous for the base implant region 256B, the collector implant region 256C, and the emitter implant region 256E of the bipolar junction device (iBJT) 256 to extend through the lowermost SiGe layer (second semiconductor layer 23) to increase the discharge rate through the bipolar junction device (iBJT) 256.

[0173] exist Fig.14 , a bipolar junction device 256A is shown, which includes a NiPN or PiNP configuration of a base implant region 256B, a collector implant region 256C, and an emitter implant region 256E, which may be referred to as an NPiN snapback device 256A or a PNiP snapback device 256A. As shown, the intrinsic region 256i between the base implant region 256B and the collector implant region 256C may be omitted. In other words, the base implant region 256B may be directly adjacent to the collector implant region 256C, with substantially no intrinsic silicon or silicon germanium between the two. Fig.14 Removing the intrinsic region 256i near the collector implant region 256C as shown can further reduce the trigger voltage Vt1 in the NPiN snapback device (bipolar junction device 256A).

[0174] exist Fig.15 , a bipolar junction device 256D is shown, including a NiN or PiP configuration that omits the collector implant region 256C and the emitter implant region 256E, which may be referred to as a NiN snapback device 256D or a PiP snapback device 256D. In the NiN configuration, the NiN snapback device (bipolar junction device 256D) omits the P+ base implant region 256B, which is beneficial for increasing the beta gain. The contact 120 on the back side of the fin 32 carries the base voltage VB, which acts as a base bias voltage to reduce the trigger voltage Vt1.

[0175] Embodiments may provide numerous advantages. The bipolar junction devices 256, 256A, 256D of the iBJT and the PIN diodes 252, 254 of the PIN diode string are compatible with processes including the backside interconnect structure 800 and processes that omit the backside interconnect structure 800. The intrinsic area 256i of the snapback device (bipolar junction device 256, 256A, 256D) reduces leakage. When used in conjunction with the backside interconnect structure 800, the thin body of the snapback device (bipolar junction device 256, 256A, 256D) improves the flexibility of front-side and back-side metal routing, and also improves performance, power, and area. The array size of the bipolar junction devices 256, 256A, 256D of the iBJT can be expanded to improve the on-resistance Ron.

[0176] According to at least one embodiment of the present disclosure, a semiconductor device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of multiple nanostructures arranged in multiple first semiconductor layers, and a gate structure that wraps around the multiple nanostructures of the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device, and at least one diode electrically connected between the collector and the base of the bipolar junction device. At least one implantation region extends through multiple first semiconductor layers and multiple second semiconductor layers, wherein the multiple second semiconductor layers are arranged between corresponding vertically adjacent and paired multiple first semiconductor layers. The back-side interconnect structure is electrically connected to the source / drain region of the nanostructure device.

[0177] In one or more embodiments, the semiconductor device further comprises a first pad for data communication with the nanostructure device; and an electrostatic discharge (ESD) circuit electrically connected to the first pad, the electrostatic discharge circuit comprising a bipolar junction device and at least one diode.

[0178] In one or more embodiments, the bipolar junction device includes a first implanted region comprising a plurality of first impurities of a first type; a second implanted region comprising a plurality of second impurities of a second type; a third implanted region comprising a plurality of third impurities of the second type; and a first intrinsic region between the first implanted region and the second implanted region.

[0179] In one or more embodiments, the bipolar junction device further includes a second intrinsic region between the first implanted region and the third implanted region.

[0180] In one or more embodiments, the bipolar junction device includes a second implanted region including a second plurality of second impurities of a second type; a third implanted region including a third plurality of second impurities of a second type; and an intrinsic region between the second implanted region and the third implanted region.

[0181] In one or more embodiments, a backside contact is in contact with the intrinsic region, the backside contact being biased with a base voltage during operation.

[0182] According to at least one embodiment of the present disclosure, a semiconductor device includes: an input pad; an output pad; a first power pad; a circuit that communicates data with the input pad and the output pad and is electrically connected to the first power pad, the circuit including at least one nanostructure device, at least one nanostructure device having a vertical stack of multiple semiconductor channels; an electrostatic discharge (ESD) protection circuit coupled between the first power pad and the input pad or the output pad, the electrostatic discharge protection circuit including: a snapback device having at least two first implanted regions, each of which extends through a multilayer lattice of alternating multiple first semiconductor layers and multiple second semiconductor layers, wherein the multiple first semiconductor layers are of a first type, and the first type is different from the second type of the multiple second semiconductor layers; and at least one diode having at least two second implanted regions, each of which extends through the multilayer lattice; and a backside interconnect structure in contact with the first nanostructure device of at least one nanostructure device.

[0183] In one or more embodiments, the at least one diode includes a first diode and a second diode, and the semiconductor device further includes a second isolation region between the first diode and the second diode.

[0184] In one or more embodiments, the circuit includes an isolation region adjacent to the first nanostructure device.

[0185] In one or more embodiments, the height of the upper surface of the isolation region is substantially the same as the height of the lower surface of the lowest second semiconductor layer of the second semiconductor layer, and the height of the upper surface of the second isolation region is coplanar with the upper surface of the topmost first semiconductor layer of the first semiconductor layer.

[0186] In one or more embodiments, the electrostatic discharge protection circuit includes multiple electrostatic discharge protection circuit areas, each of the multiple electrostatic discharge protection circuit areas includes: a bipolar junction device having a collector implantation area and an emitter implantation area; and at least one PIN diode, each having a cathode implantation area and an anode implantation area.

[0187] In one or more embodiments, at least one PIN diode includes a first PIN diode and a second PIN diode, the anode implant region of the first PIN diode is connected to the input pad or the output pad, the cathode implant region of the second PIN diode is connected to the base implant region of the bipolar junction device, and the cathode implant region of the first PIN diode is connected to the anode implant region of the second PIN diode.

[0188] In one or more embodiments, the first semiconductor layer is silicon and the second semiconductor layer is silicon germanium.

[0189] According to at least one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a multilayer structure of alternating multiple first semiconductor layers and multiple second semiconductor layers on a substrate; forming multiple implantation regions of a snapback device in a first region of the multilayer structure; forming a vertical stack of multiple nanosheets by patterning the multilayer structure in a second region of the multilayer structure, wherein the second region is offset from the first region; forming multiple source / drain regions adjacent to the vertical stack; forming a gate structure that wraps around the multiple nanosheets that surround the vertical stack; and forming multiple corresponding contacts, the multiple corresponding contacts contacting at least one of the multiple implantation regions and the multiple source / drain regions.

[0190] In one or more embodiments, the plurality of implantation regions include a first implantation region and a second implantation region separated from each other by an intrinsic region.

[0191] In one or more embodiments, the method for manufacturing the semiconductor device further includes: removing the substrate; and forming a backside interconnect structure, wherein the backside interconnect structure contacts at least one of the plurality of source / drain regions.

[0192] In one or more embodiments, the plurality of implanted regions are formed prior to forming the vertical stack.

[0193] In one or more embodiments, the method for manufacturing the semiconductor device further includes: forming an isolation region between the vertical stack and an adjacent vertical stack; and forming a second isolation region in the first region, wherein the second isolation region is higher than the isolation region.

[0194] In one or more embodiments, the formation of the plurality of implanted regions is later than the formation of the isolation region and the formation of the second isolation region.

[0195] In one or more embodiments, the method for manufacturing the semiconductor device further includes: forming a plurality of second implantation regions of a diode string; and electrically connecting the diode string to the snapback device.

[0196] The foregoing disclosure summarizes the features of multiple embodiments so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to accomplish the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A first circuit area, comprising: A nanostructure device having a vertical stack of a plurality of nanostructures disposed in a plurality of first semiconductor layers, and a gate structure wrapping around the nanostructures of the vertical stack; a second circuit region, offset from the first circuit region, and comprising: a bipolar junction device electrically connected to the nanostructure device; and at least one diode electrically connected between a collector and a base of the bipolar junction device; at least one implantation region extending through the first semiconductor layer and a plurality of second semiconductor layers, wherein the second semiconductor layers are disposed between corresponding vertically adjacent pairs of the first semiconductor layers; and A back-side interconnect structure is electrically connected to a source / drain region of the nanostructure device.

2. The semiconductor device according to claim 1, wherein Also includes: a first bonding pad, used for data communication with the nanostructure device; and An electrostatic discharge (ESD) circuit is electrically connected to the first pad, and the electrostatic discharge circuit includes the bipolar junction device and the at least one diode.

3. The semiconductor device according to claim 1, wherein: The bipolar junction device comprises: a first implantation region including a plurality of first impurities of a first type; a second implantation region including a plurality of second impurities of a second type; a third implantation region, comprising a plurality of third impurities of the second type; and A first intrinsic region is located between the first implantation region and the second implantation region.

4. The semiconductor device according to claim 1, wherein: The bipolar junction device comprises: a second implantation region including a plurality of second impurities of a second type; a third implantation region, comprising a plurality of third impurities of the second type; and An intrinsic region is located between the second implantation region and the third implantation region.

5. A semiconductor device, characterized in that: include: An input pad; an output pad; a first power pad; a circuit in data communication with the input pad and the output pad and electrically connected to the first power pad, the circuit comprising at least one nanostructure device having a vertical stack of a plurality of semiconductor channels; An electrostatic discharge (ESD) protection circuit is coupled between the first power pad and the input pad or the output pad, and the electrostatic discharge protection circuit includes: A snapback device having at least two first implanted regions, each of which extends through a multilayer lattice of alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers are of a first type that is different from a second type of the second semiconductor layers; and at least one diode having at least two second implanted regions, each of which extends through the multilayer lattice; and A back-side interconnect structure contacts a first nanostructure device of the at least one nanostructure device.

6. The semiconductor device according to claim 5, wherein: The at least one diode includes a first diode and a second diode, and the semiconductor device further includes a second isolation region between the first diode and the second diode.

7. The semiconductor device according to claim 6, wherein: The circuit includes an isolation region adjacent to the first nanostructure device.

8. The semiconductor device according to claim 7, wherein: The height of an upper surface of the isolation region is substantially the same as the height of a lower surface of a lowest second semiconductor layer of the second semiconductor layer, and the height of an upper surface of the second isolation region is coplanar with the height of an upper surface of a topmost first semiconductor layer of the first semiconductor layer.

9. The semiconductor device according to claim 5, wherein: The electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection circuit areas, each of which includes: A bipolar junction device having a collector implant region and an emitter implant region; and At least one PIN diode, each having a cathode implantation region and an anode implantation region.

10. The semiconductor device according to claim 9, wherein: The at least one PIN diode includes a first PIN diode and a second PIN diode, the anode implantation region of the first PIN diode is connected to the input pad or the output pad, the cathode implantation region of the second PIN diode is connected to a base implantation region of the bipolar junction device, and the cathode implantation region of the first PIN diode is connected to the anode implantation region of the second PIN diode.

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