Display panel and display device

Abstract

The embodiment of the utility model provides a display panel, and belongs to the technical field of display. The display panel comprises a display area and a peripheral area, and the display panel comprises a driving backboard and a light-emitting functional layer which are stacked. The driving backboard comprises a substrate and a driving circuit layer on the first surface of the substrate, and the light-emitting functional layer comprises a plurality of light-emitting units distributed in an array. The driving circuit layer comprises a first conductive structure, the first conductive structure comprises a plurality of first signal lines and a plurality of second signal lines, the first signal lines extend in the first direction, the second signal lines extend in the second direction, the first direction intersects with the second direction, the first signal lines are electrically connected with the second signal lines, and the second signal lines are electrically connected with the first conductive structure. The first conductive structure is at least located in the display area and is used for providing a negative power supply voltage for the plurality of light-emitting units. According to the embodiment of the invention, the problem of high power consumption of the display panel can be solved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display devices have a wide range of application scenarios in life, such as mobile phones, tablet computers and other electronic devices. Display panels are an important component of display devices.

[0003] In the related art, the display panel includes a stacked driving backplane and a light-emitting functional layer. The display panel includes a display area and a peripheral area, and the peripheral area surrounds the display area. The light-emitting functional layer includes a plurality of light-emitting units distributed in an array. The driving backplane includes a signal line located in the peripheral area and surrounding the display area, and the signal line provides a negative power supply voltage to the plurality of light-emitting units. The display panel has a problem of high power consumption. Utility Model Content

[0004] The embodiments of the present disclosure provide a display panel and a display device, which can reduce the power consumption of the display panel. The technical solution is as follows:

[0005] On the one hand, a display panel is provided, which includes a display area and a peripheral area, wherein the peripheral area surrounds the display area, and the display panel includes a stacked driving backplane and a light-emitting functional layer; the driving backplane includes a base substrate and a driving circuit layer on a first surface of the base substrate, and the light-emitting functional layer includes a plurality of light-emitting units distributed in an array; the driving circuit layer includes a first conductive structure, the first conductive structure includes a plurality of first signal lines and a plurality of second signal lines, the plurality of first signal lines extend along a first direction, the plurality of second signal lines extend along a second direction, the first direction and the second direction intersect, the plurality of first signal lines are electrically connected to the plurality of second signal lines, the first conductive structure is at least located in the display area, and the first conductive structure is used to provide a negative power supply voltage to the plurality of light-emitting units.

[0006] Optionally, the light-emitting functional layer also includes a pixel definition layer, the pixel definition layer includes a plurality of openings distributed in an array, the plurality of light-emitting units correspond one-to-one to the plurality of openings, and at least part of the light-emitting units are located in the corresponding openings; the orthographic projection of each of the first signal lines on the first surface passes through the geometric center of the orthographic projection of at least one of the openings on the first surface, and different first signal lines pass through different openings.

[0007] Optionally, the plurality of first signal lines and the plurality of second signal lines are located in different layers, and the first signal lines and the second signal lines are electrically connected through vias; or, the plurality of first signal lines and the plurality of second signal lines are located in the same layer.

[0008] Optionally, the driving circuit layer also includes a second conductive structure and a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected one-to-one with the plurality of light-emitting units; the second conductive structure includes a plurality of third signal lines and a plurality of fourth signal lines, the plurality of third signal lines extend along a first direction, the plurality of fourth signal lines extend along a second direction, the plurality of third signal lines are electrically connected to the plurality of fourth signal lines, the second conductive structure is at least located in the display area, and the second conductive structure is used to provide a positive power supply voltage to the plurality of pixel driving circuits.

[0009] Optionally, the multiple openings include a plurality of first openings distributed in an array, and the plurality of first openings are divided into a plurality of first opening groups arranged along the second direction, each first opening group includes a plurality of first openings arranged at intervals along the first direction, and the orthographic projections of the plurality of first openings in each first opening group on the first surface partially overlap with the orthographic projections of a pair of third signal lines on the first surface; the orthographic projections of two third signal lines in a pair of third signal lines on the first surface are located on both sides of a first connecting line and are symmetrical about the first connecting line, and the first connecting line is a line connecting the geometric centers of the orthographic projections of the plurality of first openings in the first opening group on the first surface whose orthographic projections partially overlap with the orthographic projections of a pair of third signal lines on the first surface.

[0010] Optionally, a distance between an orthographic projection of the first opening on the first surface and an orthographic projection of the second signal line closest to the first opening on the first surface is greater than or equal to 3 μm.

[0011] Optionally, the second conductive structure also includes a plurality of connection parts, which are a plurality of connection part groups arranged along the second direction, each connection part group includes a plurality of connection parts arranged at intervals along the first direction, and the plurality of connection parts in each of the connection part groups are respectively connected to two third signal lines in a pair of the third signal lines; the orthographic projection of the first opening on the first surface is located within the orthographic projection of one of the connection parts and the pair of the third signal lines connected to the connection part on the first surface.

[0012] Optionally, the multiple openings also include a plurality of second openings distributed in an array, the plurality of second openings are divided into a plurality of second opening groups arranged along the second direction, each second opening group includes a plurality of second openings arranged at intervals along the first direction; the fourth signal line includes a main body and a plurality of extensions, the main body extends along the second direction, one end of the plurality of extensions is connected to the main body, and the plurality of extensions extend along the first direction; the plurality of extensions arranged along the second direction are a plurality of extension groups, each of the extension groups includes two adjacent extensions, the orthographic projection of the extension group on the first surface coincides with the orthographic projection of one of the second openings on the first surface, the orthographic projections of the two extensions in the extension group on the first surface are located on both sides of the geometric center of the orthographic projection of the corresponding second opening on the first surface in the second direction, and are symmetrical about the geometric center of the orthographic projection of the corresponding second opening on the first surface.

[0013] Optionally, the first signal line and the second signal line are in different layers, the third signal line and the first signal line are in the same layer, and the fourth signal line and the second signal line are in the same layer; or, the first signal line and the second signal line are in the same layer, the third signal line is located on a side of the first signal line close to the light-emitting unit, the multiple fourth signal lines include multiple first parts and multiple second parts, the multiple first parts and the multiple second parts have the same extension direction and are alternately arranged in the second direction y, the first part of each of the fourth signal lines is in the same layer as the first signal line, and the second part of each of the fourth signal lines is in the same layer as the third signal line.

[0014] Optionally, the driving circuit layer includes a plurality of data lines extending along a first direction; the orthographic projections of the plurality of second openings in each second opening group on the first surface partially overlap with the orthographic projections of a pair of the data lines on the first surface; the orthographic projections of two data lines in a pair of the data lines on the first surface are located on both sides of the geometric center of the orthographic projections of the second openings in the corresponding second opening group on the first surface in the second direction, and are symmetrical about the geometric center of the orthographic projections of the second openings in the corresponding second opening group on the first surface.

[0015] Optionally, the plurality of data lines are in the same layer as the third signal line.

[0016] Optionally, the light-emitting unit includes a first electrode, a light-emitting layer and a second electrode stacked in sequence on the driving backplane, a plurality of the second electrodes are connected into an integrated structure, the first conductive structure is electrically connected to the plurality of the second electrodes through at least one first via hole, and the at least one first via hole is located in the peripheral area.

[0017] Optionally, the plurality of light emitting units include a plurality of first light emitting units, a plurality of second light emitting units and a plurality of third light emitting units, and the colors of light emitted by the first light emitting units, the second light emitting units and the third light emitting units are different.

[0018] On the other hand, a display device is further provided. The display device includes a power supply circuit and any one of the above-mentioned display panels, wherein the power supply circuit supplies power to the display panel.

[0019] The beneficial effects brought about by the technical solution provided by the present disclosure include at least: by designing the signal line that provides a negative power supply voltage to multiple light-emitting units as a first conductive structure, the first conductive structure includes multiple electrically connected first signal lines and multiple second signal lines, thereby reducing resistance and reducing power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 It is a schematic diagram of a planar structure of a display panel in the related art;

[0022] Figure 2 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure;

[0023] Figure 3 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0024] Figure 4 is a schematic diagram of a planar structure of a light-emitting unit and a first conductive structure provided by an embodiment of the present disclosure;

[0025] Figure 5 is a schematic diagram of a cross-sectional structure of a driving circuit layer provided by an embodiment of the present disclosure;

[0026] Figure 6 is a schematic diagram of the distribution of multiple openings in a pixel definition layer provided by an embodiment of the present disclosure;

[0027] Figure 7 is a schematic diagram of a planar structure of a third source-drain layer and a schematic diagram of a planar structure of a second source-drain layer provided by an embodiment of the present disclosure;

[0028] Figure 8 is a schematic diagram of a planar structure of another display panel provided by an embodiment of the present disclosure;

[0029] Fig. 9 is a schematic diagram of a planar structure of a third source-drain layer and a schematic diagram of a planar structure of a second source-drain layer provided in an embodiment of the present disclosure;

[0030] Fig.10 It is a schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present disclosure.

[0031] Legend:

[0032] A, display area B, peripheral area x, first direction y, second direction

[0033] 10. Driving backplane 11, base substrate 11a, first surface 12, driving circuit layer

[0034] 121, first conductive structure 1211, first signal line 1212, second signal line

[0035] 122, second conductive structure 1221, third signal line 1222, fourth signal line

[0036] 12211, connecting portion 122110, connecting portion group 12221, main body 12222, extending portion 122220, extending portion group

[0037] 123, data line 1201, first source and drain electrode layer 1202, second source and drain electrode layer 1203, third source and drain electrode layer 1204, light shielding layer 1205, buffer layer 1206, first active layer 1207, first gate insulating layer 1208, first gate layer 1209, first insulating layer 1240, second gate layer 1241, second gate insulating layer 1242, second active layer 1243, third gate insulating layer 1244, third gate layer 1245, interlayer dielectric layer 1246, passivation layer 1247, first planarization layer 1248, second planarization layer

[0038] 20. Light-emitting functional layer 200. Light-emitting unit

[0039] 21, first electrode 22, light-emitting layer 23, second electrode

[0040] 24, pixel definition layer 240, opening 241, first opening 2410, first opening group 242, second opening 2420, second opening group 243, third opening

[0041] 30, FPC 40, packaging layer 51, first via hole 52, second via hole 53, third via hole 54, fourth via hole 55, fifth via hole 56, sixth via hole DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0043] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate quantitative restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. The directional terms mentioned in the present disclosure, such as "top", "bottom", "up", "down", "left" or "right", etc., are only referenced to the directions of the drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present disclosure, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure.

[0044] In the related art, the display panel includes a stacked driving backplane and a light-emitting functional layer, the driving backplane includes a base substrate and a driving circuit layer on a first surface of the base substrate, and the light-emitting functional layer includes a plurality of light-emitting units distributed in an array. Figure 1 FIG. 1 is a schematic diagram of a planar structure of a display panel in the related art. Figure 1 As shown, the display panel includes a display area A' and a peripheral area B', and the peripheral area B' surrounds the display area A'. The driving circuit layer includes a signal line 120' located in the peripheral area B' and surrounding the display area A', and the signal line 120' is used to provide a negative power supply voltage (also called a VSS signal) to multiple light-emitting units, for example, through an FPC (Flexible Printed Circuit Board) 30' to provide a negative power supply voltage to multiple light-emitting units. However, since the resistance of the signal line 120' is relatively large, that is, the resistance between the cathode of the light-emitting unit and the external structure (such as the control circuit board) is too large, the power consumption of the display panel is relatively large.

[0045] Figure 2 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure. Figure 2As shown, the display panel includes a stacked driving backplane 10 and a light-emitting functional layer 20 . The driving backplane 10 includes a base substrate 11 and a driving circuit layer 12 on a first surface 11 a of the base substrate 11 .

[0046] Figure 3 Schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure. Figure 3 As shown, the display panel includes a display area A and a peripheral area B, and the peripheral area B surrounds the display area A. The light-emitting functional layer 20 includes a plurality of light-emitting units 200 distributed in an array. The plurality of light-emitting units 200 are located in the display area A. The driving circuit layer 12 is used to control the plurality of light-emitting units 200 to emit light, thereby displaying a picture.

[0047] The driving circuit layer 12 includes a first conductive structure 121, the first conductive structure 121 includes a plurality of first signal lines 1211 and a plurality of second signal lines 1212, the plurality of first signal lines 1211 extend along a first direction x, the plurality of second signal lines 1212 extend along a second direction y, the first direction x and the second direction y intersect, forming a Figure 3 The mesh structure shown. The plurality of first signal lines 1211 and the plurality of second signal lines 1212 are electrically connected. The first conductive structure 121 is at least located in the display area A and is used to provide a negative power supply voltage to the plurality of light emitting units 200 .

[0048] By designing the signal line that provides a negative power supply voltage to the multiple light-emitting units 200 as a first conductive structure 121, the first conductive structure 121 includes multiple first signal lines 1211 and multiple second signal lines 1212 that are electrically connected, which is equivalent to increasing the cross-sectional area of ​​the signal line that provides the negative power supply voltage, or is equivalent to connecting multiple first signal lines and multiple second signal lines in parallel, so that the resistance of the first conductive structure 121 is smaller than that of the signal line in the related art, that is, the resistance between the light-emitting unit and the outside (such as a control circuit board) is reduced, preventing excessive energy loss such as heat energy on the signal line, thereby reducing the power consumption of the display panel.

[0049] For example, Figure 3 As shown, the display panel further includes an FPC 30, which is electrically connected to the first conductive structure 121, and is used for the outside (such as a control circuit board) to input a negative power supply voltage to the first conductive structure 121 through the FPC. Optionally, the first conductive structure is located in the display area A and the peripheral area B, and is electrically connected to the pad located in the peripheral area B, and the FPC is electrically connected to the pad located in the peripheral area B.

[0050] Alternatively, if Figure 3As shown, the first conductive structure 121 is electrically connected to the plurality of second electrodes 23 through at least one first via hole 51, and the at least one first via hole 51 is located in the peripheral area B. The plurality of light-emitting units 200 are electrically connected to the first conductive structure 121 through at least one first via hole 51, so that the first conductive structure 121 provides a negative power supply voltage to the plurality of light-emitting units. Figure 3 As shown, the first conductive structure 121 further includes a ring-shaped signal line, which is located in the peripheral area B and surrounds the display area A. The ring-shaped signal line is electrically connected to the plurality of first signal lines 1211 and the plurality of second signal lines 1212, and the ring-shaped signal line is connected to the first via 51. It should be noted that Figure 3 The position of the first via hole 51 in the figure is only an example, and the first via hole 51 can also be located at other positions of the peripheral area B, such as at Figure 3 In the illustrated embodiment, the first via hole 51 may also be located on the left side of the display area A and in the peripheral area B. Optionally, the ring-shaped signal line and the first signal line 1211 are located in the same layer or in different layers.

[0051] Exemplarily, the first direction x is perpendicular to the second direction y. In some examples, the first direction x is the row direction of the plurality of light emitting units 200, and the second direction y is the column direction of the plurality of light emitting units 200. In other examples, the first direction x is the column direction of the plurality of light emitting units 200, and the second direction y is the row direction of the plurality of light emitting units 200.

[0052] For example, Figure 2 As shown, the light emitting unit includes a first electrode 21, a light emitting layer 22 and a second electrode 23 sequentially stacked on the first surface 11a.

[0053] Optionally, the first electrode 21 is an anode, the second electrode 23 is a cathode, and the second electrode 23 is electrically connected to the first conductive structure 121. Optionally, multiple second electrodes 23 are connected as an integrated structure to simplify the manufacturing process. Optionally, multiple second electrodes 23 are connected as an integrated structure and the integrated structure is located in the display area A and the peripheral area B, and the orthographic projections of the multiple first vias 51 on the first surface 11a are located within the orthographic projection of the integrated structure on the first surface 11a.

[0054] Optionally, the plurality of light-emitting units 200 include a plurality of first light-emitting units, a plurality of second light-emitting units, and a plurality of third light-emitting units, and the colors of the light emitted by the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different, so as to realize a color display function. For example, the color of the light emitted by the first light-emitting unit is green (Green, G), the color of the light emitted by the second light-emitting unit is blue (Blue, B), and the color of the light emitted by the third light-emitting unit is red (Red, R). The embodiments of the present disclosure do not limit the colors of the light emitted by the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit.

[0055] Exemplarily, the second electrode 23 may be made of a transparent conductive material, such as ITO (Indium tin oxide).

[0056] Exemplarily, the light-emitting layer 22 may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), an electron blocking layer (EBL) and a light-emitting material layer. The color of the light emitted by the first light-emitting unit, the second light-emitting unit and the third light-emitting unit is determined by the light-emitting material layer.

[0057] Exemplarily, the first electrode layer 21 is made of a metal material such as magnesium-silver alloy; or made of a transparent conductive material such as ITO.

[0058] like Figure 2 As shown, the light-emitting functional layer also includes a pixel definition layer 24. The pixel definition layer 24 includes a plurality of openings 240 distributed in an array. The plurality of light-emitting units 200 correspond to the plurality of openings 240 one by one, and at least a portion of the light-emitting unit 200 is located in the corresponding opening 240. Here, at least a portion of the light-emitting unit 200 is located in the corresponding opening 240 means that a portion of the first electrode 21 of the light-emitting unit and the light-emitting layer 22 are located in the opening 240, another portion of the first electrode 21 is located outside the opening 240 and located on the side of the pixel definition layer 24 close to the base substrate 11, and the second electrode 23 is not located in the opening 240, so as to form an integrated structure of the entire surface. In other possible embodiments, the second electrodes 23 of the light-emitting unit 200 are all located in the opening 240, and the plurality of second electrodes 23 are electrically connected by, for example, strip-shaped connecting electrodes to form a mesh-like integrated structure.

[0059] Optionally, the orthographic projection of the opening 240 on the first surface 11 a is located within the orthographic projection of the first electrode 21 of the corresponding light emitting unit 200 on the first surface 11 a .

[0060] Optionally, the shape of the orthographic projection of the opening 240 on the first surface 11a may be a circle, or a shape approximately similar to a circle (such as an ellipse or other centrally symmetrical shapes), or a square, etc., which is not limited in the embodiment of the present disclosure.

[0061] Exemplarily, the material of the pixel definition layer 24 includes one or more of polyimide, polyphthalimide, polyphthalamide, silicon oxide, silicon nitride, and the like.

[0062] For example, Figure 2 As shown, the display panel further includes an encapsulation layer 40 for protecting the display panel. Optionally, the encapsulation layer 40 is made of silicon nitride, silicon oxide or silicon oxynitride.

[0063] Optionally, the display panel further includes a color filter layer, which is located on a side of the encapsulation layer away from the base substrate 11. The color filter layer includes a plurality of color resist blocks distributed in an array.

[0064] Optionally, the display panel further includes a touch layer, a touch insulating layer and a touch protection layer stacked in sequence on the first surface 11a, and the touch layer is located on the side of the color film layer away from the base substrate 11. Among them, the touch layer can be a self-capacitive touch structure or a mutual-capacitive touch structure, which is not limited in the present disclosure. Optionally, the touch layer is made of one or more metal materials such as copper and aluminum. The touch insulating layer can be made of silicon oxide or silicon nitride, silicon nitride oxide, etc. The touch protection layer is made of an organic material that can be heat-cured or light-cured, such as acrylates and epoxy resins. Optionally, the touch layer can also be located on the side of the color film layer close to the base substrate 11.

[0065] It should be noted that, for a display panel without a touch function, it is not necessary to provide the aforementioned touch layer, touch insulation layer and touch protection layer.

[0066] Figure 4 Schematic diagram of the planar structure of the light-emitting unit and the first conductive structure provided by the embodiment of the present disclosure. Figure 2 and Figure 4 The orthographic projection of each first signal line 1211 on the first surface 11a passes through the geometric center O1 of the orthographic projection of at least one opening 240 on the first surface 11a, and different first signal lines 1211 pass through different openings 240. The first signal line 1211 is set to pass through the geometric center O1 of the opening 240, so that the opening 240 is symmetrical about the first signal line 1211, and the light-emitting unit 200 located in the opening 240 and the part of the first electrode 21 in contact with the light-emitting layer 22 has good flatness and symmetry, thereby effectively improving color deviation and improving display effects.

[0067] In one embodiment, there is a first signal line 1211 under each opening 240 , and the orthographic projection of the first signal line 1211 on the first surface 11 a passes through the geometric center O1 of the orthographic projection of the opening 240 on the first surface 11 a .

[0068] In another embodiment, a portion of the openings 240 has a first signal line 1211 below them, for example Figure 4 As shown, the first direction x is the column direction of the plurality of openings 240, the second direction y is the row direction of the plurality of openings 240, there is a first signal line 1211 under one column of openings 240, and there is no first signal line 1211 under another column of openings 240, and the orthographic projection of the first signal line 1211 on the first surface 11a passes through the geometric center O1 of the orthographic projection of the openings 240 on the first surface 11a, and there is no first signal line 1211 under another part of the openings 240. Optionally, there is a column of openings or multiple columns of openings between two adjacent first signal lines 1211.

[0069] The following is an explanation of the relationship between flat symmetry and color shift improvement. Figure 2 , assuming that the line connecting the first position C and the center of the display panel is perpendicular to the display panel, and taking the line as the reference line, the line connecting the second position D and the center of the display panel is at a first angle to the reference line, the line connecting the third position E and the center of the display panel is at a second angle to the reference line, and the first position C, the second position D and the third position E are on a straight line and the straight line is parallel to the display panel. If the portion of the first electrode 21 located in the opening 240 and in contact with the light-emitting layer 22 is symmetrically flat about the geometric center O1 of the opening, then the color seen by the human eye when viewing the display panel at the second position D and at the third position E is the same; if the portion of the first electrode 21 located in the opening 240 and in contact with the light-emitting layer 22 is asymmetrically flat about the geometric center O1 of the opening, then the color seen by the human eye when viewing the display panel at the second position D and at the third position E is different, that is, there is color deviation. Therefore, if the portion located in the opening 240 has good flatness and symmetry, the color deviation can be effectively improved, so that the color seen by the human eye when viewing the display panel at the second position and at the third position is the same, thereby improving the display effect.

[0070] In a possible implementation manner, the plurality of first signal lines and the plurality of second signal lines are located in different layers, and the first signal lines are electrically connected to the second signal lines through vias.

[0071] Exemplarily, the driving circuit layer 12 includes a first source-drain layer 1201, a second source-drain layer 1202, and a third source-drain layer 1203 stacked in sequence on the first surface 11a. A plurality of first signal lines 1211 are located in the third source-drain layer 1203, a plurality of second signal lines 1212 are located in the second source-drain layer 1202, and the first signal lines 1211 and the second signal lines 1212 are electrically connected through vias. A mesh-like first conductive structure 121 is formed by respectively arranging a plurality of first signal lines 1211 and a plurality of second signal lines 1212 in the third source-drain layer 1203 and the second source-drain layer 1202. In other possible embodiments, the first signal line 1211 may be located in the second source-drain layer 1202, and the second signal line 1212 may be located in the third source-drain layer 1203.

[0072] Figure 5 Schematic diagram of a cross-sectional structure of a driving circuit layer provided by an embodiment of the present disclosure. Figure 5 As shown, the driving circuit layer 12 includes a light shielding layer 1204, a buffer layer 1205, a first active layer 1206, a first gate insulating layer 1207, a first gate layer 1208, a first insulating layer 1209, a second gate layer 1240, a second gate insulating layer 1241, a second active layer 1242, a third gate insulating layer 1243, a third gate layer 1244, an interlayer dielectric layer 1245, a first source and drain layer 1201, a passivation layer 1246, a second source and drain layer 1202, a first planarization layer 1247, a third source and drain layer 1203 and a second planarization layer 1248 stacked in sequence on the first surface 11a of the base substrate 11.

[0073] Optionally, the first source and drain layer, the second source and drain layer 1202 and the third and fourth source and drain layer 1203 are single-layer metal layers, made of, for example, molybdenum or aluminum; or, are formed by stacking multiple metal layers, for example, including stacked molybdenum layers, aluminum layers and molybdenum layers, or stacked titanium layers, aluminum layers and titanium layers, etc.

[0074] Exemplarily, the base substrate 11 can be any transparent substrate, such as a glass substrate, a quartz substrate, a plastic substrate, other transparent hard substrates or other transparent flexible substrates, which can be a single layer or a multilayer structure. Taking the multilayer structure as an example, the base substrate 11 includes a first PI (polyimide) layer, a first protective layer, a second PI (polyimide) layer, and a second protective layer stacked from bottom to top. The two protective layers are used to protect the PI layer to prevent subsequent processes from damaging the PI layer. The second protective layer is also covered with a buffer layer, which can block water oxygen and block alkaline ions.

[0075] Exemplarily, the light shielding layer 1204 can be made of metal materials, including but not limited to molybdenum, aluminum, titanium, copper and other materials. The light shielding layer 1204 can reduce the light exposure to the TFT and can also conduct electricity. The light shielding layer 1204 can also be called a BSM (bottom shield metal) layer.

[0076] Exemplarily, the first active layer 1206 is made of low temperature polycrystalline silicon material, and the second active layer 1242 is made of metal oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide). The driving backplane including the first active layer 1206 and the second active layer 1242 is also called LTPO (Low Temperature Polycrystalline Oxide) driving backplane.

[0077] Exemplarily, the materials of the first gate insulating layer 1207, the first insulating layer 1209, the second gate insulating layer 1241, the third gate insulating layer 1243, the interlayer dielectric layer 1245, the second insulating layer and the passivation layer 1246 may be silicon oxide or silicon nitride, silicon oxynitride, etc.

[0078] Exemplarily, the first gate layer 1208 , the second gate layer 1240 , and the third gate layer 1244 are made of metal materials, such as one or more of molybdenum, copper, and aluminum.

[0079] Exemplarily, the first planarization layer 1247 and the second planarization layer 1248 are made of an organic insulating material, such as resin.

[0080] In other possible embodiments, the driving backplane may not be an LTPO driving backplane, but an LTPS (Low Temperature Poly-Silicon) driving backplane. For the LTPS backplane, the driving circuit layer may include a buffer layer 1205, a first gate layer 1208, a first gate insulating layer 1207, a first active layer 1206, a second gate insulating layer 1241, a second gate layer 1240, an interlayer dielectric layer 1245, a first source and drain layer 1201, a passivation layer 1246, a second source and drain layer 1202 and a first planarization layer 1248 stacked sequentially on the first surface 11a. Among them, the first active layer 1206 is made of low temperature polysilicon material.

[0081] Optionally, when the driving backplane is an LTPS driving backplane, the first signal line 1211 is located in the second source-drain layer 1202 , and the second signal line 1212 is located in the first source-drain layer 1201 ; or, the first signal line 1211 is located in the first source-drain layer 1201 , and the second signal line 1212 is located in the second source-drain layer 1202 .

[0082] Exemplarily, the driving circuit layer 12 further includes a plurality of pixel driving circuits, which are connected to the plurality of light-emitting units 200 in a one-to-one correspondence, and each pixel driving circuit includes at least two TFTs (Thin Film Transistors). According to the number of TFTs and capacitors included in each pixel driving circuit, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Each pixel driving circuit is used to control the light-emitting unit 200 connected thereto to emit light.

[0083] Optionally, the driving circuit layer 12 further includes a second conductive structure 122. The second conductive structure 122 includes a plurality of third signal lines 1221 and a plurality of fourth signal lines 1222, the plurality of third signal lines 1221 extend along the first direction x, the plurality of fourth signal lines 1222 extend along the second direction y, the plurality of third signal lines 1221 and the plurality of fourth signal lines 1222 are electrically connected, the second conductive structure 122 is at least located in the display area A and the second conductive structure 122 is used to provide a positive power supply voltage (also referred to as a VDD signal) to a plurality of pixel driving circuits, and the second conductive structure 122 is the above-mentioned power supply line. Since the second conductive structure 122 is in a mesh shape and can be distributed relatively evenly in the display area A, the difference in the signal of the positive power supply voltage received by different pixel driving circuits can be small, which is conducive to improving display uniformity.

[0084] Figure 6 FIG. 1 is a schematic diagram of the distribution of multiple openings in a pixel definition layer provided by an embodiment of the present disclosure. Figure 6 As shown, the plurality of openings 240 include a first opening 241, a second opening 242 and a third opening 243. The first light-emitting unit is at least partially located in the first opening 241, the second light-emitting unit is at least partially located in the second opening 242, and the third light-emitting unit is at least partially located in the third opening 243. The light-emitting units located in the first opening 241, the second opening 242 and the third opening 243 are respectively the first light-emitting unit, the second light-emitting unit and the third light-emitting unit. Optionally, the colors of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are respectively green (G), blue (B) and red (R). In order to more clearly show the distribution of the first opening 241, the second opening 242 and the third opening 243, the first opening 241 where the first light-emitting unit is located, the second opening 242 where the second light-emitting unit is located and the third opening 243 where the third light-emitting unit is located are respectively in Figure 6 It is represented by R, G, and B.

[0085] Alternatively, if Figure 6 As shown, one pixel includes two first light-emitting units, one second light-emitting unit and one third light-emitting unit, that is, one pixel corresponds to one opening group p, and one opening group p includes two first openings 241, one second opening 242 and one third opening 243. The distribution of multiple opening groups p is shown in FIG. Figure 6 As shown. A plurality of opening groups p are arranged in an array, with the row direction being the second direction y and the column direction being the first direction x. For two adjacent rows of opening groups p, the second row of opening groups p can be obtained by first translating the first row of opening groups p along the first direction x and then translating along the second direction y. In each opening group p, the line connecting the geometric centers of the four openings 240 is in a rhombus shape, with two first openings 241 distributed along the first direction x, and one second opening 242 and one first opening 241 distributed along the second direction y.

[0086] In other possible embodiments, an opening group p may also include a first opening 241, a second opening 242 and a third opening 243 arranged along a direction, that is, a pixel may also include a first light-emitting unit, a second light-emitting unit and a third light-emitting unit arranged along a direction. The embodiments of the present disclosure do not limit the type and number of light-emitting units included in the pixel.

[0087] For example, Figure 6 As shown, among the plurality of openings 240, a plurality of first openings 241 are arranged in an array, and the plurality of first openings 241 are divided into a plurality of first opening groups 2410 arranged along the second direction y, and each first opening group 2410 includes a plurality of first openings 241 arranged at intervals along the first direction x. Figure 4 and Figure 6, the orthographic projections of the plurality of first openings 241 in each first opening group 2410 on the first surface 11a partially overlap with the orthographic projections of a pair of third signal lines 1221 on the first surface 11a. The orthographic projections of two third signal lines 1221 in the pair of third signal lines 1221 on the first surface 11a are symmetrical about the first connecting line L, and the first connecting line L is the line connecting the geometric centers O1 of the orthographic projections of the plurality of first openings 241 in the first opening group 2410 on the first surface 11a where the orthographic projections on the first surface 11a partially overlap with the orthographic projections of the pair of third signal lines 1221 on the first surface 11a. That is, there is a first opening group 2410, the line connecting the geometric centers O1 of the orthographic projections of the plurality of first openings 241 in the first opening group 2410 on the first surface 11a is L, and there is a pair of third signal lines 1221 above the first opening group 2410, and the orthographic projections of the pair of third signal lines 1221 on the first surface 11a are symmetrical about the connecting line L. This design facilitates improving the flatness and symmetry of the portion of the first electrode 21 in the first light-emitting unit located above the third signal line 1221 and in contact with the light-emitting layer 22 , thereby effectively improving color deviation and improving display effects.

[0088] For example, see again Figure 4 , the distance a between the orthographic projection of the first opening 241 on the first surface 11a and the orthographic projection of the second signal line 1212 closest to the first opening 241 on the first surface 11a is greater than or equal to 3 μm. Since the size of the first electrode 21 is larger than the size of the first opening 241, that is, the orthographic projection of the first opening 241 on the first surface 11a is located within the orthographic projection of the first electrode 21 on the first surface 11a, Figure 4 As shown, if the distance a between the first opening 241 and the second signal line 1212 is too small, the first electrode 21 ( Figure 4 The portion near the second signal line 1212 (not shown) is less flat. Even if the first signal line 1211 is located outside the first opening 241, this unevenness will affect the portion of the first electrode 21 located within the first opening 241, thereby affecting the flatness and symmetry of the portion of the first electrode 21 located within the first opening 241, which is not conducive to improving the color deviation and affects the display effect.

[0089] Exemplarily, the insulating layer between the third source-drain electrode layer 1203 and the anode layer has a third via hole 53, and the insulating layer between the second source-drain electrode layer 1202 and the third source-drain electrode layer 1203 has a fourth via hole 54. Figure 4 , Figure 4exemplarily shows the projection relationship between a first electrode 21 and an opening 240, as well as the projection relationship between a third via 53 and a fourth via 54 and the first electrode 21, and the first electrode 21 shown is located above a third opening 243. Optionally, the first electrode 21 has a strip-shaped connecting portion, and the connecting portion is used to connect to a TFT in a pixel driving circuit. The connecting portion can first be connected to a pattern in a third source-drain electrode layer through a third via 53, and then connected to a pattern in a second source-drain electrode layer through a fourth via 54, and the connection with the TFT in the pixel driving circuit is achieved through the transfer of the pattern in the third source-drain electrode layer and the pattern in the second source-drain electrode layer. Therefore, the third signal line 1221 needs to be set to a zigzag line type instead of a straight line type to avoid the third via 53 and the fourth via 54.

[0090] For example, Figure 6 As shown, the plurality of second openings 242 are divided into a plurality of second opening groups 2420 arranged along the second direction y, and each second opening group 2420 includes a plurality of second openings 242 arranged at intervals along the first direction x.

[0091] Figure 7 Schematic diagram of the planar structure of a third source and drain layer and a schematic diagram of the planar structure of a second source and drain layer provided by an embodiment of the present disclosure. Figure 7 As shown in part (b), the fourth signal line 1222 includes a main body 12221 and a plurality of protruding portions 12222, the main body 12221 extends along the second direction y, one end of the plurality of protruding portions 12222 is connected to the main body 12221, and the plurality of protruding portions 12222 extend along the first direction x. The plurality of protruding portions 12222 arranged along the second direction y are divided into a plurality of protruding portion groups 122220, each protruding portion group 122220 includes two adjacent protruding portions 12222, the orthographic projection of the protruding portion group 122220 on the first surface 11a partially overlaps with the orthographic projection of a second opening 242 on the first surface 11a, and the orthographic projections of the two protruding portions 12222 in the protruding portion group 122220 on the first surface 11a are located on both sides of the geometric center O1 of the orthographic projection of the corresponding second opening 242 on the first surface 11a in the second direction y, and are symmetrical about the geometric center O1 of the orthographic projection of the corresponding second opening 242 on the first surface 11a.

[0092] Here, the extension 12222 has the function of electrically connecting other structures in the display panel. In the related art, the extension 12222 is relatively short. For example, the orthographic projection of the extension 12222 on the first surface 11a is located in the upper half of the orthographic projection of the second opening 242 on the first surface 11a, which is not conducive to the symmetry and flatness of the first electrode 21 of the light-emitting unit located in the second opening 242, resulting in a color shift problem in the display panel. However, the embodiment of the present disclosure improves the symmetry and flatness of the first electrode 21 of the light-emitting unit located in the second opening 242 by extending the length of the extension 12222, thereby improving the color shift problem and enhancing the display effect.

[0093] Exemplarily, the insulating layer between the second source-drain electrode layer 1202 and the third source-drain electrode layer 1203 has a fifth via hole 55, and the insulating layer between the first source-drain electrode layer 1201 and the second source-drain electrode layer 1202 has a sixth via hole 56. Figure 4 , Figure 4 In the example, a third via hole 53 and a fourth via hole 54 are shown in FIG. Figure 4 The third signal line 1221 can be electrically connected to the extension portion 12222 through the fifth via 55, and the extension portion 12222 is electrically connected to the pattern in the first source-drain electrode layer 1201 through the sixth via 56. The pattern in the first source-drain electrode layer 1201 is electrically connected to the source electrode of a thin film transistor in the pixel driving circuit, thereby realizing the introduction of the positive power supply voltage on the third signal line 1221 into the pixel driving circuit.

[0094] Exemplarily, the first signal line 1211 and the second signal line 1212 are in different layers, such as Figure 4 and Figure 7 As shown in part (a) of FIG. 1 , the third signal line 1221 is in the same layer as the first signal line 1211. Figure 4 and Figure 7 As shown in part (b), the fourth signal line 1222 is in the same layer as the second signal line 1212. Since the third signal line 1221 and the first signal line 1211 extend in the same direction, and the fourth signal line 1222 and the second signal line 1212 extend in the same direction, the first signal line 1211 and the third signal line 1221 can be made in the same layer, and the second signal line 1212 and the fourth signal line 1222 can be made in the same layer, saving process.

[0095] The following is an exemplary description of the structure of the data line. Figure 4, the driving circuit layer 12 includes a plurality of data lines 123 extending along the first direction x. The orthographic projections of the plurality of second openings 242 in each second opening group 2420 on the first surface 11a partially overlap with the orthographic projections of a pair of data lines 123 on the first surface 11a. The orthographic projections of two data lines 123 in a pair of data lines 123 on the first surface 11a are located on both sides of the geometric center O1 of the orthographic projection of the second openings 242 in the corresponding second opening group 2420 on the first surface 11a in the second direction y, and are symmetrical about the geometric center O1 of the orthographic projection of the second openings 242 in the corresponding second opening group 2420 on the first surface 11a, thereby improving the symmetry and flatness of the first electrode 21 of the light-emitting unit located in the second opening 242, improving the color deviation problem, and enhancing the display effect.

[0096] Exemplarily, the plurality of data lines 123 are in the same layer as the third signal line 1221. Since the data lines 123 and the third signal lines 1221 extend in the same direction, they can be manufactured in the same layer, saving process. Exemplarily, the data lines 123, the third signal lines 1221 and the first signal lines 1211 are all located in the third source and drain layer.

[0097] Figure 8 is a schematic diagram of a planar structure of another display panel provided by an embodiment of the present disclosure. Figure 4 Compared with the embodiment shown, Figure 8 As shown, Figure 8 In the illustrated embodiment, the first conductive structure 121 has a plurality of first signal lines 1211 and a plurality of second signal lines 1212 located in the same layer. Since the first signal lines and the second signal lines transmit the same electrical signal, they can be arranged in the same layer to save process. Exemplarily, the plurality of first signal lines 1211 and the plurality of second signal lines 1212 are both located in the aforementioned second source-drain layer 1202.

[0098] For example, Figure 8 The embodiment shown also includes a plurality of data lines 123, and the extension direction of the data lines 123 is the first direction x. Since the extension direction of the data lines 123 intersects with the extension direction of the second signal lines 1212, the data lines 123 and the second signal lines 1212 are fabricated in different layers. Optionally, the data lines 123 are located in the aforementioned third source-drain electrode layer 1203.

[0099] For example, Figure 8In the second conductive structure 122 shown, the third signal line 1221 and the data line 123 have the same extension direction, so the third signal line 1221 can be made in the same layer as the data line 123, for example, both are located in the aforementioned third source and drain electrode layer 1203. At the same time, since the fourth signal line 1222 and the third signal line 1221 transmit the same electrical signal, but need to avoid the data line 123 at the same time, a part of the fourth signal line 1222 can be set in the aforementioned third source and drain electrode layer 1203, that is, a different layer from the first signal line 1211, and another part of the fourth signal line 1222 is set in the aforementioned second source and drain electrode layer, that is, the same layer as the first signal line 1211.

[0100] Fig. 9 Schematic diagram of the planar structure of a third source and drain layer and a schematic diagram of the planar structure of a second source and drain layer provided by an embodiment of the present disclosure. Fig. 9 As shown in parts (a) and (b), each fourth signal line 1222 includes a plurality of first parts 1222a and a plurality of second parts 1222b, and the plurality of first parts 1222a and the plurality of second parts 1222b have the same extension direction and are alternately arranged in the second direction y, and are used to transmit electrical signals of a positive power supply voltage in the second direction y, but the first parts 1222a and the second parts 1222b are located in different layers.

[0101] like Fig. 9 As shown in part (b) of FIG. 1 , the first signal line 1211 and the second signal line 1212 are in the same layer, and in the fourth signal line 1222, the first portion 1222a is in the same layer as the first signal line 1211. The third signal line 1221 and the first signal line 1211 are in different layers, as shown in FIG. Fig. 9 As shown in part (a) of FIG. 1 , the third signal line 1221 is located on a side of the first signal line 1211 close to the light emitting unit 20 .

[0102] like Fig. 9 As shown in part (a) of FIG. 1 , the second portion 1222b of each fourth signal line 1222 is in the same layer as the third signal line 1221. Fig. 9 As shown in part (b) of FIG. 1 , the first portion 1222a of each fourth signal line is on the same layer as the first signal line.

[0103] The first conductive structure 121 is arranged on the same layer, a part of the second conductive structure 122 is arranged on the same layer as the first conductive structure 121, and another part of the second conductive structure 122 is arranged on another layer, so as to form a mesh-shaped first conductive structure 121 and a mesh-shaped second conductive structure 122. In the second conductive structure 122, a part 1222a of the fourth signal line 1222 is connected to a second part 1222b of the fourth signal line 1222 through a second via 52. The orthographic projection of the second via 52 on the first surface 11a is located in the overlapped part of the orthographic projection of the first part 1222a on the first surface 11a and the orthographic projection of the second part 1222b on the first surface 11a.

[0104] For example, Figure 8 and Fig. 9 As shown, the second conductive structure 122 also includes a plurality of connection parts 12211, and the plurality of connection parts 12211 are divided into a plurality of connection part groups 122110 arranged along the second direction, and each connection part group 122110 includes a plurality of connection parts 12211 arranged at intervals along the first direction x, and the plurality of connection parts 12211 in each connection part group 122110 are respectively connected to two third signal lines 1221 in a pair of third signal lines 1221. The orthographic projection of the first opening 241 on the first surface 11a is located within the orthographic projection of a connection part 12211 and a pair of third signal lines 1221 connected to the connection part 12211 on the first surface 11a. The connection part 12211 is provided to further improve the symmetry and flatness of the first electrode 21 of the light-emitting unit located in the second opening 242, improve the color deviation problem, and enhance the display effect.

[0105] Optionally, the plurality of connection parts 12211 correspond to the plurality of first openings 241 one by one, that is, each first opening 241 has a connection part 12211 below. Alternatively, a portion of the first openings 241 has a connection part 12221 below, and another portion of the first openings 241 has no connection part 12221 below.

[0106] Fig.10 FIG. 1 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.10 As shown, the method includes:

[0107] In step S1 , a driving backplane is provided, wherein the driving backplane includes a base substrate and a driving circuit layer on a first surface of the base substrate.

[0108] In step S2, a light-emitting functional layer is manufactured on the driving backplane, and the light-emitting functional layer includes a plurality of light-emitting units distributed in an array.

[0109] Among them, the display panel includes a display area and a peripheral area, the peripheral area surrounds the display area, the driving circuit layer includes a first conductive structure, the first conductive structure includes multiple first signal lines and multiple second signal lines, the multiple first signal lines extend along a first direction, the multiple second signal lines extend along a second direction, the first direction and the second direction intersect, the multiple first signal lines and the multiple second signal lines are electrically connected, the first conductive structure is at least located in the display area and the first conductive structure is used to provide a negative power supply voltage to multiple light-emitting units.

[0110] Below Figure 4 Taking the structure shown as an example, step S2 is exemplarily described. Exemplarily, step S2 may include:

[0111] The first step is to deposit a light-shielding metal layer on the substrate, and then obtain a photoresist structure through processes such as photoresist coating, exposure, and development, and then etch the light-shielding metal layer using the photoresist structure as a mask to obtain a light-shielding layer.

[0112] The second step is to form a buffer layer on the light-shielding pattern layer, for example, by deposition. Then, a first active layer is formed on the buffer layer. For example, an initial first active layer may be deposited on the buffer layer, and the initial first active layer may be patterned to obtain the first active layer.

[0113] Step 3: Form an initial first gate insulating layer and an initial first gate layer on the first active layer in sequence by, for example, deposition. The initial first gate insulating layer covers the first active layer. The initial first gate layer is patterned to obtain a first gate layer.

[0114] Step 4: forming an initial first insulating layer and an initial second gate layer on the first gate layer in sequence by, for example, deposition, and patterning the initial second gate layer to obtain the second gate layer.

[0115] Step 5: forming an initial second gate insulating layer and an initial second active layer on the second gate layer in sequence by, for example, deposition, and patterning the initial second active layer to obtain a second active layer.

[0116] Step 6: Form an initial third gate insulating layer and an initial third gate layer on the second active layer in sequence by, for example, deposition. The initial third gate insulating layer covers the second active layer. The initial third gate layer is patterned to obtain a third gate layer.

[0117] Step 7: Form an initial interlayer dielectric layer on the third gate layer by, for example, deposition. Through a series of processes such as photoresist coating, exposure, etching, and stripping, multiple vias are formed to expose the light shielding layer, and the first gate insulating layer is obtained from the initial first gate insulating layer; and then through a series of processes such as photoresist coating, exposure, etching, and stripping, multiple vias are formed to expose the first active layer, and the first insulating layer is obtained from the initial first insulating layer, and the second gate insulating layer is obtained from the initial second gate insulating layer. At the same time, an interlayer dielectric layer is obtained.

[0118] Step 8: In the via holes of the exposed light shielding layer and the first active layer obtained by etching in the step 7, a first source and drain layer is formed by a series of processes such as deposition, photoresist coating, exposure, etching, and stripping.

[0119] Step 9: Form an initial passivation layer on the first source-drain electrode layer by, for example, deposition, and form a second source-drain electrode layer on the initial passivation layer by, for example, deposition, photoresist coating, exposure, etching, stripping, and a series of processes, wherein the second source-drain electrode layer includes a plurality of second signal lines and a plurality of fourth signal lines. Form an initial first planarization layer on the second source-drain electrode layer by, for example, deposition. Form a plurality of vias exposing the second active layer by a series of processes, such as photoresist coating, exposure, etching, stripping, and a series of processes, and simultaneously obtain a third gate insulating layer from the initial third gate insulating layer, and obtain a passivation layer from the initial passivation layer.

[0120] Step 10. In the via hole that exposes the second active layer obtained by etching in the ninth step, a third source-drain layer is formed by a series of processes such as deposition, photoresist coating, exposure, etching, and stripping, wherein the third source-drain layer includes a plurality of first signal lines and a plurality of third signal lines.

[0121] Step 11: Form a second planarization layer on the third source and drain electrode layer by, for example, deposition.

[0122] The materials of each layer refer to the above embodiments and will not be described in detail here.

[0123] Optionally, the patterning process includes processes such as photoresist coating, exposure, development, etching, and stripping.

[0124] An embodiment of the present disclosure further provides a display device, comprising a power supply circuit and any one of the aforementioned display panels, wherein the power supply circuit supplies power to the display panel.

[0125] Exemplarily, the display device further includes a control circuit board, and the control circuit board inputs a negative power supply voltage and a positive power supply voltage to the first conductive structure and the second conductive structure respectively through the FPC in the display panel.

[0126] Illustratively, the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0127] The display device has the same effect as the above-mentioned display panel, which will not be described in detail here.

[0128] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a peripheral area, wherein the peripheral area surrounds the display area, and the display panel comprises a stacked driving backplane (10) and a light-emitting functional layer (20); The driving backplane (10) comprises a base substrate (11) and a driving circuit layer (12) on a first surface (11a) of the base substrate (11); the light-emitting functional layer (20) comprises a plurality of light-emitting units (200) distributed in an array; The driving circuit layer (12) comprises a first conductive structure (121), the first conductive structure (121) comprising a plurality of first signal lines (1211) and a plurality of second signal lines (1212), the plurality of first signal lines (1211) extending along a first direction, the plurality of second signal lines (1212) extending along a second direction, the first direction and the second direction intersecting, the plurality of first signal lines (1211) and the plurality of second signal lines (1212) being electrically connected, the first conductive structure (121) being at least located in the display area and the first conductive structure (121) being used to provide a negative power supply voltage to the plurality of light-emitting units (200).

2. The display panel according to claim 1, characterized in that: The light-emitting functional layer (20) further comprises a pixel definition layer (24), the pixel definition layer (24) comprising a plurality of openings (240) distributed in an array, the plurality of light-emitting units (200) corresponding to the plurality of openings (240) one by one, and at least a portion of the light-emitting unit (200) is located in the corresponding opening (240); The orthographic projection of each first signal line (1211) on the first surface (11a) passes through the geometric center of the orthographic projection of at least one opening (240) on the first surface (11a), and different first signal lines (1211) pass through different openings (240).

3. The display panel according to claim 2, characterized in that: The plurality of first signal lines (1211) and the plurality of second signal lines (1212) are located in different layers, and the first signal lines (1211) and the second signal lines (1212) are electrically connected through vias; or, The plurality of first signal lines (1211) and the plurality of second signal lines (1212) are located in the same layer.

4. The display panel according to claim 3, characterized in that: The driving circuit layer (12) further comprises a second conductive structure (122) and a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are connected to the plurality of light-emitting units (200) in a one-to-one correspondence; The second conductive structure (122) comprises a plurality of third signal lines (1221) and a plurality of fourth signal lines (1222), the plurality of third signal lines (1221) extending along a first direction, the plurality of fourth signal lines (1222) extending along a second direction, the plurality of third signal lines (1221) and the plurality of fourth signal lines (1222) being electrically connected, the second conductive structure (122) being at least located in the display area and the second conductive structure (122) being used to provide a positive power supply voltage to the plurality of pixel driving circuits.

5. The display panel according to claim 4, characterized in that: The plurality of openings (240) include a plurality of first openings (241) distributed in an array, the plurality of first openings (241) are divided into a plurality of first opening groups (2410) arranged along the second direction, each first opening group (2410) includes a plurality of first openings (241) arranged at intervals along the first direction, and the orthographic projections of the plurality of first openings (241) in each first opening group (2410) on the first surface (11a) partially overlap with the orthographic projections of a pair of the third signal lines (1221) on the first surface (11a); The orthographic projections of two third signal lines (1221) in a pair of the third signal lines (1221) on the first surface (11a) are located on both sides of a first connecting line and are symmetrical about the first connecting line, and the first connecting line is a line connecting the geometric centers of the orthographic projections of a plurality of first openings (241) in the first opening group (2410) on the first surface (11a) where the orthographic projections on the first surface (11a) partially overlap with the orthographic projections of the pair of the third signal lines (1221) on the first surface (11a).

6. The display panel according to claim 5, characterized in that: The distance between the orthographic projection of the first opening (241) on the first surface (11a) and the orthographic projection of the second signal line (1212) closest to the first opening (241) on the first surface (11a) is greater than or equal to 3 μm.

7. The display panel according to claim 5, characterized in that: The second conductive structure (122) further comprises a plurality of connection portion groups (12211), wherein the plurality of connection portion groups (12211) are divided into a plurality of connection portion groups (122110) arranged along the second direction, each connection portion group (122110) comprises a plurality of connection portion groups (12211) arranged at intervals along the first direction, and the plurality of connection portion groups (12211) in each of the connection portion groups (122110) are respectively connected to two third signal lines (1221) in a pair of the third signal lines (1221); The orthographic projection of the first opening (241) on the first surface (11a) is located within the orthographic projection of one of the connection portion groups (12211) and a pair of the third signal lines (1221) connected to the connection portion group (12211) on the first surface (11a).

8. The display panel according to claim 7, characterized in that: The plurality of openings (240) further include a plurality of second openings (242) distributed in an array, the plurality of second openings (242) are divided into a plurality of second opening groups (2420) arranged along the second direction, and each second opening group (2420) includes a plurality of second openings (242) arranged at intervals along the first direction; The fourth signal line (1222) comprises a main body (12221) and a plurality of extensions (12222), the main body (12221) extending along the second direction, one end of the plurality of extensions (12222) being connected to the main body (12221), and the plurality of extensions (12222) extending along the first direction; A plurality of protrusions (12222) arranged along the second direction are divided into a plurality of protrusion groups (122220), each of the protrusion groups (122220) comprising two adjacent protrusions (12222), the orthographic projection of the protrusion group (122220) on the first surface (11a) partially overlapping with the orthographic projection of one of the second openings (242) on the first surface (11a), the orthographic projections of the two protrusions (12222) in the protrusion group (122220) on the first surface (11a) in the second direction being located on both sides of the geometric center of the orthographic projection of the corresponding second opening (242) on the first surface (11a), and being symmetrical with respect to the geometric center of the orthographic projection of the corresponding second opening (242) on the first surface (11a).

9. The display panel according to any one of claims 4 to 8, characterized in that: The first signal line (1211) and the second signal line (1212) are in different layers, the third signal line (1221) and the first signal line (1211) are in the same layer, and the fourth signal line (1222) and the second signal line (1212) are in the same layer; or, The first signal line (1211) and the second signal line (1212) are in the same layer, the third signal line (1221) is located on a side of the first signal line (1211) close to the light-emitting unit (200), the plurality of fourth signal lines (1222) include a plurality of first parts and a plurality of second parts, the plurality of first parts and the plurality of second parts have the same extension direction and are alternately arranged in a second direction y, the first part of each of the fourth signal lines (1222) is in the same layer as the first signal line (1211), and the second part of each of the fourth signal lines (1222) is in the same layer as the third signal line (1221).

10. The display panel according to claim 8, characterized in that: The driving circuit layer (12) comprises a plurality of data lines (123) extending along a first direction; The orthographic projections of the plurality of second openings (242) in each of the second opening groups (2420) on the first surface (11a) partially overlap with the orthographic projections of a pair of the data lines (123) on the first surface (11a); The orthographic projections of two data lines (123) in a pair of the data lines (123) on the first surface (11a) are located on both sides of the geometric center of the orthographic projection of the second opening (242) in the corresponding second opening group (2420) on the first surface (11a) in the second direction, and are symmetrical about the geometric center of the orthographic projection of the second opening (242) in the corresponding second opening group (2420) on the first surface (11a).

11. The display panel according to claim 10, characterized in that: The plurality of data lines (123) and the third signal line (1221) are in the same layer.

12. The display panel according to any one of claims 1 to 2, claims 4 to 8 and claims 10 to 11, characterized in that: The light-emitting unit (200) comprises a first electrode (21), a light-emitting layer (22) and a second electrode (23) which are sequentially stacked on the driving backplane (10); a plurality of the second electrodes (23) are connected to form an integrated structure; the first conductive structure (121) is electrically connected to the plurality of the second electrodes (23) via at least one first via hole (51); and the at least one first via hole (51) is located in the peripheral area.

13. The display panel according to any one of claims 1 to 2, claims 4 to 8 and claims 10 to 11, characterized in that: The plurality of light-emitting units (200) include a plurality of first light-emitting units, a plurality of second light-emitting units and a plurality of third light-emitting units, and the colors of light emitted by the first light-emitting units, the second light-emitting units and the third light-emitting units are different.

14. A display device, characterized in that: The display device comprises a power supply circuit and a display panel according to any one of claims 1 to 13, wherein the power supply circuit supplies power to the display panel.

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