Chip packaging structure

Abstract

A chip package structure includes a first semiconductor device, a second semiconductor device, a die bonding structure, a package bracket, and a stress balancing structure. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, and the die bonding structure is electrically connected between the first redistribution structure and the second redistribution structure. The package bracket covers the first semiconductor device and the second semiconductor device, and the stress balancing structure is disposed in the package bracket.

Description

Technical Field

[0001] The present disclosure relates to a chip packaging structure. Background Art

[0002] As the semiconductor industry introduces new generations of integrated circuits (ICs) with higher performance and greater functionality, the density of components forming the ICs increases while the size, dimensions, and spacing between components or elements decreases. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area.

[0003] The chip package structure of the system-on-integrated chip (SoIC) is usually composed of more than three dies. Since the chip package structure (e.g., chip size, die type, gap filling volume) has different cross-sections in the X and Y directions, it will cause different warpage in the X and Y directions, and thermal stress and stress accumulation will produce irregular shapes and cracking risks on the chip package structure. Utility Model Content

[0004] According to some embodiments of the present disclosure, a chip packaging structure is provided, which includes a first semiconductor device, a second semiconductor device, a die bonding structure, a packaging bracket and a stress balance structure. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, and the die bonding structure is electrically connected between the first redistribution structure and the second redistribution structure. The packaging bracket covers the first semiconductor device and the second semiconductor device, and the stress balance structure is disposed in the packaging bracket.

[0005] According to some embodiments of the present disclosure, a chip packaging structure is provided, which includes a first semiconductor device, a second semiconductor device, a bridge circuit, a first die bonding structure, a second die bonding structure, a packaging bracket and a stress balancing structure. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, the first die bonding structure is electrically connected between the bridge circuit and the first redistribution structure, and the second die bonding structure is electrically connected between the bridge circuit and the second redistribution structure. The packaging bracket covers the first semiconductor device and the second semiconductor device, and the stress balancing structure is disposed in the packaging bracket.

[0006] According to some embodiments of the present disclosure, a chip packaging structure is provided, comprising a first semiconductor device, a second semiconductor device, a packaging bracket and two stress balance structures. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. The packaging bracket covers the first semiconductor device and the second semiconductor device. One stress balance structure is configured in the packaging bracket, and another stress balance structure is disposed in at least one of the first semiconductor device and the second semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1A to 1C They are respectively a top view of a wafer-level chip packaging structure, a schematic cross-sectional view of the chip packaging structure along the XX axis, and a schematic cross-sectional view of the chip packaging structure along the YY axis;

[0009] FIG. 2A to FIG. 2B They are schematic diagrams of stress distribution of the chip packaging structure in different warping directions;

[0010] FIG. 3A to FIG. 3D are schematic diagrams of stress balancing structures of chip packaging structures according to embodiments of the present disclosure;

[0011] FIG. 4A to FIG. 4C are respectively a top view and a schematic cross-sectional view of a chip packaging structure and a stress balancing structure thereof according to an embodiment of the present disclosure;

[0012] FIG. 5A to FIG. 5B Schematic cross-sectional views of a chip packaging structure and a stress balancing structure according to two embodiments of the present disclosure;

[0013] FIG. 6A to FIG. 6B Schematic cross-sectional views of a chip packaging structure and a stress balancing structure according to two other embodiments of the present disclosure.

[0014]

Explanation of symbols

[0015] 100: Chip packaging structure / SoIC packaging structure

[0016] 101: Chip packaging structure

[0017] 102: Chip packaging structure

[0018] 103: Chip packaging structure

[0019] 104: Chip packaging structure

[0020] 105: Chip packaging structure

[0021] 110: Bracket base plate

[0022] 112: Bracket base plate

[0023] 113:Solder ball

[0024] 120: First semiconductor device

[0025] 120a: first redistribution structure

[0026] 121: first redistribution dielectric layer

[0027] 122: First redistribution wire interconnection

[0028] 123: first bonding pad

[0029] 124: first conductive bump

[0030] 125: Welding ball

[0031] 126: First bonding film

[0032] 127:TSV structure

[0033] 130: Second semiconductor device

[0034] 130a: Second redistribution structure

[0035] 131: Second redistribution dielectric layer

[0036] 132: Second redistribution wire interconnection

[0037] 133: Second bonding pad

[0038] 134: second conductive bump

[0039] 135: First die bonding structure

[0040] 136: Second bonding film

[0041] 137: Second die bonding structure

[0042] 140: Virtual Device

[0043] 140a: Bridge circuit

[0044] 141: third redistribution dielectric layer

[0045] 142: Third redistribution wire interconnection

[0046] 143: Third bonding pad

[0047] 144: third conductive bump

[0048] 145: fourth conductive bump

[0049] 146: Third bonding film

[0050] 150:Packaging bracket

[0051] 150': Packaging bracket

[0052] 151: Stress balance structure

[0053] 152: Groove

[0054] 152a: first groove

[0055] 152b: Second groove

[0056] 152c: third groove

[0057] 153: Stress Balance Material

[0058] 154~155: Stress balance structure

[0059] 156: Top cover layer / third stress balance structure

[0060] 157: Adhesive

[0061] 160: Epoxy molding material (EMC)

[0062] 161: first dielectric layer

[0063] 162: Second dielectric layer

[0064] D1: Distance

[0065] D2: edge to edge distance

[0066] H1: Groove depth

[0067] H2: Groove depth

[0068] H3: Groove depth

[0069] D3: Distance

[0070] D4: Distance

[0071] D5: Width

[0072] D6: Length

[0073] D7: Distance

[0074] D8:Thickness

[0075] BS: Back side

[0076] X,Y: axis DETAILED DESCRIPTION

[0077] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0078] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0079] Figures 1A to 1C The top view, the schematic cross-sectional view along the XX axis, and the schematic cross-sectional view along the YY axis of the wafer-level chip package structure are shown respectively. The chip package structure 100 in the present embodiment includes a carrier substrate 110, a first semiconductor device 120 and a second semiconductor device 130 stacked on the carrier substrate 110. The chip package structure 100 can be completed by fan-out wafer-level packaging (FOWLP) technology, and FOWLP is an improvement on wafer-level packaging (WLP) for providing more additional connections to semiconductor devices. The first semiconductor device 120 and the second semiconductor device 130 are sequentially disposed on a carrier substrate 110, and the first semiconductor device 120 and the second semiconductor device 130 are encapsulated by an epoxy molding material (EMC) 160, and then the first semiconductor device 120 and the second semiconductor device 130 are bonded via hybrid bonding or fusion bonding, and copper bumps are used as die bonding structures to form a system-on-integrated chip (SoIC) packaging structure 100.

[0080] In the integrated chip-on-chip system package structure 100, the first semiconductor device 120 and the second semiconductor device 130 and the epoxy resin molding material (EMC) 160 are made of different materials and in close contact, and the mismatch of thermal expansion coefficients will cause thermal stress to be generated in the adjacent materials. For example, during the heat treatment process, undesirable bending occurs due to different component configurations in the respective epitaxial directions of the chip package structure 100. Figure 1B and Figure 1C As shown in FIG. 1 , the component configuration along the XX axis and the component configuration along the YY axis have different structures, respectively, so that the warping along the XX axis and the warping along the YY axis are different, such as Figure 2A and Figure 2B In addition, thermal stress and stress accumulation will produce irregular shapes and cracking risks on the XX axis and YY axis of the chip package structure. In order to solve this problem, the present embodiment provides a technology for depositing a stress balancing material 153 in the package bracket 150. The stress balancing material 153 is used to balance the warpage of the chip package structure 100 on different axes and reduce the degree of warpage.

[0081] See also FIG. 3A to FIG. 3D , FIG. 3A to FIG. 3D Schematic diagrams of the stress balancing structure 151 of the chip package structure 101 according to embodiments of the present disclosure are shown respectively. The stress balancing structure 151 is embedded in the package bracket 150, and the stress balancing structure 151 includes a plurality of grooves 152 and a filling material (i.e., a stress balancing material 153, such as a conductive material, an insulating material, or a semiconductor material) filled in the grooves 152. The stress balancing material 153 may include aluminum, copper, tungsten, titanium, TaN, TiN, silicon dioxide, silicon carbide, silicon nitride, a combination of the above materials, or other suitable materials. The size and position of the stress balancing structure 151 depend on the warpage characteristics of the chip package structure 101. In various embodiments, the package bracket 150 may be made of a fiber material, a polymer material, a semiconductor material, a glass material, or any other suitable material. In some embodiments, the package bracket 150 is made of a semiconductor material such as silicon or germanium. In order to form the grooves 152, a patterned mask (not shown) is formed on the package bracket 150 using a patterning and etching process. The mask may be a photoresist mask or a hard mask. In some embodiments, the hard mask is made of silicon oxide (SiO 2 ), silicon carbide nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) or silicon nitride (SiN or Si 3 N 4), or other suitable materials. Using a patterned mask, the groove 152 can be etched in the package bracket 150. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, or other suitable processes or combinations thereof.

[0082] exist FIG. 3A to FIG. 3D In the embodiment of the present invention, the stress balancing structure 151 is selectively formed in the groove 152 to offset or reduce the warpage caused by thermal stress. For example, depending on the processing conditions, metals tend to have a higher thermal expansion coefficient than semiconductors such as silicon, germanium, etc. Dielectrics such as silicon oxide, silicon nitride, etc. have a lower thermal expansion coefficient than semiconductors. Therefore, at room temperature, dielectric films tend to be in compressive stress or have compressive strain. In contrast, thin metal films tend to be in tensile stress or have tensile strain. These properties can be used to deposit different materials in the groove 152 to affect the warpage of the chip packaging structure 100. For example, if the chip packaging structure 101 warps upward due to thermal stress, the stress balancing material 153 (such as metal) that causes the chip packaging structure 101 to bend downward can be selected to resist the warpage. Similarly, if the chip packaging structure 101 warps downward due to thermal stress, the stress balancing material 153 (such as dielectric) that causes the chip packaging structure 101 to bend upward can be selected to resist the warpage.

[0083] In some embodiments, the amount of warpage can be adjusted by the trench density and the stress-balancing material 153 formed in the trench 152. Figure 3A In the embodiment, the groove 152 in the package bracket 150 may be a long and narrow structure, wherein the long side is perpendicular to the warping direction (ie, the X-axis or Y-axis direction) or parallel to the warping direction (ie, the X-axis or Y-axis direction). Figure 3B In the embodiment, the grooves 152 in the package bracket 150 can be arranged in a matrix in a square pattern, a circular pattern, a triangular pattern, etc., wherein the density distribution of the grooves 152 in the X-axis direction can be different from the density distribution of the grooves 152 in the Y-axis direction. Figure 3C In the embodiment, the grooves 152 in the package bracket 150 may be in a square pattern, a circular pattern, or a triangular pattern with different density distributions. Figure 3C In the embodiment, the stress balancing structure 151 includes at least one first groove 152a and at least one second groove 152b (such as a square pattern or a circular pattern), and the size and area density of the first groove 152a are greater than the size or area density of the second groove 152b, so that the stress balancing characteristics at the area of ​​the first groove 152a are greater than the stress balancing characteristics at the area of ​​the second groove 152b.

[0084] exist Figure 3D , the stress balancing structure 151 includes at least one third groove 152c disposed at a corner of the package bracket 150. In this example, a plurality of third grooves 152c are formed at the corners of the package bracket 150 to resist stress at the corners of the chip package structure 101. For example, two sides of the third groove 152c intersect perpendicularly at 90 degrees and are arranged in parallel or at a certain angle (e.g., 45 degrees), wherein the two sides are adjacent to the corners of the package bracket 150.

[0085] In some embodiments, since the stress balance characteristics of the groove 152 include the groove width, the groove pitch, the groove length and the groove depth, we can select the appropriate groove width, groove pitch, groove length, groove depth and groove density according to the warpage characteristics of the chip package structure 101. For example, the width of the groove 152 is in the range of 1 μm and 20 μm, such as 12 μm. The pitch of the groove 152 is in the range of 1 μm and 120 μm, such as 80 μm. The length of the groove 152 is in the range of 1 μm and 2000 μm, such as 400 μm. In addition, according to some embodiments, the depth of the groove 152 is in the range of 1 μm and 250 μm, such as 70 μm. In addition, the total density of the groove 152 can be increased to increase the anti-warpage effect.

[0086] See also FIG. 4A to FIG. 4C , FIG. 4A to FIG. 4C The top view and schematic cross-sectional view are respectively of a chip package structure 101 and a stress balancing structure 151 thereof according to an embodiment of the present disclosure. In some embodiments, the distance D1 between two adjacent semiconductor devices is, for example, greater than 1 μm, the edge-to-edge distance D2 of two stacked semiconductor devices is, for example, greater than 0 μm, the distance D3 between the outermost edge of the first semiconductor device 120 and the edge of the stress balancing structure 151 is, for example, greater than 1 μm, the distance D4 between two adjacent stress balancing structures 151 is, for example, greater than 0.1 μm, the width D5 of the stress balancing structure 151 is, for example, greater than 1 μm, and the length D6 of the stress balancing structure 151 is, for example, greater than 1 μm. The length direction of the stress balancing structure 151 is, for example, perpendicular to the length direction of the second semiconductor device 130. In addition, in Figure 4C In the embodiment, for example, the distance D7 between the bottom of the stress balancing structure 151 and the top surface of the second semiconductor device 130 is greater than 1 μm. In some embodiments, the length D6 of the groove 152 is less than the edge length of the first semiconductor device 120, such as 10% to 70%. In some examples, the length D6 of the groove 152 is 25% to 50% of the edge length of the chip packaging area, and it is ideal not to exceed the boundary of the chip packaging area to prevent the wafer cutting tool from cutting the stress balancing structure 151.

[0087] See also Figure 4C The chip package structure 100 includes a first semiconductor device 120 and a second semiconductor device 130 stacked on each other, a dummy device 140 and a package bracket 150. The first semiconductor device 120 has a first redistribution structure 120a, the second semiconductor device 130 has a second redistribution structure 130a, and a die bonding structure 135 is electrically connected between the first redistribution structure 120a and the second redistribution structure 130a. The package bracket 150 covers the first semiconductor device 120 and the second semiconductor device 130, and a stress balance structure 151 is disposed in the package bracket 150. In addition, a first dielectric layer 161 encapsulates the first semiconductor device 120, and a second dielectric layer 162 encapsulates the second semiconductor device 130 and the dummy device 140. The first dielectric layer 161 and the second dielectric layer 162 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating or other suitable processes. The first dielectric layer 161 and the second dielectric layer 162 may be made of amorphous SiOx, SiOxCyHz, SiOxCy, SiCx or related low-k value materials, and the k value may range from 2.0 to 3.0 or 2.5 to 3.5.

[0088] In this embodiment, the first / second redistribution structure 120a / 130a of the first / second semiconductor device 120 / 130 can be used to provide high interconnection density and flexible wiring for wafer-level multi-chip packaging structures. To achieve these advantages, in addition to the redistribution layer (RDL, such as 120a and 130a) used for fan-out packaging structures, a silicon-free insert can be used. Multiple semiconductor devices can form a large computing system on a wafer instead of a traditional printed circuit board (PCB). Multiple semiconductor devices are disposed on a wafer-level insert (e.g., a back end of line (BEOL) layer). In the present disclosure FIG. 4C to FIG. 6B, the wafer-level back-end process layer supports electrical interconnection between two adjacent semiconductor devices (e.g., 120 and 130). The semiconductor devices can be bonded on one or both sides of a wafer-level insert (WLI, not shown) to improve yield and allow high-density integration. This single-sided or double-sided assembly provides system application flexibility. Known good die (KGD) can be used to provide good system yield. Metal-to-metal bonding (e.g., Cu-Cu bonding, such as 124 and 134) can be used between semiconductor devices (e.g., 120 and 130) and wafer-level inserts to form multiple fine-gap contact pads for high-density signals and to form larger contact pads for lower resistance to enable lower power and produce better yield for high-speed signals. Multiple system modules can be aggregated into a wafer-level system to reduce costs by simplifying the system architecture. The system may have different functions, such as logic, memory, input / output (I / O), power management integrated circuit (PMIC) or integrated passive device (IPD) for multiple semiconductor devices (e.g., 120 and 130) integrated on a wafer-level system to provide design flexibility for different applications.

[0089] The first semiconductor device 120 and the second semiconductor device 130 may be logic chips (e.g., central processing unit (CPU), graphics processing unit (GPU), system chip (system-on-a-chip, SoC), application processor (AP), microcontroller, memory chip (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.), power management chip (e.g., power management integrated circuit (PMIC)), radio frequency (RF) chip, sensor chip, micro-electro-mechanical-system (MEMS) chip, signal processing chip (e.g., digital signal processor (DSP)), front-end chip (e.g., analog front-end (AFE) chip), special application chip (e.g., application-specific integrated circuit (ASIC), field-programmable gate array (FPGA)). array, FPGA, etc.), input / output (I / O) die, integrated passive device (IPD) die, similar die, or a combination thereof.

[0090] In some embodiments, a die bonding structure 135 between the first semiconductor device 120 and the second semiconductor device 130 may be connected to the first redistribution structure 120a and the second redistribution structure 130a using a suitable bonding method (e.g., metal-to-metal bonding). The die bonding structure 135 includes a first conductive bump 124 and a second conductive bump 134. The first conductive bump 124 and the second conductive bump 134 are, for example, copper bumps. The first conductive bump 124 is disposed on the back side of the first semiconductor device 120, and the first conductive bump 124 may be electrically connected to the first redistribution wire interconnect 122 of the first redistribution structure 120a via the TSV structure 127. The second conductive bump 134 is disposed on the active side of the second semiconductor device 130, and the second conductive bump 134 is electrically connected to the second redistribution wire interconnect 132 of the second redistribution structure 130a.

[0091] In some embodiments, the first redistribution structure 120a may include a first redistribution dielectric layer 121, a first redistribution wire interconnect 122, and a first bonding pad 123. The first redistribution dielectric layer 121 includes a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polyphenylene bis (PBO). Each of the first redistribution dielectric layers 121 may be formed by spin coating and drying the dielectric polymer material. The thickness of each first redistribution dielectric layer 121 may be in the range of 2 microns to 40 microns (e.g., 4 microns to 20 microns). A photoresist layer may be applied over each first redistribution dielectric layer 121 and patterned using an etching process (e.g., an anisotropic etching process) to transfer the pattern in the photoresist layer to the first redistribution dielectric layer 121. Subsequently, for example, the photoresist layer may be removed by ashing. In addition, the metal filling material for the first redistribution wire interconnect 122 may include copper, nickel, or a combination thereof. The thickness of the metal fill material deposited to form each first redistribution wire interconnect 122 may be in the range of 2 microns to 40 microns (e.g., 4 microns to 10 microns), although lesser or greater thicknesses may also be used. The total number of wire levels in the first redistribution structure 120a may range from 1 to 10. Additionally, the first bonding pad 123 may be configured for solder ball bonding, and the solder ball 125 may have a thickness in the range of 25 microns to 50 microns.

[0092] The structure and manufacturing method of the second redistribution structure 130a are similar to the structure and manufacturing method of the first redistribution structure 120a, and the first redistribution structure 120a has been illustrated in the above content. The second redistribution structure 130a may include a second redistribution dielectric layer 131, a second redistribution wire interconnect 132, and a second bonding pad 133. The second redistribution dielectric layer 131 includes a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polyphenylene bis (PBO). The metal filling material for the second redistribution wire interconnect 132 may include copper, nickel, or both copper and nickel. The metal filling material of the second bonding pad 133 may include copper. In addition, the second bonding pad 133 may be configured for micro-bump (e.g., copper guide column) bonding, and the micro-bump (i.e., the second conductive bump 134) may have a thickness in the range of 25 microns to 50 microns.

[0093] In addition, a solder material (e.g., solder balls 125) may be formed on the first bonding pad 123, and the chip package structure 101 and the carrier (e.g., a silicon substrate or a glass epoxy type circuit board, etc.) are electrically connected to each other via the solder balls 125. In addition, the solder balls 125 may be ball grid array (BGA) connectors, solder balls, metal guide posts, controlled collapse chip connection (C4) bumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like.

[0094] In some embodiments, the first semiconductor device 120 includes a first bonding film 126, and the second semiconductor device 130 includes a second bonding film 136. The first bonding film 126 is disposed on the back side BS of the first semiconductor device 120, and the second bonding film 136 is disposed on the active side of the second semiconductor device 130. The active side of the second semiconductor device 130 is configured on the first bonding film 126 together with the second bonding film 136 on the back side of the first semiconductor device 120. In some embodiments, hybrid bonding or fusion bonding is used to bond the first semiconductor device 120 and the second semiconductor device 130 to each other. Bonding includes pre-bonding and annealing. During pre-bonding, a small pressure is applied to bond the first semiconductor device 120 and the second semiconductor device 130 to each other by van der Waals forces. Pre-bonding can be performed at room temperature (e.g., between about 21° C. and about 25° C.), although higher temperatures can also be used.

[0095] In some embodiments, the first conductive bump 124 passes through the first bonding film 126, the second conductive bump 134 passes through the second bonding film 136, and the first conductive bump 124 and the second conductive bump 134 are connected to each other using hybrid bonding or fusion bonding. The second semiconductor device 130 can be electrically connected to the first redistribution structure 120a of the first semiconductor device 120 via the die bonding structure 135 and the TSV structure 127 to shorten the signal transmission path.

[0096] In some embodiments, the orthographic projection of the stress balancing structure 151 overlaps with the orientation of the first semiconductor device 120, and ideally exceeds the boundary of the chip packaging area to prevent the wafer cutting tool from cutting the stress balancing structure 151. In addition, the top of the stress balancing structure 151 is covered by a cap layer 156, such as a dielectric including silicon oxide, silicon nitride, etc., and the cap layer 156 has a thermal expansion coefficient lower than the thermal expansion coefficient of the semiconductor and has a thickness D8, for example, a thickness greater than 0.1 μm.

[0097] In some embodiments, the package carrier 150 may be a heat dissipation substrate, such as a substrate having high thermal conductivity (140 to 200 W / mk) and low thermal expansion coefficient (6.5 to 9.5×10 -6 / K) of the chip packaging structure 101. A silicon substrate or other suitable material can be applied to the chip packaging structure 101 together with a plurality of semiconductor devices to improve the heat dissipation performance and match the thermal expansion coefficients of the second semiconductor device 130 and the dummy device 140. The heat dissipation substrate (i.e., the package bracket 150) is mounted on the top of the chip packaging structure 101 by, for example, a high dielectric constant adhesive 157. The adhesive 157 is, for example, an epoxy resin, and silicon dioxide can be added to the adhesive 157 to reduce the thermal expansion coefficient. The chip packaging structure 101 with a heat dissipation substrate can be used in technical fields with high heat dissipation requirements, such as mobile communications, satellite communications, high-speed computing, and electric vehicles, and can also be used in general consumer electronic products.

[0098] In some embodiments, the package carrier 150 may be a second carrier substrate (eg, a silicon substrate), and the package carrier 150 is bonded to the first semiconductor device 120 and the second semiconductor device 130 on the first carrier substrate 110 by an adhesive 157 (see Figures 1A to 1C). Then, a patterning process is performed on the back side of the package bracket 150, and the groove 152 can be etched in the package bracket 150 by using a patterned mask. Then, the stress balancing material 153 is deposited in the groove 152 together with the metal material or the insulating material by chemical vapor deposition, physical vapor deposition, spin coating or other suitable processes. A planarization process such as chemical mechanical polishing (CMP), grinding, etching, a combination thereof, etc. can be performed after the deposition process is completed. The planarization process can remove a portion of the package bracket 150 to make the package bracket 150 thinner. After the planarization process is completed, the first bracket substrate 110 (see Figures 1A to 1C ) is removed, and the package carrier 150 is singulated to complete the chip package structure 101 (see Figure 4C ).

[0099] In some embodiments, the groove position, groove density, groove width, length and depth of the stress balance structure 151 can be determined according to the warpage characteristics (warpage amount) of the chip package structure 101, and the grooves 152 of the stress balance structure 151 can have different depths, different lengths or widths, or different densities. The warpage characteristics can be measured using, for example, shadow ripple or other measurement methods or using theoretical analysis or computer simulation methods to determine the warpage characteristics, or using artificial intelligence algorithms such as neural networks, linear regression, etc. to determine the warpage characteristics.

[0100] See also Figure 5A and Figure 5B , Figure 5A and Figure 5B Schematic cross-sectional views of chip packaging structures 102 and 103 along the YY axis and their stress balancing structures according to two embodiments of the present disclosure. Figure 5A In addition to forming the stress balancing structure 151 on the back side of the package bracket 150, the chip package structure 102 may also form at least one stress balancing structure 154 to 156 in the first semiconductor device 120, the second semiconductor device 130 and / or the dummy device 140. Figure 5A As shown in FIG. 1 , the second stress balancing structure 155 is formed on the back side of the first semiconductor device 120, the third stress balancing structure 156 is formed on the back side BS of the second semiconductor device 130, and the fourth stress balancing structure 154 is formed on the back side BS of the dummy device 140. The positions, numbers, and densities of these stress balancing structures 154 to 156 can be determined according to the warpage characteristics (warpage amount) of the chip package structure 101.

[0101] That is, the stress balancing structure may be selectively formed in at least one of the package bracket 150, the first semiconductor device 120, the second semiconductor device 130, and the dummy device 140, and the stress balancing structure includes a plurality of trenches 152 and a stress balancing material 153 (such as a conductive material, an insulating material, or a semiconductor material) filled in the trenches 152. The stress balancing material 153 may include aluminum, copper, tungsten, titanium, TaN, TiN, silicon dioxide, silicon carbide, silicon nitride, or other suitable materials.

[0102] In some embodiments, the groove depth H1 in the package bracket 150 may be greater than the groove depth H2 in the dummy device 140, and the groove depth H2 in the dummy device 140 may be greater than the groove depth H3 of the first semiconductor device 120 and the second semiconductor device 130. In other embodiments, the groove depth H1 in the package bracket 150 may be less than or equal to the groove depth H2 in the dummy device 140, and the groove depth H2 in the dummy device 140 may be less than or equal to the groove depth H3 of the first semiconductor device 120 and the second semiconductor device 130.

[0103] exist Figure 5B In the embodiment, the stress balancing structure 151 is not limited to being formed on the back side of the package bracket 150, but is formed on at least one of the first semiconductor device 120, the second semiconductor device 130, and the dummy device 140. Since the stress balancing structure 151 is not formed on the back side of the package bracket 150, the thickness of the package bracket 150 can be further reduced. Figure 5B In the embodiment, since no integrated circuit or electronic component (e.g., transistor, diode, resistor, capacitor, etc.) is provided in the dummy device 140, a trench 152 having a high aspect ratio is formed on the back side of the dummy device 140 and filled with a stress balancing material 153 (i.e., a stress balancing structure 154). The carrier substrates of the first semiconductor device 120 and the second semiconductor device 130 are provided with integrated circuits and electronic components inside. Compared with the trench of the dummy device 140, the aspect ratio of the trench 152 is smaller than that of the trench 152 of the dummy device 140.

[0104] See also FIG. 6A to FIG. 6B , FIG. 6A to FIG. 6B Schematic cross-sectional views of chip package structures 104 and 105 along the YY axis and their stress balancing structures 151 according to two other embodiments of the present disclosure are shown respectively. Fig. 6A The chip package structure 104 is similar to Figure 4C The chip package structure 101, except Fig. 6A The wafer package carrier 150 ′ is formed of an epoxy resin molding material to cover the first semiconductor device 120 .

[0105] exist Fig. 6AIn the embodiment, the chip package structure 104 includes a first semiconductor device 120, a second semiconductor device 130 and a package bracket 150' stacked on each other. The first semiconductor device 120 has a first redistribution structure 120a, the second semiconductor device has a second redistribution structure 130a, and a die bonding structure 135 is electrically connected between the first redistribution structure 120a and the second redistribution structure 130a. The package bracket 150' covers the first semiconductor device 120 and the second semiconductor device 130, and a stress balancing structure 151 is disposed in the package bracket 150'.

[0106] In some embodiments, after curing the package carrier 150', a patterning process is performed on the back side of the package carrier 150', and the groove 152 can be etched in the package carrier 150' using a patterned mask. Then, the stress balancing material 153 is deposited in the groove 152 together with the metal material or the insulating material by chemical vapor deposition, physical vapor deposition, spin coating or other suitable processes. After the deposition process is completed, a planarization process such as chemical mechanical polishing (CMP), grinding, etching or a combination thereof can be performed to make the top surface of the stress balancing structure 151 coplanar with the top surface of the package carrier 150'.

[0107] exist Figure 6B In the embodiment, the chip package structure 105 includes a bracket substrate 112, a first semiconductor device 120 and a second semiconductor device 130 disposed adjacent to each other, a bridge circuit 140a and a package bracket 150'. The first semiconductor device 120 has a first redistribution structure 120a, the second semiconductor device has a second redistribution structure 130a, and a first die bonding structure 135 is electrically connected between the bridge circuit 140a and the first redistribution structure 120a. The second die bonding structure 137 is electrically connected between the bridge circuit 140a and the second redistribution structure 130a. The package bracket 150' covers the first semiconductor device 120 and the second semiconductor device 130, and a stress balancing structure 151 is disposed in the package bracket 150'.

[0108] In some embodiments, for example, the carrier substrate 112 is, for example, a silicon substrate, a printed circuit board, or other suitable substrate, the bridge circuit 140a is disposed on the carrier substrate 112, and the bridge circuit 140a is formed on the carrier substrate 112 by a redistribution process. The structure and method of the bridge circuit 140a are generally similar to the first redistribution structure 120a and the second redistribution structure 130a described above, and will not be repeated here. The bridge circuit 140 may include a third redistribution dielectric layer 141, a third redistribution wire interconnect 142, and a third bonding pad 143. The third redistribution dielectric layer 141 includes a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polyphenylene bisoxazole (PBO).

[0109] In some embodiments, the first semiconductor device 120 and the second semiconductor device 130 are disposed on the bridge circuit 140a. The first die bonding structure 135 disposed between the first semiconductor device 120 and the bridge circuit 140a uses a suitable bonding method (e.g., metal-to-metal bonding, including Cu-Cu bonding or Al-Al bonding) to connect with the first redistribution structure 120a and the bridge circuit 140a. The first die bonding structure 135 includes a first conductive bump 124 and a third conductive bump 144, the first conductive bump 124 and the third conductive bump 144 are, for example, copper bumps, and the first conductive bump 124 is disposed on the active side of the first semiconductor device 120. The third conductive bump 144 is disposed on the top surface of the bridge circuit 140a, and the first conductive bump 124 is electrically connected to the third conductive bump 144. In addition, the second die bonding structure 137 disposed between the second semiconductor device 130 and the bridge circuit 140a uses a suitable bonding method (e.g., metal-to-metal bonding, including Cu-Cu bonding or Al-Al bonding) to connect with the second redistribution structure 130a and the bridge circuit 140a. The second die bonding structure 137 includes a second conductive bump 134 and a fourth conductive bump 145. The second conductive bump 134 and the fourth conductive bump 145 are, for example, copper bumps. The second conductive bump 134 is disposed on the active side of the second semiconductor device 130. The fourth conductive bump 145 is disposed on the top surface of the bridge circuit 140a, and the second conductive bump 134 is electrically connected to the fourth conductive bump 145. In some embodiments, the first semiconductor device 120 and the second semiconductor device 130 are electrically connected to each other via the first die bonding structure 135, the second die bonding structure 137, and the bridge circuit 140a. In addition, the first semiconductor device 120 and the second semiconductor device 130 may also be electrically connected to the solder balls 113 (or conductive bumps) respectively under the carrier substrate 112 via the bridge circuit 140 a .

[0110] In some embodiments, the first semiconductor device 120 includes a first bonding film 126, and the second semiconductor device 130 includes a second bonding film 136. The first bonding film 126 is disposed on the active side of the first semiconductor device 120, and the second bonding film 136 is disposed on the active side of the second semiconductor device 130. In addition, the bridge circuit 140a includes a third bonding film 146 disposed on the top surface of the bridge circuit 140a. The active side of the first semiconductor device 120 is disposed on the third bonding film 146 on the top surface of the bridge circuit 140a together with the first bonding film 126, and the active side of the second semiconductor device 130 is disposed on the third bonding film 146 on the top surface of the bridge circuit 140a together with the second bonding film 136. In some embodiments, hybrid bonding or fusion bonding is used to dispose the first semiconductor device 120 and the second semiconductor device 130 on the bridge circuit 140a. Bonding includes pre-bonding and annealing. During the pre-bonding, a small pressure is applied to bond the first semiconductor device 120 and the bridge circuit 140 a to each other by the van der Waals force, and to bond the second semiconductor device 130 and the bridge circuit 140 a to each other by the van der Waals force.

[0111] In some embodiments, the first conductive bump 124 passes through the first bonding film 126, the second conductive bump 134 passes through the second bonding film 136, and the third conductive bump 144 passes through the third bonding film 146, and the fourth conductive bump 145 passes through the third bonding film 146, the first conductive bump 124 and the third conductive bump 144 are bonded to each other by hybrid bonding or fusion bonding, and the second conductive bump 134 and the fourth conductive bump 145 are bonded to each other by hybrid bonding or fusion bonding.

[0112] In some embodiments, the package bracket 150' is formed of, for example, an epoxy resin material to encapsulate the first semiconductor device 120 and the second semiconductor device 130. The package bracket 150' includes, for example, an epoxy molding compound (EMC), and the epoxy resin compound can be hardened (i.e., cured) to provide the function of a dielectric material with sufficient hardness and mechanical strength. The EMC may include an epoxy resin, a curing agent, silicon oxide (as a filler material), and other additives. The EMC can be available in liquid form or solid form depending on viscosity and fluidity. Liquid EMC generally provides better handling, good fluidity, less porosity, more filling, and less flow marks. Solid EMC generally provides less curing shrinkage, better stand-off, and lower die drift. A high filler content in the EMC (e.g., 85% by weight) reduces molding time, molding shrinkage, and molding warpage. A uniform filler size distribution in the EMC can reduce flow marks and enhance flow. The curing temperature of the EMC is lower than the release (peeling) temperature of the die attaching film (DAF).

[0113] In some embodiments, after curing the package carrier 150', a patterning process is performed on the back side of the package carrier 150', and the groove 152 can be etched in the package carrier 150' using a patterned mask. Then, the stress balancing material 153 is deposited in the groove 152 together with the metal material or the insulating material by chemical vapor deposition, physical vapor deposition, spin coating or other suitable processes. After the deposition process is completed, a planarization process such as chemical mechanical polishing (CMP), grinding, etching or a combination thereof can be performed to make the top surface of the stress balancing structure 151 coplanar with the top surface of the package carrier 150'.

[0114] See also FIG. 6A to FIG. 6B In this embodiment, a method for preventing warping of a chip packaging structure is provided, and the method includes the following steps. A first semiconductor device 120 and a second semiconductor device 130 are sequentially formed on a carrier substrate 110 or 112. The carrier substrate 110 or 112 is, for example, a silicon substrate or other suitable substrate. The carrier substrates 110 and 112 can be used in a wafer-level packaging process. Although the carrier substrate 110 is not shown in FIG. Fig. 6A However, it is desirable that the carrier substrate 110 can be removed after the package carrier 150 is formed. The first semiconductor device 120 has a first redistribution structure 120a, and the second semiconductor device has a second redistribution structure 130a. The first semiconductor device 120 and the second semiconductor device 130 are arranged opposite to each other (eg, Fig. 6A ) and are arranged adjacent to each other (as shown in Figure 6BThe first redistribution structure 120a and the second redistribution structure 130a are electrically connected via at least one die bonding structure. Fig. 6A In FIG. 1 , the die bonding structure 135 is vertically connected between the first semiconductor device 120 and the second semiconductor device 130 . Figure 6B In the embodiment, the first die bonding structure 135 is vertically connected between the first semiconductor device 120 and the bridge circuit 140a, the second die bonding structure 137 is vertically connected between the second semiconductor device 130 and the bridge circuit 140a, and the bridge circuit 140a is electrically connected between the first semiconductor device 120 and the second semiconductor device 130. Then, a package bracket 150 or 150' is formed, and the package bracket 150 or 150' covers the first semiconductor device 120 and the second semiconductor device 130. Figure 4C and Figure 5A As shown in FIG. 1 , the package bracket 150 may be made of a fiber material, a polymer material, a semiconductor material, or a glass material, and the package bracket 150′ may be formed of an epoxy resin molding material. Next, the stress balancing structure 151 is formed in the package bracket 150 or 150′. According to the warpage characteristics of the chip package structures 101 to 105, the stress balancing structure 151 is distributed in the package bracket 150 or 150′. The configuration of the stress balancing structure 151 may refer to FIG. 3A to FIG. 3D , and will not be repeated here.

[0115] In some embodiments, Fig. 6A and Figure 6B The chip package structures 104 and 105 may further include another stress balancing structure 155 and 156 disposed in at least one of the first semiconductor device 120 and the second semiconductor device 130. The configuration of the stress balancing structure 155 and 156 may refer to Figure 5A and Figure 5B , and will not be repeated here.

[0116] The present disclosure relates to a chip package structure and a method for preventing the chip package structure from warping. The stress balancing structure for preventing the chip package structure from warping can be formed according to the warping characteristics so as to balance the stress of the chip package structure in different warping directions.

[0117] According to some embodiments of the present disclosure, a chip packaging structure is provided, which includes a first semiconductor device, a second semiconductor device, a die bonding structure, a packaging bracket and a stress balance structure. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, and the die bonding structure is electrically connected between the first redistribution structure and the second redistribution structure. The packaging bracket covers the first semiconductor device and the second semiconductor device, and the stress balance structure is disposed in the packaging bracket. In some embodiments, the stress balance structure includes at least one groove and a filling material filled in the groove. In some embodiments, the filling material includes aluminum, copper, tungsten, titanium, TaN, TiN, silicon dioxide, silicon carbide, silicon nitride or a combination thereof. In some embodiments, the groove is a long and narrow structure, wherein the long side of the groove is perpendicular to the warping direction or parallel to the warping direction. In some embodiments, a material of the packaging bracket includes a fiber material, a polymer material, a semiconductor material, a glass material or a combination thereof. In some embodiments, the die bonding structure includes a first conductive bump and a second conductive bump, the first conductive bump is disposed on the back side of the first semiconductor device, and the first conductive bump is electrically connected to the first redistribution structure via a through silicon via structure, the second conductive bump is configured on the active side of the second semiconductor device, and the second conductive bump is electrically connected to the second redistribution structure. In some embodiments, the first semiconductor device includes a first bonding film, the second semiconductor device includes a second bonding film, and the first bonding film is disposed on the first semiconductor device, the second bonding film is disposed on the active side of the second semiconductor device, and the active side of the second semiconductor device is disposed on the first bonding film together with the second bonding film. In some embodiments, the first conductive bump passes through the first bonding film, the second conductive bump passes through the second bonding film, and the first conductive bump and the second conductive bump are bonded to each other using hybrid bonding or fusion bonding. In some embodiments, the chip packaging structure further includes another stress balance structure disposed in at least one of the first semiconductor device and the second semiconductor device.

[0118] According to some embodiments of the present disclosure, a chip packaging structure is provided, which includes a first semiconductor device, a second semiconductor device, a bridge circuit, a first die bonding structure, a second die bonding structure, a packaging bracket and a stress balance structure. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, the first die bonding structure is electrically connected between the bridge circuit and the first redistribution structure, and the second die bonding structure is electrically connected between the bridge circuit and the second redistribution structure. The packaging bracket covers the first semiconductor device and the second semiconductor device, and the stress balance structure is disposed in the packaging bracket. In some embodiments, the first die bonding structure includes a first conductive bump and a third conductive bump, the first conductive bump is disposed on the active side of the first semiconductor device, the third conductive bump is disposed on the top surface of the bridge circuit, and the first conductive bump is electrically connected to the third conductive bump, and the second die bonding structure includes a second conductive bump and a fourth conductive bump, the second conductive bump is disposed on the active side of the second semiconductor device, the fourth conductive bump is disposed on the top surface of the bridge circuit, and the second conductive bump is electrically connected to the fourth conductive bump. In some embodiments, the first semiconductor device includes a first bonding film, the second semiconductor device includes a second bonding film, the first bonding film is disposed on the active side of the first semiconductor device, the second bonding film is disposed on the active side of the second semiconductor device, the bridge circuit includes a third bonding film disposed on the top surface of the bridge circuit, the active side of the first semiconductor device is disposed on the third bonding film together with the first bonding film, and the active side of the second semiconductor device is disposed on the third bonding film together with the second bonding film. In some embodiments, the first conductive bump passes through the first bonding film, the second conductive bump passes through the second bonding film, and the third conductive bump passes through the third bonding film, the fourth conductive bump passes through the third bonding film, the first conductive bump and the third conductive bump are bonded to each other by hybrid bonding or fusion bonding, and the second conductive bump and the fourth conductive bump are bonded to each other by hybrid bonding or fusion bonding. In some embodiments, the chip packaging structure further includes another stress balancing structure disposed in at least one of the first semiconductor device and the second semiconductor device.

[0119] According to some embodiments of the present disclosure, a method for preventing warping of a chip packaging structure is provided, the method comprising the following steps. A first semiconductor device and a second semiconductor device are sequentially arranged on a bracket substrate, the first semiconductor device having a first redistribution structure, the second semiconductor device having a second redistribution structure, the first semiconductor device and the second semiconductor device being arranged opposite to each other or adjacent to each other, and the first redistribution structure and the second redistribution structure being electrically connected via at least one die bonding structure. A package bracket is formed, and the package bracket covers the first semiconductor device and the second semiconductor device. A stress balancing structure is formed in the package bracket, and the stress balancing structure is distributed in the package bracket according to a warping characteristic of the chip packaging structure. In some embodiments, the package bracket is formed of an epoxy resin molding material to cover at least one of the first semiconductor device and the second semiconductor device. In some embodiments, after the package bracket is cured, a patterning process is performed on the back side of the package bracket, and a groove is etched in the package bracket using a patterned mask, and a stress balancing material is deposited in the groove to form a stress balancing structure. In some embodiments, the package carrier is a carrier substrate, the patterning process is performed on the back side of the package carrier, and the groove is etched in the package carrier using a patterned mask, and the stress balancing material is deposited in the groove to form a stress balancing structure. In some embodiments, the stress balancing structure includes a material selected from the group consisting of aluminum, copper, tungsten, titanium, TaN, TiN, silicon dioxide, silicon carbide, silicon nitride, or a combination thereof. In some embodiments, the method further includes forming another stress balancing structure in at least one of the first semiconductor device and the second semiconductor device.

[0120] According to some embodiments of the present disclosure, a chip packaging structure is provided, comprising a first semiconductor device, a second semiconductor device, a packaging bracket and two stress balance structures. The first semiconductor device has a first redistribution structure, the second semiconductor device has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. The packaging bracket covers the first semiconductor device and the second semiconductor device. One stress balance structure is configured in the packaging bracket, and another stress balance structure is disposed in at least one of the first semiconductor device and the second semiconductor device.

[0121] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A chip packaging structure, characterized in that: Include: a first semiconductor device having a first redistribution structure; a second semiconductor device having a second redistribution structure; a die bonding structure electrically connected between the first redistribution structure and the second redistribution structure; a package bracket covering the first semiconductor device and the second semiconductor device; and A stress balancing structure is disposed in the packaging bracket.

2. The chip packaging structure according to claim 1, wherein: The stress balance structure includes at least one groove and a filling material filled in the at least one groove.

3. The chip packaging structure according to claim 2, wherein: The at least one groove is a long and narrow structure, wherein a long side of the at least one groove is perpendicular to a warping direction or parallel to the warping direction.

4. The chip packaging structure according to claim 1, wherein: The die bonding structure includes a first conductive bump and a second conductive bump, wherein the first conductive bump is disposed on a back side of the first semiconductor device and is electrically connected to the first redistribution structure via a through silicon via structure, and the second conductive bump is disposed on an active side of the second semiconductor device and is electrically connected to the second redistribution structure.

5. The chip packaging structure as claimed in claim 4, characterized in that: The first semiconductor device includes a first bonding film, the second semiconductor device includes a second bonding film, and the first bonding film is arranged on the first semiconductor device, the second bonding film is arranged on the active side of the second semiconductor device, and the active side of the second semiconductor device is arranged on the first bonding film together with the second bonding film.

6. A chip packaging structure, characterized in that: Include: a first semiconductor device having a first redistribution structure; a second semiconductor device having a second redistribution structure; A bridge circuit; a first die bonding structure electrically connected between the bridge circuit and the first redistribution structure; a second die bonding structure electrically connected between the bridge circuit and the second redistribution structure; a package bracket covering the first semiconductor device and the second semiconductor device; and A stress balancing structure is disposed in the packaging bracket.

7. The chip packaging structure according to claim 6, wherein: The first grain bonding structure includes a first conductive bump and a third conductive bump, the first conductive bump is arranged on an active side of the first semiconductor device, the third conductive bump is arranged on a top surface of the bridge circuit, and the first conductive bump is electrically connected to the third conductive bump, and the second grain bonding structure includes a second conductive bump and a fourth conductive bump, the second conductive bump is arranged on an active side of the second semiconductor device, the fourth conductive bump is arranged on the top surface of the bridge circuit, and the second conductive bump is electrically connected to the fourth conductive bump.

8. The chip packaging structure according to claim 7, wherein: The first semiconductor device includes a first bonding film, the second semiconductor device includes a second bonding film, the first bonding film is arranged on the active side of the first semiconductor device, the second bonding film is arranged on the active side of the second semiconductor device, the bridge circuit includes a third bonding film arranged on the top surface of the bridge circuit, the active side of the first semiconductor device is arranged on the third bonding film together with the first bonding film, and the active side of the second semiconductor device is arranged on the third bonding film together with the second bonding film.

9. The chip packaging structure according to claim 8, wherein: The first conductive bump passes through the first bonding film, the second conductive bump passes through the second bonding film, the third conductive bump passes through the third bonding film, and the fourth conductive bump passes through the third bonding film. The first conductive bump and the third conductive bump are bonded to each other by hybrid bonding or fusion bonding, and the second conductive bump and the fourth conductive bump are bonded to each other by hybrid bonding or fusion bonding.

10. A chip packaging structure, characterized in that: Include: a first semiconductor device having a first redistribution structure; a second semiconductor device having a second redistribution structure, the first redistribution structure being bonded to the second redistribution structure; a package bracket covering the first semiconductor device and the second semiconductor device; A stress balancing structure is disposed in the packaging bracket; and Another stress-balancing structure is disposed in at least one of the first semiconductor device and the second semiconductor device.

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