Self-cleaning low-power-consumption flow chip

Abstract

The utility model relates to a self-cleaning flow chip with low power consumption. The light emitting diode comprises a substrate; the supporting structure layer is arranged on the substrate; the platinum thermal resistance wire layer is arranged on the supporting structure layer; the first insulating layer covers the platinum thermal resistance wire layer; the upstream temperature measuring element thermopiles, the central heat source and the downstream temperature measuring element thermopiles are respectively arranged on the first insulating layer, and the multiple groups of upstream temperature measuring element thermopiles and the multiple groups of downstream temperature measuring element thermopiles are respectively distributed side by side along the longitudinal direction of the chip; and front release isolation through holes are formed between thermopiles of the adjacent upstream temperature measurement elements and between thermopiles of the adjacent downstream temperature measurement elements, and the front release isolation through holes extend to the back release cavity. According to the utility model, the sensitive area of the temperature measuring element can be automatically cleaned, and the power consumption can be reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of flow sensors, in particular to a self-cleaning low-power flow chip. Background Art

[0002] Thermal flow sensor is a device that uses thermal sensing effect to measure the flow of gas and liquid. It consists of hot wire sensor, compensation circuit, temperature compensation circuit and operational amplifier. This sensor has been widely used in many fields, including industrial automation, air conditioning, automobile industry, medical equipment and robotics, due to its high precision, fast response and little impact on the medium.

[0003] However, after long-term use, the sensitive areas of the temperature measuring elements of existing flow chips are prone to moisture and dirt, resulting in reduced measurement accuracy and requiring regular cleaning and maintenance. In addition, existing flow chips also have high power consumption, which not only increases the cost of use, but also limits their application in certain scenarios where power supply is limited or low power consumption is required. Summary of the invention

[0004] To this end, the utility model provides a self-cleaning low-power flow chip, which can not only automatically clean the sensitive area of ​​the temperature measuring element, but also reduce power consumption.

[0005] In order to solve the above technical problems, the utility model provides a self-cleaning low-power flow chip, comprising:

[0006] A substrate provided with a backside release cavity;

[0007] A supporting structure layer is disposed on the substrate;

[0008] A platinum thermal resistance wire layer is arranged on the supporting structure layer;

[0009] A first insulating layer, covering the platinum thermal resistance wire layer;

[0010] The upstream temperature measuring element thermopile, the central heat source and the downstream temperature measuring element thermopile are respectively arranged on the first insulating layer, wherein a plurality of groups of the upstream temperature measuring element thermopile and a plurality of groups of the downstream temperature measuring element thermopile are respectively arranged side by side along the longitudinal direction of the chip;

[0011] Among them, there are front release isolation through holes between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles, and the front release isolation through holes extend to the back release cavity.

[0012] In one embodiment of the present invention, the platinum thermal resistance wire layer is respectively arranged below the cold end of the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile.

[0013] In one embodiment of the utility model, the upstream temperature measuring element thermopile comprises an upstream temperature measuring element thermopile lower layer thermocouple and an upstream temperature measuring element thermopile upper layer thermocouple;

[0014] The downstream temperature measuring element thermopile comprises a downstream temperature measuring element thermopile lower layer thermocouple and a downstream temperature measuring element thermopile upper layer thermocouple;

[0015] The upstream temperature measuring element thermopile lower layer thermocouple and the downstream temperature measuring element thermopile lower layer thermocouple are covered with a second insulating layer;

[0016] The upper thermocouple of the upstream temperature measuring element thermopile and the upper thermocouple of the downstream temperature measuring element thermopile are covered with a third insulating layer.

[0017] In one embodiment of the utility model, it also includes a connecting wire structure that runs through the third insulating layer;

[0018] The connecting wire structure includes an upstream cold end connecting wire connected to the lower thermocouple of the upstream temperature measuring element thermopile, an upstream hot end connecting wire connected between the lower thermocouple of the upstream temperature measuring element thermopile and the upper thermocouple of the upstream temperature measuring element thermopile, a downstream cold end connecting wire connected to the lower thermocouple of the downstream temperature measuring element thermopile, a downstream hot end connecting wire connected between the lower thermocouple of the downstream temperature measuring element thermopile and the upper thermocouple of the downstream temperature measuring element thermopile, a central heat source wire connected to the central heat source, and an upstream resistance wire connecting wire and a downstream resistance wire connecting wire connected to the platinum thermal resistance wire layer.

[0019] In one embodiment of the present invention, the support structure layer includes a first silicon oxide support layer, a silicon nitride support layer and a second silicon oxide support layer which are sequentially arranged on the surface of the substrate.

[0020] In one embodiment of the present invention, a silicon nitride passivation layer is provided on the surface of the third insulating layer.

[0021] In one embodiment of the utility model, the front release isolation through hole sequentially penetrates the silicon nitride passivation layer, the third insulating layer, the second insulating layer, the first insulating layer, the second silicon oxide support layer, the silicon nitride support layer and the first silicon oxide support layer.

[0022] In one implementation of the utility model, the platinum thermal resistance wire layer is serpentine, and the front release isolation through hole passes through the serpentine gap formed by the platinum thermal resistance wire layer.

[0023] The above technical solution of the utility model has the following advantages compared with the prior art:

[0024] The self-cleaning low-power flow chip described in the utility model adopts a platinum thermal resistance wire layer, which is located on the upper part of the insulating layer and the lower part of the temperature measuring element functional layer, so that after each use, the sensitive area of ​​the temperature measuring element can be automatically cleaned by applying high voltage power supply, thereby ensuring that the accuracy is not affected when it is used next time. In addition, by setting an isolation through hole between adjacent thermocouple pairs of temperature measuring elements, the through hole separates the back heat transfer channel, improves the sensitivity of the temperature measuring element to heat, so that the central heat source only needs a very small voltage drive to make the temperature measuring element sense heat changes, which further improves the overall resolution of the chip and reduces the power consumption of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0026] Figure 1 It is a transverse cross-sectional schematic diagram of the flow chip with cleaning function of the utility model.

[0027] Figure 2 It is a schematic diagram of the longitudinal cross-section structure of the flow chip with a cleaning function of the utility model.

[0028] Figure 3 It is a schematic diagram of the thermopile temperature measuring element, the "snake-shaped" platinum thermal resistance wire layer and the front release isolation through hole of the utility model.

[0029] Figure 4 It is a schematic diagram of the serpentine platinum thermal resistor wire layer and the front release isolation through hole of the utility model.

[0030] Description of the Figures in the Specification:

[0031] 1. Substrate;

[0032] 2. A first silicon oxide support layer;

[0033] 3. Silicon nitride support layer;

[0034] 4. A second silicon oxide support layer;

[0035] 5. Platinum thermal resistance wire layer;

[0036] 6a, first insulating layer; 6b, second insulating layer; 6c, third insulating layer;

[0037] 7a, the thermocouple of the lower layer of the thermopile of the upstream temperature measuring element; 7b, the thermocouple of the lower layer of the thermopile of the downstream temperature measuring element;

[0038] 8. Central heat source;

[0039] 8a, upper thermocouple of the thermopile of the upstream temperature measuring element; 8b, upper thermocouple of the thermopile of the downstream temperature measuring element;

[0040] 91. Upstream cold end connecting wire; 92. Upstream hot end connecting wire; 93. Downstream cold end connecting wire; 94. Downstream hot end connecting wire; 95. Upstream resistance wire connecting wire; 96. Downstream resistance wire connecting wire; 97. Central heat source wire;

[0041] 10. Silicon nitride passivation layer;

[0042] 11. Front release isolation through hole;

[0043] 12. Back release cavity. DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0045] Reference Figures 1 to 3 As shown, a self-cleaning low-power flow chip comprises:

[0046] A substrate 1 is provided with a backside release cavity 12;

[0047] A supporting structure layer, disposed on the substrate 1;

[0048] The platinum thermal resistance wire layer 5 is arranged on the supporting structure layer;

[0049] A first insulating layer 6a, covering the platinum thermal resistance wire layer 5;

[0050] The upstream temperature measuring element thermopile, the central heat source 8 and the downstream temperature measuring element thermopile are respectively arranged on the first insulating layer 6a, wherein a plurality of groups of the upstream temperature measuring element thermopile and a plurality of groups of the downstream temperature measuring element thermopile are respectively arranged side by side along the longitudinal direction of the chip;

[0051] Among them, there are front release isolation through holes 11 between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles, and the front release isolation through holes 11 extend to the back release cavity 12.

[0052] Specifically, the platinum thermal resistance wire layer 5 is disposed below the cold end of each of the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile.

[0053] Specifically, the upstream temperature measuring element thermopile includes an upstream temperature measuring element thermopile lower layer thermocouple 7a and an upstream temperature measuring element thermopile upper layer thermocouple 8a;

[0054] The downstream temperature measuring element thermopile comprises a downstream temperature measuring element thermopile lower layer thermocouple 7b and a downstream temperature measuring element thermopile upper layer thermocouple 8b;

[0055] The upstream temperature measuring element thermopile lower layer thermocouple 7a and the downstream temperature measuring element thermopile lower layer thermocouple 7b are covered with a second insulating layer 6b;

[0056] The upstream temperature measuring element thermopile upper thermocouple 8a and the downstream temperature measuring element thermopile upper thermocouple 8b are covered with a third insulating layer 6c.

[0057] Specifically, it also includes a connecting wire structure that runs through the third insulating layer 6c;

[0058] The connecting wire structure includes an upstream cold end connecting wire 91 connected to the lower thermocouple 7a of the upstream temperature measuring element thermopile, an upstream hot end connecting wire 92 connected between the lower thermocouple 7a of the upstream temperature measuring element thermopile and the upper thermocouple 8a of the upstream temperature measuring element thermopile, a downstream cold end connecting wire 93 connected to the lower thermocouple 7b of the downstream temperature measuring element thermopile, a downstream hot end connecting wire 94 connected between the lower thermocouple 7b of the downstream temperature measuring element thermopile and the upper thermocouple 8b of the downstream temperature measuring element thermopile, a central heat source wire 97 connected to the central heat source 8, and an upstream resistance wire connecting wire 95 and a downstream resistance wire connecting wire 96 connected to the platinum thermal resistance wire layer 5.

[0059] Specifically, the support structure layer includes a first silicon oxide support layer 2, a silicon nitride support layer 3 and a second silicon oxide support layer 4 which are sequentially arranged on the surface of the substrate 1.

[0060] Specifically, a silicon nitride passivation layer 10 is disposed on the surface of the third insulating layer 6c to enhance the overall anti-pollution capability of the chip.

[0061] Specifically, the front release isolation through hole 11 sequentially penetrates the silicon nitride passivation layer 10, the third insulating layer 6c, the second insulating layer 6b, the first insulating layer 6a, the second silicon oxide support layer 4, the silicon nitride support layer 3 and the first silicon oxide support layer 2.

[0062] Specifically, the platinum thermal resistance wire layer 5 is in a “snake shape”, and the front release isolation through hole 11 passes through the serpentine gap formed by the platinum thermal resistance wire layer 5 .

[0063] In this embodiment, the platinum resistance wire layer 5 includes two groups, which are respectively formed below the cold ends of the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile. A high voltage power supply of 5-10V is supplied to the layer (the upstream resistance wire connecting wire 95 and the downstream resistance wire connecting wire 96) to achieve self-cleaning treatment of water vapor and dirt attached to the sensitive area of ​​the temperature measuring element, thereby ensuring that the accuracy is not affected when used next time.

[0064] In this embodiment, refer to Figure 4 As shown, the platinum thermal resistance wire layer 5 is in a "snake shape" and is composed of a plurality of straight-edged U-shaped structures. The front release isolation through hole 11 passes through the serpentine gap formed by the platinum thermal resistance wire layer 5.

[0065] By setting a "snake-shaped" platinum thermal resistor wire layer 5, a self-cleaning effect can be achieved when it is heated. Compared with thin film resistors, serpentine resistors have a larger aspect ratio, a higher resistance value, and a greater heating power. Through the serpentine distribution, its specific surface area on the substrate surface is larger and the heat distribution is more uniform.

[0066] After the temperature measuring element senses the temperature, it will transfer heat from the hot end to the cold end, forming the Seebeck effect and generating a thermoelectric potential between the hot and cold ends. That is, this part of heat conduction is necessary and is also one of the important factors that determine the sensitivity of the chip, because the greater the temperature difference between the hot and cold ends, the greater the thermoelectric potential, the greater the output signal, and the greater the sensitivity of the chip. However, in addition to transferring heat to the cold end, the hot end will also transfer heat to the left and right adjacent thermocouples and the lower insulating support layer. By preparing the front isolation release hole, the hot end can be prevented from transferring heat to the left and right adjacent thermocouples. At the same time, in conjunction with the back release cavity 12, the lower insulating support layer between each group of thermocouples of the thermopile temperature measuring element is directly completely carved open, thereby blocking the heat transfer channel from the hot end to the bottom insulating support layer. Therefore, after the direction of the unnecessary heat transfer channel is reduced, when the hot end conducts heat, there is only one heat transfer channel, which is to flow to the cold end, so the thermoelectric potential between the hot and cold ends will be higher, and the chip sensitivity will also be higher. By bidirectional release etching on the front and back sides, the insulating layer between the adjacent thermocouple pairs of the temperature measuring element is formed into an isolation through hole, thereby isolating the back heat transfer channel and improving the sensitivity of the temperature measuring element to heat. This allows the central heat source 8 to be driven by only a small voltage, and the temperature measuring element can sense the heat change, thereby improving the overall resolution of the chip and reducing the chip power consumption.

[0067] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the utility model rather than to limit it. Although the utility model has been described in detail with reference to examples, ordinary technicians in the field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. A self-cleaning low-power flow chip, characterized in that: include: A substrate (1) provided with a backside release cavity (12); A supporting structure layer, arranged on the substrate (1); A platinum thermal resistance wire layer (5) is arranged on the supporting structure layer; A first insulating layer (6a), covering the platinum thermal resistance wire layer (5); The upstream temperature measuring element thermopile, the central heat source (8) and the downstream temperature measuring element thermopile are respectively arranged on the first insulating layer (6a), wherein a plurality of groups of the upstream temperature measuring element thermopile and a plurality of groups of the downstream temperature measuring element thermopile are respectively distributed side by side in the longitudinal direction of the chip; Wherein, the front release isolation through holes (11) between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles extend to the back release cavity (12).

2. A self-cleaning low-power flow chip according to claim 1, characterized in that: The platinum thermal resistance wire layer (5) is respectively arranged below the cold end of the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile.

3. A self-cleaning low-power flow chip according to claim 1, characterized in that: The upstream temperature measuring element thermopile comprises an upstream temperature measuring element thermopile lower layer thermocouple (7a) and an upstream temperature measuring element thermopile upper layer thermocouple (8a); The downstream temperature measuring element thermopile comprises a downstream temperature measuring element thermopile lower layer thermocouple (7b) and a downstream temperature measuring element thermopile upper layer thermocouple (8b); The upstream temperature measuring element thermopile lower layer thermocouple (7a) and the downstream temperature measuring element thermopile lower layer thermocouple (7b) are covered with a second insulating layer (6b); The upper thermocouple (8a) of the upstream temperature measuring element thermopile and the upper thermocouple (8b) of the downstream temperature measuring element thermopile are covered with a third insulating layer (6c).

4. A self-cleaning low-power flow chip according to claim 3, characterized in that: It also includes a connecting wire structure that passes through the third insulating layer (6c); The connecting wire structure comprises an upstream cold end connecting wire (91) connected to the lower thermocouple (7a) of the upstream temperature measuring element thermopile, an upstream hot end connecting wire (92) connected between the lower thermocouple (7a) of the upstream temperature measuring element thermopile and the upper thermocouple (8a) of the upstream temperature measuring element thermopile, a downstream cold end connecting wire (93) connected to the lower thermocouple (7b) of the downstream temperature measuring element thermopile, a downstream hot end connecting wire (94) connected between the lower thermocouple (7b) of the downstream temperature measuring element thermopile and the upper thermocouple (8b) of the downstream temperature measuring element thermopile, a central heat source wire (97) connected to the central heat source (8), and an upstream resistance wire connecting wire (95) and a downstream resistance wire connecting wire (96) connected to the platinum thermal resistance wire layer (5).

5. A self-cleaning low-power flow chip according to claim 3, characterized in that: The support structure layer comprises a first silicon oxide support layer (2), a silicon nitride support layer (3) and a second silicon oxide support layer (4) which are sequentially arranged on the surface of the substrate (1).

6. A self-cleaning low-power flow chip according to claim 5, characterized in that: A silicon nitride passivation layer (10) is provided on the surface of the third insulating layer (6c).

7. A self-cleaning low-power flow chip according to claim 6, characterized in that: The front release isolation through hole (11) sequentially penetrates the silicon nitride passivation layer (10), the third insulating layer (6c), the second insulating layer (6b), the first insulating layer (6a), the second silicon oxide support layer (4), the silicon nitride support layer (3) and the first silicon oxide support layer (2).

8. The self-cleaning low-power flow chip according to claim 1, characterized in that: The platinum thermal resistance wire layer (5) is in a serpentine shape, and the front release isolation through hole (11) passes through the serpentine gap formed by the platinum thermal resistance wire layer (5).

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