Asynchronous finite state machine, switching converter and switching circuit

Abstract

The utility model relates to an asynchronous finite state machine, a switching converter and a switching circuit. The asynchronous finite-state machine has a state coupled by transitions implemented by the respective free flip-flops. Each flip-flop supplies bits of an arrival state of a corresponding transition and receives bits of an initial state of the transition at its data input and receives a first signal dedicated to the flip-flop at its control input. The circuitry supplies, for each transition, a second signal requesting the transition. Another circuit generates a pulse of the first signal dedicated to the transitioned flip-flop and a pulse of the first signal dedicated to each flip-flop that supplies bits to the transitioned flip-flop based on the second signal each time a transition is requested and without a pulse of the first signal.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French Patent Application No. 2302253, filed on March 10, 2023, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits, and in particular to a finite state machine (FSM) of a switching converter, ie, a finite state machine for supplying a control signal to a cut-off switch of the switching converter. Background Art

[0004] A switching converter is a circuit used in a wide variety of applications to convert an input voltage (eg, a direct current (DC) voltage) of the converter to an output voltage (eg, a DC output voltage) of the converter, where the value of the output voltage is determined by a set point.

[0005] Figure 1 An example of such a switching converter 1 is illustrated very schematically.

[0006] The converter 1 comprises a high-side switch HSS and a low-side switch LSS.

[0007] The switch HSS couples the node 100 of the converter 1 to a connection node (or switching node) 102 of the converter 1. The node 100 is configured to receive a supply potential VDD.

[0008] The switch LSS couples a node 104 of the converter 1 to the node 102. The node 104 is configured to receive a reference potential, for example a ground GND potential.

[0009] The potential VDD referenced to the reference potential GND corresponds to the input voltage or the power supply voltage of the converter 1 .

[0010] The converter 1 further comprises an inductor L. The inductor L couples the node 102 to the output terminal OUT of the converter 1. An output voltage Vout is available at the output terminal OUT of the converter 1.

[0011] As an example, each switch HSS, LSS is implemented by one or more MOS transistors.

[0012] In order to control the cut-off switches HSS and LSS, the converter comprises a finite state machine FSM, or in other words, a circuit FSM implementing the finite state machine. The circuit FSM is configured to control each of the switches HSS and LSS to be in an on and off state.

[0013] More specifically, the state machine FSM is configured to supply a first binary signal cmdH having a first binary state for controlling the switch HSS to be in an off state and a second binary state for controlling the switch HSS to be in an on state. Similarly, the state machine FSM is configured to supply a second binary signal cmdL having a first binary state for controlling the switch LSS to be in an off state and a second binary state for controlling the switch LSS to be in an on state.

[0014] As an example, the signal cmdH is supplied directly or via a driver circuit DriverH to a control terminal of a switch HSS, for example, to a gate of a MOS transistor implementing the switch. As an example, the signal cmdL is supplied directly or via a driver circuit DriverL to a control terminal of a switch LSS, for example, to a gate of a MOS transistor implementing the switch.

[0015] The binary state of the signals cmdH and cmdL is determined by the current state of the state machine FSM.

[0016] The state machine FSM comprises a plurality of states coupled together by transitions. In order to determine whether the state machine FSM should or should not implement a transition between two states, for example, a transition between a current state of the state machine FSM and a next state of the state machine FSM, the circuit FSM receives an input signal sig-in. The signal sig-in indicates whether a condition for a signal of the converter 1 is verified. For example, the signal sig-in indicates whether the current flowing in the inductor L has a zero value, whether the output voltage Vout is greater than or less than at least one threshold value, etc.

[0017] Typically, when the circuit FSM is implemented synchronously, that is, when the current state of the state machine FSM and the outputs cmdH and cmdL of the state machine FSM are updated at the frequency of a periodic clock signal, the circuit FSM includes: a state register having an output indicating the current state of the state machine FSM and an input for receiving an indication of the next state of the state machine FSM; and a combinational circuit that takes the signal sig-in and the output of the state register as inputs and supplies an indication of the next state of the state machine.

[0018] In this case, the state register of the state machine FSM is updated at each cycle of the periodic clock signal.

[0019] As an example, the outputs cmdH and cmdL are determined based on an indication of the current state of the state machine FSM, i.e., based on the output of the state register. As an alternative example, the circuit FSM further comprises: an output register for supplying the outputs cmdH and cmdL and an input for receiving an indication of the next value of the outputs cmdH and cmdL; and a combinational circuit that receives an indication of the current state of the state machine FSM and a signal sig-in, and supplies an indication of the next value of the outputs cmdH and cmdL.

[0020] In this alternative example, the output register and the status register are updated simultaneously during each cycle of the periodic clock signal.

[0021] However, a disadvantage of the synchronous implementation of the circuit FSM is that the frequency of the periodic clock signal must be much greater than the switching frequency or control frequency of the switches LSS and HSS, for example at least 100 times greater, in order to regulate the value of the voltage Vout in a sufficiently accurate manner. This entails various problems. For example, this makes the converter 1 unsuitable for applications in which it is desired to minimize power consumption.

[0022] In order to overcome the drawbacks of synchronously implemented finite state machines, it has been provided to implement purely asynchronous finite state machines, ie without a clock signal. These purely asynchronous state machines are then implemented with the aid of dedicated electronic components such as Muller cells.

[0023] However, the design of pure asynchronous state machines requires specific development tools that are generally incompatible with tools for developing digital circuits rated by periodic clock signals. In addition, pure asynchronous state machines are generally incompatible with digital circuits rated by periodic clock signals.

[0024] In order to overcome the inherent disadvantages of synchronously implemented finite state machines and purely asynchronous finite state machines, a method for implementing a global asynchronous-locally synchronous (GALS) state machine is also provided.

[0025] The implementation of a GALS-type state machine is similar to the pure synchronous state machine of the above-mentioned alternative example, except that: the GALS-type state machine does not include a periodic clock signal that controls the updating of its state and output registers; the GALS-type state machine includes a circuit for storing its input signals, such that the stored signals are supplied to a combinational circuit that provides an indication of the next state of the state machine and an indication of the next value of the output of the state machine; and the GALS-type state machine includes a local clock generation circuit, which is configured to supply a local clock signal based on the indication of the next state of the state machine and the indication of the current state of the state machine, the local clock signal controlling the storage of the input signals of the state machine and controlling the updating of the state and output registers (only when available), whereby the local clock signal is not periodic.

[0026] In a GALS-type state machine, registers and storage circuits are implemented by common synchronous components such as flip-flops or latches.

[0027] However, GALS type state machines are typically slow because the maximum frequency that the local clock signal can reach is limited by the metastable state resolution time in the input signal storage circuit and the calculation time of the next state indication of the state machine.

[0028] There is a need to overcome all or some of the disadvantages of known finite state machines for switching converters. Utility Model Content

[0029] One aspect of the present disclosure provides an asynchronous finite state machine for controlling a high-side switch and a low-side switch of a switching converter, the state machine comprising a plurality of states connected together by transitions, the asynchronous finite state machine comprising: a trigger for implementing each transition, wherein each trigger has an output terminal, a data input terminal and a control input terminal, the output terminal being configured to supply a bit representing a state of the asynchronous finite state machine, the state being an arrival state of a transition implemented by the trigger, the data input terminal being configured to receive a bit representing an initial state of a transition implemented by the trigger, and the control input terminal being configured to receive a first binary signal dedicated to the trigger; A combinational circuit, the first combinational circuit being configured to supply, for each transition, a second binary signal corresponding to the transition and indicating whether the transition needs to be implemented, based on an input signal of the asynchronous finite state machine and a bit supplied by an output terminal of the trigger; and a second circuit, the second circuit being configured to generate, based on the second binary signal, a pulse of the first binary signal dedicated to a trigger that implements the transition and a pulse of the first binary signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger that implements the transition each time a transition is requested to be implemented and in the absence of a pulse of the first binary signal.

[0030] According to at least one embodiment of the present disclosure, each flip-flop is configured such that the start of each pulse of the first binary signal dedicated to the flip-flop causes an update of the flip-flop.

[0031] According to at least one embodiment of the present disclosure, the second circuit is configured to, each time a request is made to implement a transition and in the absence of a pulse of the first binary signal, generate only a pulse of the first binary signal for a trigger dedicated to implementing the transition and a pulse of the first binary signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger implementing the transition.

[0032] According to at least one embodiment of the present disclosure, the first combinational circuit does not include a state register and does not include a circuit for storing an input signal of the asynchronous finite state machine.

[0033] According to at least one embodiment of the present disclosure, the asynchronous finite state machine includes: at least one pair of transitions having the same initial state; and for each pair of transitions having the same initial state, the first combinational circuit includes a mutually exclusive circuit, which is configured to supply a second binary signal indicating whether a first transition in the pair of transitions needs to be implemented and a second binary signal indicating whether a second transition in the pair of transitions needs to be implemented based on a plurality of the input signals of the asynchronous finite state machine, so that only one of the second binary signals indicates that a transition corresponding to the second binary signal is required.

[0034] According to at least one embodiment of the present disclosure, the second circuit: for each transition includes a pulse generator associated with the transition, the pulse generator being configured to: receive a second binary signal corresponding to the transition; and generate an output pulse each time a request is made to implement the transition and in the absence of a pulse of the first binary signal; and includes a third combination circuit, the third combination circuit being configured to supply the first binary signal based on the output pulse of the pulse generator.

[0035] According to at least one embodiment of the present disclosure, the third combinational circuit is also configured to transmit a locked binary signal at a first level only when at least one of the first binary signals exhibits a pulse, otherwise transmits a locked binary signal at a second level, and each pulse generator is configured not to transmit an output pulse when the locked binary signal is at the first level.

[0036] In accordance with at least one embodiment of the present disclosure, each pulse generator is configured such that, at each output pulse transmitted by the pulse generator, switching of an output terminal of a flip-flop that implements a transition associated with the generator ends the output pulse.

[0037] According to at least one embodiment of the present disclosure, each pulse generator is configured to cause, at each output pulse transmitted by the pulse generator, switching of a data input of a flip-flop implementing a transition associated with the generator to end the output pulse.

[0038] According to at least one embodiment of the present disclosure, the second circuit is configured such that each pulse of the first binary signal has the same constant duration determined by a hold time of the flip-flop.

[0039] According to at least one embodiment of the present disclosure, the second circuit is configured so that each time a request is made to implement a transition, the second circuit generates a pulse of the first binary signal dedicated to a trigger that implements the transition and a pulse of the first binary signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger that implements the transition, and the switching of the output terminal of the trigger that implements the transition ends the pulse.

[0040] According to at least one embodiment of the present disclosure, the second circuit is configured so that each time a request is made to implement a transition, the second circuit generates a pulse of the first binary signal dedicated to a trigger that implements the transition and a pulse of the first binary signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger that implements the transition, and the switching of the data input terminal of the trigger that implements the transition ends the pulse.

[0041] According to at least one embodiment of the present disclosure, the asynchronous finite state machine is configured to implement: a first stage, in which the high-voltage side switch of the switching converter is controlled to be in an on state and the low-voltage side switch of the converter is controlled to be in an off state; a second stage, in which the low-voltage side switch is controlled to be in an on state and the high-voltage side switch is controlled to be in an off state respectively; and a third stage, in which the third stage controls the two switches to be in an off state, and wherein, for each state, the asynchronous finite state machine is configured to implement one of the first stage, the second stage and the third stage.

[0042] According to at least one embodiment of the present disclosure, the asynchronous finite state machine is configured to control the converter alternately in a continuous conduction mode and a discontinuous conduction mode, the continuous conduction mode including one or more implementations of a continuous process of the second stage, the third stage, and the first stage, and the discontinuous conduction mode including one or more implementations of a continuous process of the second stage and the first stage.

[0043] According to at least one embodiment of the present disclosure, the trigger precisely includes a first trigger, a second trigger, a third trigger and a fourth trigger, and the first trigger, the second trigger, the third trigger and the fourth trigger are configured such that: the data input terminal of the first trigger receives a bit supplied by the output terminal of the second trigger and a bit supplied by the output terminal of the third trigger; the data input terminals of the third trigger and the fourth trigger each receive a bit supplied by the output terminal of the first trigger; and the data input terminal of the second trigger receives a bit supplied by the output terminal of the fourth trigger.

[0044] According to at least one embodiment of the present disclosure, a bit supplied by the output terminal of the second flip-flop and a bit supplied by the output terminal of the third flip-flop represent a first state of the asynchronous finite state machine; a bit supplied by the output terminal of the first flip-flop represents a second state of the asynchronous finite state machine; a bit supplied by the output terminal of the fourth flip-flop represents a third state of the asynchronous finite state machine; and the asynchronous finite state machine is configured to implement the first stage, the second stage, and the third stage in the first state, the second state, and the third state, respectively.

[0045] Another aspect of the present disclosure provides a switching converter, which includes: a high-voltage side switch, which couples a connection node to a node configured to receive a power supply potential; a low-voltage side switch, which couples the connection node to a node configured to receive a reference potential; an inductor, which couples the connection node to an output end of the converter; and an asynchronous finite state machine according to one aspect of the present disclosure, which is used to control the high-voltage side switch and the low-voltage side switch of the switching converter.

[0046] Yet another aspect of the present disclosure provides an asynchronous finite state machine having a plurality of states connected together by transitions, the asynchronous finite state machine comprising: a trigger for each transition, wherein the output of each trigger supplies a bit representing an arrival state of the asynchronous finite state machine, wherein a data input receives a bit representing an initial state of the transition, and a control input receives a first binary signal dedicated to the trigger; a first combinational circuit, the first combinational circuit being configured to process the input signal of the asynchronous finite state machine, and to process the bit at the output of the trigger to generate, for each transition, a second binary signal indicating the implementation of the transition; and a second circuit, the second circuit being configured to process the second binary signal, and for each implementation of the transition, to generate a pulse of the first binary signal dedicated to the trigger implementing the transition, and to generate a pulse of the first binary signal dedicated to each trigger whose output supplies a bit to the data input of the trigger implementing the transition.

[0047] According to at least one embodiment of the present disclosure, when at least one pair of transitions have the same initial state, the first combinational circuit includes a mutual exclusion circuit, which is configured to supply a second binary signal for controlling only one trigger associated with the pair of transitions, and the second binary signal is provided to indicate the implementation of the transition.

[0048] According to at least one embodiment of the present disclosure, the second circuit: for each transition, includes a pulse generator associated with the transition, the pulse generator being configured to: receive a second binary signal corresponding to the transition; and generate an output pulse each time a request is made to implement the transition; and includes a third combination circuit, the third combination circuit being configured to supply the first binary signal based on the output pulse of the pulse generator.

[0049] According to at least one embodiment of the present disclosure, the second circuit is configured such that each pulse of the first binary signal has the same constant duration determined by a hold time of the flip-flop.

[0050] Yet another aspect of the present disclosure provides a switch circuit, comprising: a plurality of transistor switches; and an asynchronous finite state machine according to one aspect of the present disclosure, wherein the asynchronous finite state machine is configured to control the plurality of transistor switches.

[0051] One embodiment provides an asynchronous finite state machine that is not implemented by a dedicated asynchronous component and / or by using a dedicated asynchronous development tool.

[0052] For example, one embodiment provides an asynchronous finite state machine that does not include a state register and, in turn, a combinational circuit that provides an indication of the next state of the state machine. This enables the asynchronous state machine to operate faster than a GALS-type state machine or an asynchronous state machine implemented by a dedicated asynchronous component, for example.

[0053] For example, one embodiment provides an asynchronous finite state machine with reduced power consumption compared to a synchronous state machine.

[0054] One embodiment provides an asynchronous finite state machine for controlling a high-side switch and a low-side switch of a switching converter, wherein: the state machine includes a plurality of states connected together by transitions, each transition being implemented by a D flip-flop; each flip-flop has an output terminal, a data input terminal, and a control input terminal, the output terminal being configured to supply a bit representing a state of the state machine, the state being an arrival state of a transition implemented by the flip-flop, the data input terminal being configured to receive a bit representing an initial state of a transition implemented by the flip-flop, and the control input terminal being configured to receive a first binary pulse signal dedicated to the flip-flop; a first combinational circuit, the first combinational circuit being configured to supply, for each transition, a second binary signal corresponding to the transition and indicating whether the transition needs to be implemented, based on an input signal of the state machine and a bit supplied by the output terminal of the flip-flop; and a second circuit, the second circuit being configured to generate, based on the second signal, a pulse of the first signal dedicated to the flip-flop implementing the transition and a pulse of the first signal dedicated to each flip-flop whose output terminal is configured to supply a bit to the data input terminal of the flip-flop implementing the transition, each time a transition is requested and in the absence of a pulse of the first signal.

[0055] According to one embodiment, each flip-flop is configured such that the start of each pulse of the first signal dedicated to the flip-flop causes an update of the flip-flop.

[0056] According to one embodiment, the second circuit is configured to, each time a request is made to implement a transition and in the absence of a pulse of the first signal, generate a pulse of the first signal only for a trigger dedicated to implementing the transition and a pulse of the first signal dedicated to each trigger whose output is configured to supply a bit to a data input of the trigger implementing the transition.

[0057] According to one embodiment, the first combinatorial circuit does not include a state register and does not include a circuit for storing an input signal of the state machine.

[0058] According to one embodiment, the state machine includes: at least one pair of transitions having the same initial state; and for each pair of transitions having the same initial state, the first combinational circuit includes a mutually exclusive circuit, which is configured to supply a second binary signal indicating whether a first transition in the pair of transitions needs to be implemented and a second binary signal indicating whether a second transition in the pair of transitions needs to be implemented based on a plurality of the input signals of the state machine, so that only one of the second signals indicates that a transition corresponding to the second signal is required.

[0059] According to one embodiment, the second circuit includes: for each transition, a pulse generator associated with the transition, and the pulse generator is configured to: receive a second signal corresponding to the transition; and generate an output pulse each time a request is made to implement the transition and in the absence of a pulse of the first signal; and a third combination circuit, which is configured to transmit the first signal based on the output pulse of the generator.

[0060] According to one embodiment, the third combination circuit is also configured to supply a binary signal at a first level only when at least one of the first signals exhibits a pulse, and otherwise to supply a binary signal at a second level, and each pulse generator is configured not to transmit an output pulse when the binary signal is at the first level.

[0061] According to one embodiment, each pulse generator is configured to, at each output pulse transmitted by the pulse generator, cause switching of an output terminal of a trigger implementing a transition associated with the generator and / or switching of a data input terminal of a trigger implementing a transition associated with the generator to end the output pulse.

[0062] According to one embodiment, the second circuit is configured such that each pulse of the first signal has the same constant duration determined by a hold time of the flip-flop.

[0063] According to one embodiment, the second circuit is configured so that each time a request is made to implement a transition, the second circuit generates a pulse of the first signal dedicated to a trigger that implements the transition and a pulse of the first signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger that implements the transition, and the switching of the output terminal of the trigger that implements the transition and / or the switching of the data input terminal of the trigger that implements the transition ends the pulse.

[0064] According to one embodiment, the state machine is configured to implement: a first stage, in which the high-voltage side switch of the switching converter is controlled to be in an on state and the low-voltage side switch of the converter is controlled to be in an off state; a second stage, in which the low-voltage side switch is controlled to be in an on state and the high-voltage side switch is controlled to be in an off state respectively; and a third stage, in which the two switches are controlled to be in an off state, and for each state, the state machine is configured to implement one of the first stage, the second stage and the third stage.

[0065] According to one embodiment, the state machine is configured to control the converter alternately in a continuous conduction mode and a discontinuous conduction mode, the continuous conduction mode comprising one or more implementations of a continuous process of the second phase, the third phase and the first phase, and the discontinuous conduction mode comprising one or more implementations of a continuous process of the second phase and the first phase.

[0066] According to one embodiment, the trigger precisely includes a first trigger, a second trigger, a third trigger and a fourth trigger, and the first trigger, the second trigger, the third trigger and the fourth trigger are configured so that: the data input terminal of the first trigger receives a bit supplied by the output terminal of the second trigger and a bit supplied by the output terminal of the third trigger; the data input terminals of the third trigger and the fourth trigger each receive a bit supplied by the output terminal of the first trigger; and the data input terminal of the second trigger receives a bit supplied by the output terminal of the fourth trigger.

[0067] According to one embodiment: the bit supplied by the output terminal of the second flip-flop and the bit supplied by the output terminal of the third flip-flop represent the first state of the state machine; the bit supplied by the output terminal of the first flip-flop represents the second state of the state machine; the bit supplied by the output terminal of the fourth flip-flop represents the third state of the state machine; and the state machine is configured to implement the first stage, the second stage and the third stage in the first state, the second state and the third state, respectively.

[0068] One embodiment provides a switching converter, comprising: a high-side switch, which couples a connection node to a node configured to receive a power supply potential; a low-side switch, which couples the connection node to a node configured to receive a reference potential; an inductor, which couples the connection node to an output terminal of the converter; and a state machine such as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The above features and advantages and others will be described in detail in the following remaining disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0070] Previously described Figure 1 An example of a switching converter is shown, the switching converter including a finite state machine for controlling a high-side switch and a low-side switch of the converter;

[0071] Figure 2 An example of an embodiment of an asynchronous finite state machine for a switching converter is shown in the form of a state diagram;

[0072] Figure 3 An example of an embodiment of an asynchronous finite state machine for a switching converter is shown in circuit form;

[0073] Figure 4 The timing diagram shows Figure 3 Examples of operating modes of the state machine;

[0074] Figure 5 Shown in box form Figure 3 An example of a detailed embodiment of the circuit of the state machine; and

[0075] Figure 6 Shown in box form Figure 3 An example of a detailed embodiment of another circuit of a state machine. DETAILED DESCRIPTION

[0076] In the various drawings, similar features have been designated by similar reference symbols. In particular, common structural and / or functional features between the various embodiments may have the same reference symbols and may have the same structure, dimensions, and material properties.

[0077] For the sake of clarity, only the steps and elements useful for understanding the described embodiments are illustrated and described in detail. In particular, various common applications in which a switching converter is implemented and includes a state machine controlling its cut-off switch have not been described, and the described embodiments and variants are compatible with these common applications.

[0078] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0079] In the following description, when referring to terms such as "front", "back", "top", "bottom", "left", "right", or terms such as "above", "below", "upper", "lower", or terms such as "horizontal", "vertical", etc., it refers to the orientation in the drawing, unless otherwise specified.

[0080] Unless otherwise indicated, the expressions "about", "substantially", "substantially" and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0081] An asynchronous finite state machine based on D flip-flops is provided herein, wherein each transition between two states of the state machine is implemented by a D flip-flop or corresponds to a D flip-flop.

[0082] Each D flip-flop supplies a bit representing or corresponding to a state of the state machine, where multiple bits can correspond to the same state. For example, a bit corresponding to a transition between two states of the state machine supplied by the flip-flop indicates the arrival state of the transition. For example, if the bit corresponding to a given state of the state machine is active, this indicates that the current state of the state machine is the given state.

[0083] Each D flip-flop has a data input for receiving a bit representing the initial state of the transition, which in turn is an output bit of another D flip-flop of the state machine.

[0084] According to an embodiment in which the state machine includes a first transition whose initial state corresponds to the arrival states of the other two transitions, the flip-flop implementing the first transition receives, on its data input, an output bit of the flip-flop corresponding to one of the two transitions and an output bit of the flip-flop corresponding to the other of the two transitions, or in other words, a combination of the two bits. More specifically, the two output bits of the two flip-flops corresponding to the two transitions are supplied to the data input of the flip-flop corresponding to the first transition, so that if one of the two bits is in an active state to indicate the current state of the state machine, the input of the flip-flop corresponding to the first transition is in an active state.

[0085] In addition, in order to control the implementation of the transition between the two states, the state machine includes a circuit configured to transmit a pulse signal for controlling each flip-flop to each flip-flop. When a transition between the two states is required, or in other words, when the condition for implementing the transition is verified and none of the control signals has shown a pulse, the circuit generates a pulse of a signal for controlling the flip-flop that implements the transition, so that the flip-flop updates its output terminal based on its data input terminal, for example, at the moment of the first edge of the pulse. In addition, the circuit also simultaneously generates a pulse of a signal for controlling each D flip-flop whose output bit is supplied to the input terminal of the D flip-flop that implements the transition.

[0086] For each transition, the corresponding output signal of the combinatorial circuit of the state machine indicates whether a transition is needed. The combinatorial circuit transmits its output signal based only on the input signal of the state machine and the output bit of the flip-flop that implements the state machine transition. In fact, for a transition to be implemented, it must be confirmed that the state machine is effectively in the initial state of the transition.

[0087] Therefore, the provided state machine is implemented based on common components of synchronous circuits, in particular based on synchronous D flip-flops, and is not implemented using dedicated asynchronous components.

[0088] The provided state machine is also faster than an equivalent finite GALS type state machine, in which the calculation of the next state takes time, while such calculation is not implemented in the provided state machine.

[0089] In addition, the state machine provided generates switching only when necessary, which reduces its power consumption relative to the synchronous state machine. In particular, during the transition between two states, the state machine does not transmit pulses to every control signal of the flip-flop, but only transmits pulses to the control signals of some flip-flops.

[0090] Furthermore, in contrast to a GALS-type state machine, the provided state machine does not need to store its input signals. This enables the provided state machine to be faster due to the fact that it does not have to provide a metastable resolution time for each storage of the state machine's input signals as is the case with a GALS-type state machine.

[0091] According to one embodiment, a finite state machine is provided that includes a pair of transitions having the same initial state. In such an embodiment, then, the combinational circuit that transmits a signal indicating whether a first transition in a pair of transitions needs to be implemented and a signal indicating whether a second transition in a pair of transitions needs to be implemented includes a mutually exclusive circuit. The mutually exclusive circuit is configured to supply the two signals so that only one of the two signals indicates that the corresponding transition is needed. This makes it possible to avoid circuits for generating control signals for controlling flip-flops that implement the two transitions simultaneously.

[0092] Figure 2 A switching converter (e.g. Figure 1 An example of an embodiment of an asynchronous finite state machine aFSM of a converter 1).

[0093] According to one embodiment, the asynchronous finite state machine aFSM provided herein is implemented based on three states OFF, HS and LS, and preferably is implemented based only on these three states OFF, HS and LS.

[0094] State HS corresponds to the first control stage in which the state machine controls the switch HSS to be in the on state and controls the switch LSS to be in the off state. In other words, in state HSS, the state machine aFSM is configured to implement the first control stage.

[0095] State LS corresponds to the second control stage in which the state machine controls the switch LSS to be in the on state and controls the switch HSS to be in the off state. In other words, in state LSS, the state machine aFSM is configured to implement the second control stage.

[0096] The state OFF corresponds to the third control phase in which the state machine controls the switches HSS and LSS of the converter 1 to be in the off state. In other words, in the state OFF, the state machine aFSM is configured to implement the third control phase.

[0097] Thus, for each of its states, the state machine aFSM implements one of the first control phase, the second control phase and the third control phase.

[0098] According to one embodiment, Figure 2 As shown in the figure, the state machine aFSM includes the three states OFF, HS and LS.

[0099] According to one embodiment, Figure 2 In the example of , the state machine aFSM is configured to control the converter 1 , ie, to control the switches HSS and LSS of the converter 1 , alternately according to a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).

[0100] In continuous conduction mode, the state machine aFSM is configured to alternate two control phases, i.e., the first control phase and the second control phase as previously described. In other words, the state machine aFSM controls the converter by implementing one or more continuous processes in the first control phase and the second control phase as described above (preferably, in this order).

[0101] In the discontinuous conduction mode, the state machine aFSM is configured to alternate three control phases, i.e., the first control phase, the second control phase, and the third control phase as previously described. In other words, the state machine aFSM controls the converter by implementing one or more continuous processes (preferably, in this order) in the first control phase, the second control phase, and the third control phase as described above.

[0102] exist Figure 2 In the state machine aFSM of the example, states OFF, HS and LS are coupled together by transitions OFF2HS, HS2LS, LS2HS and LS2OFF, each transition coupling two states, namely, an initial state of the transition and an arrival state of the transition.

[0103] More specifically, in Figure 2In the example of , transition OFF2HS couples state OFF to state HS, state OFF corresponds to the initial state of transition OFF2HS, and state HS corresponds to its arrived state. Transition HS2LS couples state HS to state LS, state HS corresponds to the initial state of transition HS2LS, and state LS corresponds to its arrived state. Transition LS2HS couples state LS to state HS, state LS corresponds to the initial state of transition LS2HS, and state HS corresponds to its arrived state. Transition LS2OFF couples state LS to state OFF, state LS corresponds to the initial state of transition LS2OFF, and state OFF corresponds to its arrived state.

[0104] When the state machine aFSM implements one or more continuous processes of transitions HS2LS, LS2OFF and OFF2HS, then the state machine aFSM implements one or more continuous processes of states HS, LS and OFF, i.e., one or more continuous processes of the first control phase, the second control phase and the third control phase described above. Then, the state machine aFSM controls the converter in discontinuous conduction mode.

[0105] When the state machine aFSM implements one or more continuous processes of the transitions HS2LS and LS2HS, then the state machine aFSM implements one or more continuous processes of the states HS and LS, i.e., one or more continuous processes of the first control phase and the second control phase described above. Then, the state machine aFSM controls the converter in continuous conduction mode.

[0106] In practice, when the current state of the state machine aFSM is the initial state of the transition and the input signal of the state machine aFSM indicates that the transition needs to be implemented, or in other words, indicates that the condition for implementing the transition is verified, the state machine aFSM implements the transition.

[0107] exist Figure 2 In the example of , the choice of the state machine aFSM to control the converter 1 according to the continuous conduction mode or the discontinuous conduction mode is determined by the choice of which of the transitions LS2OFF and LS2HS is implemented when the current state of the state machine is the state LS. In fact, if the transition LS2OFF is implemented and the transition LS2HS is not implemented, the state machine aFSM controls the converter in the discontinuous mode, at least until its current state is again the state LS. On the contrary, if the transition LS2HS is implemented and the transition LS2OFF is not implemented, the state machine aFSM controls the converter in the continuous mode, at least until its current state is again the state LS.

[0108] According to one embodiment, when the state machine aFSM includes two transitions having the same initial state, such as the two transitions having the same initial state LS( Figure 2In the example of the transitions LS2OFF and LS2HS, a mutually exclusive function and / or circuit configured to enable only one of the two transitions to be effectively implemented (i.e., to prevent the two transitions from being implemented at the same time) is provided. For example, the state machine aFSM is implemented by a circuit aFSM including a combinational circuit, wherein the combinational circuit transmits such signals, each of which indicates whether the transition needs to be implemented for the corresponding transition, or in other words, whether the condition of the transition passes verification. In this case, the combinational circuit includes a mutually exclusive circuit to transmit a signal indicating whether the transition LS2HS needs to be implemented and a signal indicating whether the transition LS2OFF needs to be implemented, so that only one of the two signals indicates that the corresponding transition needs to be implemented.

[0109] Although a specific example of an asynchronous finite state machine aFSM has been described herein, a person skilled in the art will be able to provide other state machines implemented with at least two of the three states HS, LS and OFF (preferably with the three states HS, LS and OFF), including, for example, Figure 2 The transformations described are different transformations.

[0110] Figure 3 An example of an embodiment of an asynchronous finite state machine for a switching converter is shown in circuit form. More specifically, Figure 3 Shown with Figure 2 An example of an embodiment of a circuit aFSM corresponding to the state machine aFSM of Figure 1 Converter 1.

[0111] As indicated previously, the state machine aFSM ( Figure 2 ) is implemented by a D flip-flop in the corresponding circuit aFSM. Figure 3 In the example of , the circuit aFSM includes a flip-flop FF-OFF2HS that implements a transition OFF2HS, a flip-flop FF-HS2LS that implements a transition HS2LS, a flip-flop FF-LS2HS that implements a transition LS2HS, and a flip-flop FF-LS2OFF that implements a transition LS2OFF.

[0112] Each flip-flop includes a data input terminal D, a control (or synchronization) input terminal C, and an output terminal Q. The operation of a synchronous D flip-flop is well known and will not be described in detail here.

[0113] The flip-flop FF-HS2LS supplies bit b1, the flip-flop FF-OFF2HS supplies bit b2, the flip-flop FF-LS2HS supplies bit b3, and the flip-flop FF-LS2OFF supplies bit b4.

[0114] The arrival state of transition HS2LS is state LS ( Figure 2), so the output bit b1 of the flip-flop FF-HS2LS corresponding to the transition represents the arrival state HS of the transition.

[0115] Similarly, the arrival state of transition HS2LS is state LS ( Figure 2 ), therefore the output bit b4 of the flip-flop FF-LS2OFF corresponding to the transition indicates the arrival state OFF of the transition.

[0116] In addition, the arrival state of transition OFF2HS and transition LS2HS is the same state HS ( Figure 2 ), therefore, the output bits b2 and b3 of the respective flip-flops FF-OFF2HS and FF-LS2HS corresponding to the two transitions respectively represent the arrival state HS of the two transitions.

[0117] Therefore, for the case where the current state of the state machine is state HS, it is sufficient that one of bits b2 and b3 is active, thereby indicating that the state corresponding to this bit is the current state of the state machine aFSM. In other words, state HS corresponds to the combination of bits b2 and b3, for example, corresponds to a bit determined by the combination of bits b2 and b3.

[0118] In addition, since the state HS is the initial state corresponding to the transition HS2LS of the flip-flop FF-HS2LS, the data input terminal D of the flip-flop FF-HS2LS receives two bits b2 and b3. More specifically, the D input terminal of the flip-flop FF-HS2LS receives a bit whose active or inactive state is determined by the state of each of the bits b2 and b3, so that once one of the bits b2 and b3 is in an active state, the bit received by the D input terminal of the flip-flop FF-HS2LS is in an active state. In other words, the flip-flop FF-HS2LS receives a bit determined by the combination of bits b2 and b3. As an example, when the active state of bits b2 and b3 corresponds to a high level, the D input terminal of the flip-flop FF-HS2LS receives a bit corresponding to the output of the logic gate 300, which implements the OR logic function between the bits b2 and b3 received on its input terminal. When the active state of one and / or the other of the bits b2 and b3 corresponds to a low level, those skilled in the art will be able to modify the logic function implemented by the gate 300.

[0119] The C control input terminal of the flip-flop FF-HS2LS receives the control signal CK1 dedicated to the flip-flop FF-HS2LS, and the C input terminals of the flip-flops FF-LS2OFF, FF-LS2HS and FF-OFF2HS receive the corresponding control signals CK2, CK3 and CK4 dedicated to the corresponding flip-flops FF-LS2OFF, FF-LS2HS and FF-OFF2HS. The control signals CK1, CK2, CK3 and CK4 are binary pulse signals, that is, binary signals that exhibit pulses.

[0120] For example, for each of the signals CK1, CK2, CK3, and CK4, a pulse of the signal corresponds to a switch from the low state of the signal to its high state, followed by a switch from the high state to the low state. The switch from the low state to the high state marks the beginning of the pulse, and the switch from the high state to the low state marks the end of the pulse. However, in other examples, the opposite may be true.

[0121] The C inputs of the flip-flops FF-HS2LS, FF-OFF2HS, FF-LS2HS, and FF-LS2OFF respond to edges marking the start of pulses of the corresponding signals CK1, CK2, CK3, and CK4, for example, to rising edges of these signals CK1, CK2, CK3, and CK4 when the pulses each correspond to a high state of the signal. In other words, when the flip-flops FF-HS2LS, FF-OFF2HS, FF-LS2HS, and FF-LS2OFF receive a pulse of the signal CK1, CK2, CK3, or CK4, respectively, the start of the pulse causes the flip-flop to be updated, that is, the flip-flop updates its output based on its data input, and maintains the state of its output until the next update of the flip-flop.

[0122] The circuit aFSM also includes a combinational circuit C1. The circuit C1 receives the input signal sig-in of the state machine aFSM and the bits b1 to b4 of the output end of the flip-flop that implements the transition of the state machine aFSM. The circuit C1 is configured to supply a binary signal indicating whether the transition needs to be implemented for each transition (and thus for each flip-flop) based only on the input signal sig-in and the bits b1 to b4. For example, for each transition, if the transition needs to be implemented, the corresponding binary signal transmitted by the circuit C1 is at a first level, otherwise it is at a second level. The advantage of the circuit C1 is that it does not include a state register and a circuit for storing the input signal sig-in of the state machine.

[0123] More specifically, in Figure 3 In the example of , the circuit C1 supplies signals R1 , R2 , R3 and R4 indicating whether for each of the respective transitions HS2LS, OFF2HS, LS2HS and LS2OFF a transition needs to be implemented.

[0124] According to an embodiment where the two transitions have the same initial state, such as the two transitions implemented by flip-flops FF-LS2OFF and FF-LS2HS have the same initial state HS represented by bit b1. Figure 3 In the example of , the circuit C1 is configured so that only one of the signal R3 indicating whether the transition LS2HS needs to be implemented and the signal R4 indicating whether the transition LS2HS needs to be implemented can effectively indicate that the transition corresponding to the signal needs to be implemented. As an example, then, the circuit C1 implements the mutual exclusion function between the signals R3 and R4, for example, by means of a mutual exclusion circuit.

[0125] Although this has been illustrated for transitions LS2OFF and LS2HS having the same initial state HS, this remains true for any combination of at least two transitions having the same initial state.

[0126] The circuit aFSM also includes a circuit C2. The circuit C2 receives the output signals R1, R2, R3 and R4 of the circuit C1. The circuit C2 is configured to generate the signals CK1, CK2, CK3 and CK4 based on the signals R1, R2, R3 and R4. More specifically, at each request to implement a transition and in the absence of a pulse of the signals CK1, CK2, CK3 and CK4, that is, when none of the signals CK1, CK2, CK3 and CK4 exhibits a pulse, the circuit C2 is configured to generate a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop that implements the transition, and in addition, to generate a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output terminal supplies a bit to the data input terminal of the flip-flop that implements the transition.

[0127] For example, as an example, when the signal R1 indicates that the transition HS2LS needs to be implemented and none of the signals CK1, CK2, CK3, and CK4 exhibits a pulse, the circuit C2 is configured to generate a pulse of the signal CK1 for controlling the flip-flop FF-HS2LS that implements the transition HS2LS. In this example, the circuit C2 is also configured to generate a pulse of the signal CK2 and a pulse of the signal CK3 simultaneously with the pulse of the signal CK1 due to the fact that both the output bit b2 of the flip-flop FF-OFF2HS and the output bit b3 of the flip-flop FF-LS2HS are supplied to the D input terminal of the flip-flop FF-HS2LS that implements the transition HS2LS.

[0128] According to one embodiment, at each request to implement a transition and in the absence of a pulse of the signals CK1, CK2, CK3 and CK4, the circuit C2 is more particularly configured to generate only a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition and a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output supplies a bit to the data input of the flip-flop implementing the transition. This makes it possible to avoid any useless switching of the signals CK1, CK2, CK3 and CK4 that is not necessary for controlling the flip-flop in order to implement the transition at each implementation of the transition.

[0129] According to one embodiment, the duration of each pulse of each of the signals CK1, CK2, CK3 and CK4 is fixed and constant.The pulse duration is then preferably determined by the holding time of the D flip-flop, for example such that the pulse duration is equal to or greater than the holding time.

[0130] According to an alternative embodiment, at each request to implement a transition, after generating a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition, and simultaneously generating a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output supplies a bit to the D input of the flip-flop implementing the transition, the circuit C2 is further configured so that the switching of the output of the flip-flop implementing the transition ends these pulses. Thus, the generated pulses can be shorter than if their duration is fixed. For example, as an example, when the circuit C2 receives the signal R2 indicating that the transition OFF2HS needs to be implemented, the circuit generates a pulse of the signal CK2, and simultaneously generates a pulse of the signal CK4, and once the output of the flip-flop FF-OFF2HS switches, the circuit C2 ends these pulses.

[0131] According to another alternative embodiment, at each request to implement a transition, after generating a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition, and simultaneously generating a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output supplies a bit to the D input of the flip-flop implementing the transition, the circuit C2 is further configured so that the switching of the input of the flip-flop implementing the transition ends these pulses. Thus, the generated pulses can be shorter than if their duration is fixed. For example, as an example, when the circuit C2 receives the signal R2 indicating that the transition OFF2HS needs to be implemented, the circuit generates a pulse of the signal CK2 and simultaneously generates a pulse of the signal CK4, and once the input bit b4 of the flip-flop FF-OFF2HS switches, the circuit C2 ends these pulses.

[0132] According to yet another alternative embodiment, at each request to implement a transition, after generating a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition, and simultaneously generating a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output supplies a bit to the D input of the flip-flop implementing the transition, the circuit C2 is further configured so that the combination of the switching of the input of the flip-flop implementing the transition and the switching of the output of the flip-flop ends these pulses. Thus, the generated pulses can be shorter than if their duration is fixed. For example, as an example, when the circuit C2 receives the signal R2 indicating that the transition OFF2HS needs to be implemented, the circuit generates a pulse of the signal CK2 and simultaneously generates a pulse of the signal CK4, and once both the input bit b4 of the flip-flop FF-OFF2HS and the output bit b2 of the flip-flop FF-OFFHS are switched, the circuit C2 ends these pulses.

[0133] Compared to the above-mentioned embodiments, the above last embodiment in which the pulse duration is determined by a combination of switching of the input terminal of the trigger that implements the transition and switching of the output terminal of the trigger makes it possible to remove the criterion that the switching time of the circuit C2 for confirming that the signals CK1 to CK4 is slower than the switching time of the trigger, for example, to remove the criterion that the width of each pulse of the confirmation signals CK1 to CK4 is 20% to 30% greater than the minimum duration that the trigger can withstand.

[0134] Figure 4 The timing diagram shows Figure 3 An example of an operating mode of the state machine or circuit aFSM of the example illustrated in FIG. More specifically, Figure 4 The diagram shows the signals b1, CK1, b2, CK2, b4, CK3, b4, CK4 and the current state (refer to Figure 4 The “state” in ( ) changes according to time t.

[0135] In the illustrated example, each of bits b1 to b4 is active in a high state (or high level) and inactive in a low state (or low level), and in addition, each pulse of each of signals CK1 to CK4 corresponds to a high state (or high level) of the signal. However, those skilled in the art will be able to apply the following description to examples in which at least one of bits b1 to b4 is active in a low level and / or at least one of signals CK1 to CK4 exhibits a pulse corresponding to a low level of the signal.

[0136] Additionally, in the illustrated example, the pulses of the signals CK1 to CK2 have a constant duration, although in other examples not illustrated, each pulse has a duration determined by the switching of at least one of the bits b1 to b4, such as for Figure 3Indicated.

[0137] At time t0 , circuit aFSM is in current state LS (bit b1 is active).

[0138] At the next moment t1, signal R3( Figure 4 (not shown) indicates to the circuit C2 that the transition LS2HS needs to be implemented. Since none of the signals CK1 to CK4 exhibits a pulse at time t1, the circuit C2 generates a pulse of the signal CK3 and simultaneously generates a pulse of the signal CK1.

[0139] As a result, bit b3 switches to the active state and bit b1 switches to the inactive state. In other words, the current state of circuit aFSM switches from state LS to state HS.

[0140] Then, at the instant t1 , the circuit aFSM controls the converter in the continuous mode CCM.

[0141] At the next time t2, after the pulses CK1 and CK3 between time t1 and t2 have ended, the signal R1 ( Figure 4 (not shown) indicates to the circuit C2 that the transition HS2LS needs to be implemented. Since none of the signals CK1 to CK4 exhibits a pulse at time t2, the circuit C2 generates a pulse of the signal CK1, a pulse of the signal CK2, and a pulse of the signal CK3.

[0142] As a result, bit b1 switches to the active state and bit b3 switches to the inactive state. In other words, the current state of circuit aFSM switches from state HS to state LS.

[0143] At the next time t3, after the pulses CK1, CK2 and CK3 between time t2 and t3 have ended, the signal R4 ( Figure 4 (not shown) indicates to the circuit C2 that the transition LS2OFF needs to be implemented. Since none of the signals CK1 to CK4 exhibits a pulse at time t3, the circuit C2 generates a pulse of the signal CK4 and simultaneously generates a pulse of the signal CK1.

[0144] As a result, bit b4 switches to the active state and bit b1 switches to the inactive state. In other words, the current state of circuit aFSM switches from state LS to state OFF.

[0145] Therefore, from the instant t3 onwards, the circuit aFSM controls the converter in the discontinuous mode DCM.

[0146] At the next time t4, after the pulses CK1 and CK4 between time t3 and t4 end, the signal R2 ( Figure 4(not shown) indicates to the circuit C2 that the transition OFF2HS needs to be implemented. Since none of the signals CK1 to CK4 exhibits a pulse at time t4, the circuit C2 generates a pulse of the signal CK2 and simultaneously generates a pulse of the signal CK4.

[0147] As a result, bit b2 switches to the active state and bit b4 switches to the inactive state. In other words, the current state of circuit aFSM switches from state OFF to state HS.

[0148] At the next time t5, after the pulses CK2 and CK4 end between time t4 and t5, the signal R1 ( Figure 4 (not shown) indicates to the circuit C2 that the transition HS2LS needs to be implemented. Since none of the signals CK1 to CK4 exhibits a pulse at time t5, the circuit C2 generates a pulse of the signal CK1, and simultaneously generates a pulse of the signal CK2 and a pulse of the signal CK3.

[0149] As a result, bit b1 switches to the active state and bit b2 switches to the inactive state. In other words, the current state of circuit aFSM switches from state HS to state LS.

[0150] What happens at the next successive instants t6, t7 and t8 is the same as what has been described for the corresponding instants t3, t4 and t5.

[0151] At the next time t9, after the pulses CK2 and CK4 end between time t8 and t9, the signal R3 ( Figure 4 (not shown) indicates to the circuit C2 that the transition LS2HS needs to be implemented. Since none of the signals CK1 to CK4 exhibits a pulse at time t9, the circuit C2 generates a pulse of the signal CK3 and simultaneously generates a pulse of the signal CK1.

[0152] As a result, bit b3 switches to the active state and bit b1 switches to the inactive state. In other words, the current state of circuit aFSM switches from state LS to state HS.

[0153] Therefore, from the instant t9, the circuit aFSM controls the converter in the continuous mode CCM.

[0154] Figure 5 Shown in box form Figure 3 An example of a detailed embodiment of the circuit C1 of the state machine aFSM.

[0155] As indicated previously, circuit C1 further comprises a mutual exclusion circuit ME configured to supply a signal R3 indicating whether transition LS2HS needs to be implemented and a signal R4 indicating whether transition LS2OFF needs to be implemented, so that only one of the signals R3 and R4 can indicate that the corresponding transition needs to be implemented.

[0156] exist Figure 5 In the example of , the circuit C1 includes a combinational circuit C3. The circuit C3 receives an input signal sig-in of the circuit C1. The circuit C3 is configured to supply signals R1 and R2 based on the signal sig-in.

[0157] exist Figure 5 In the example of FIG. 4 , the circuit C3 is further configured to supply a signal R3 -int inside the circuit C1 and a signal R4 -int inside the circuit C1 based on the signal sig-in.

[0158] Signal R3-int indicates whether the condition for implementing transition LS2HS is verified without regard to whether the condition for implementing transition LS2OFF is verified. Similarly, signal R4-int indicates whether the condition for implementing transition LS2OFF is verified without regard to whether the condition for implementing transition LS2HS is verified.

[0159] Therefore, the signals R3-int and R4-int can indicate whether the conditions of the transitions LS2HS and LS2OFF are verified at the same time. The circuit ME receives the two signals R3-int and R4-int and supplies the corresponding signals R3 and R4. In particular, when the two signals R3-int and R4-int simultaneously indicate that the conditions of the transitions LS2HS and LS2OFF are verified, the circuit ME supplies the signals R3 and R4 so that only one of these signals indicates to the circuit C2 that the transition corresponding to the signal is verified.

[0160] Figure 6 Shown in box form Figure 3 An example of a detailed embodiment of the circuit C2 of the state machine aFSM.

[0161] exist Figure 6 In the example of , for each transition of the state machine aFSM, the circuit C2 comprises a pulse generator associated with this transition.

[0162] Therefore, in Figure 6 In the example, circuit C2 is for Figure 2 and Figure 3 The circuit of the state machine aFSM described, the circuit C2 includes the transition HS2LS ( Figure 2 ) associated with the pulse generator PG1, and the transition OFF2HS ( Figure 2) associated with the pulse generator PG2, and the transition LS2HS ( Figure 2 ) associated with the pulse generator PG3 and with the transition LS2OFF ( Figure 2 ) associated pulse generator PG4.

[0163] Each pulse generator is configured to receive a signal R1, R2, R3 or R4, wherein the signal R1, R2, R3 or R4 corresponds to a transition associated with the pulse generator, ie, the signal R1, R2, R3 or R4 indicates whether the transition associated with the pulse generator needs to be implemented.

[0164] exist Figure 6 In the example, circuit C2 is for Figure 2 and Figure 3 The circuit of the state machine aFSM is described, so that the pulse generator PG1 receives the signal R1, the pulse generator PG2 receives the signal R2, the pulse generator PG3 receives the signal R3, and the pulse generator PG4 receives the signal R4.

[0165] Each generator PG1, PG2, PG3, PG4 is configured to generate an output pulse only when none of the signals CK1 to CK4 exhibits a pulse, whenever the signal R1, R2, R3, R4 it receives indicates the need to implement a transition corresponding to that signal, that is, whenever the generator receives a request to implement a transition associated with it.

[0166] More specifically, the generators PG1 , PG2 , PG3 and PG4 are configured to supply respective output signals sig1 , sig2 , sig3 and sig4 , and the supply of output pulses by the generators corresponds to the pulses supplying their output signals.

[0167] Circuit C2 includes a combinational circuit C4. Circuit C4 is configured to supply signals CK1 to CK4 based on output pulses sig1 to sig4 of generators PG1 to PG4. Thus, circuit C4 receives signals sig1 to sig4. Implementing circuit C4 to obtain the aforementioned operation is within the capabilities of a person skilled in the art, particularly with respect to supplying signals CK1 to CK4 based on signals sig1 to sig4.

[0168] As Figure 6 In an example not described in detail, in the case where each pulse of each of the signals sig1 to sig4 and CK1 to CK4 corresponds to a high level of the signal, the signal CK3 is generated by the circuit C4 based on the signals sig1 and sig3, and corresponds, for example, to the output signal of a logic OR gate that takes the two signals sig1 and sig3 at its input.

[0169] More generally, the circuit C4 is configured so that, for example, for each pulse generator PG1 to PG4, each pulse of the output signal of the generator receives a synchronization pulse of the same duration as the signal CK1, CK2, CK3 or CK4 of a trigger dedicated to implementing the transition associated with the pulse generator, and further receives a synchronization pulse of the same duration as the signal CK1, CK2, CK3 or CK4 of each trigger dedicated to supplying a bit at its output to an input terminal implementing the transition associated with the pulse generator.

[0170] In other words, the duration of each pulse of each signal CK1, CK2, CK3, CK4 is set by, or is equal to, the duration of the pulse of the signal sig1, sig2, sig3 or sig4 that causes it.

[0171] For example, when circuit C4 receives a pulse of signal sig1 , it transmits a pulse of each of signals CK1 , CK2 , and CK3 having the same duration as the pulse of signal sig1 .

[0172] According to one embodiment, in order for each pulse generator PG1 to PG4 not to generate a pulse of its output signal if at least one of the signals CK1 to CK4 has exhibited a pulse, the circuit C4 is also configured to supply a binary signal "locked" indicating whether at least one of the signals CK1 to CK4 exhibits a pulse. More specifically, if at least one of the signals CK1 to CK4 exhibits a pulse, the signal "locked" is in a first binary state or level, otherwise in a second binary state or level. Then, each pulse generator PG1, PG2, PG3, PG4 is configured to transmit a pulse of its output signal sig1, sig2, sig3, sig4 only when the signal "locked" is at its first level when the signal R1, R2, R3, R4 it receives indicates to it a request to implement the corresponding transition. Therefore, each pulse generator PG1, PG2, PG3, PG4 receives the signal "locked".

[0173] As Figure 6 In the example illustrated by dotted lines, when each pulse of each of the signals CK1 to CK4 corresponds to a high level of the signal, the signal "LOCK" is, for example, the output signal of an OR gate 600 having the signals CK1 to CK4 as inputs, then the first level of the signal "LOCK" is the high level of the signal.

[0174] In an embodiment in which, for each transition, the duration of the pulse of the signal CK1 to CK4 generated to achieve the transition is determined or controlled by switching the output terminal of the flip-flop that achieves the transition, and thus the duration of the pulse of the signal sig1 to sig4 is determined or controlled, each pulse generator PG1 to PG4 is configured so that, at each pulse of its output signal, the switching of the output bit of the flip-flop that achieves the transition associated with the generator ends the pulse of its output signal. For example, each pulse generator PG1, PG2, PG3, PG4 includes an input terminal configured to control the setting back to the idle state of its output signal sig1, sig2, sig3 or sig4, that is, to force the end of the pulse of its output signal. Then, the input terminal of the pulse generator receives a signal representing the output bit of the flip-flop of the transition associated with the generator, for example, directly receives the output bit of the flip-flop, wherein the pulse generators PG1, PG2, PG3 and PG4 receive bits b1, b2, b3 and b4, respectively, as Figure 6 As shown in the figure.

[0175] In an alternative embodiment (not shown), for each transition, the duration of the pulse of the signal CK1 to CK4 generated to achieve the transition is determined or controlled by switching the D input terminal of the flip-flop that achieves the transition, thereby determining or controlling the duration of the pulse of the signal sig1 to sig4. In this case, each pulse generator PG1 to PG4 is configured so that at each pulse of its output signal, the switching of the input bit of the flip-flop that achieves the transition associated with the generator ends the pulse of its output signal. For example, each pulse generator PG1, PG2, PG3, PG4 includes an input terminal configured to control the setting back to the idle state of its output signal sig1, sig2, sig3 or sig4, that is, to force the end of the pulse of its output signal. Then, the input terminal of the pulse generator receives a signal representing the input bit of the flip-flop of the transition associated with the generator, for example, directly receiving the input bit of the flip-flop. For example, in such an embodiment, the pulse generator PG4 receives the input bit b1 of the flip-flop FF-LS2OFF associated with the generator PG4.

[0176] In another alternative embodiment (not shown), for each transition, the duration of the pulse of the signal CK1 to CK4 generated to achieve the transition is determined or controlled by a combination of the switching of the D input terminal of the flip-flop that achieves the transition and the switching of the output terminal of the flip-flop that achieves the transition, thereby determining or controlling the duration of the pulse of the signal sig1 to sig4. In this case, each pulse generator PG1 to PG4 is configured so that at each pulse of its output signal, the combination of the switching of the D input terminal of the flip-flop that achieves the transition associated with the generator and the switching of the output terminal of the flip-flop that achieves the transition associated with the generator ends the pulse of its output signal. For example, each pulse generator PG1, PG2, PG3, PG4 includes an input terminal configured to control the setting back to the idle state of its output signal sig1, sig2, sig3 or sig4, that is, to force the end of the pulse of its output signal. Then, this input of the pulse generator receives a signal representing a combination of the input bit and the output bit of the flip-flop associated with the transition, for example, directly receiving the output bit of a logic gate having as input the complement of the input bit and the output bit of the flip-flop (when these bits are active in the high state). For example, in such an embodiment, if bit b1 is inactive and bit b4 is active, the pulse generator PG4 receives a bit in the first state, otherwise it receives a bit in the second state.

[0177] In yet another embodiment, the duration of the output pulses of the generators PG1 to PG4 is fixed.

[0178] According to one embodiment, there is provided Figure 1 The state machine FSM is composed of a switching converter similar to or identical to a switching converter of Figures 2 to 6 Specific examples are provided here and implemented in the state machine or circuit aFSM described above.

[0179] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features and variations of these various embodiments may be combined, and that other variations will occur to those skilled in the art. Specifically, based on the above description of specific examples of embodiments, those skilled in the art will be able to provide a finite state machine aFSM for controlling a converter that includes other transitions between states OFF, HS and LS in addition to the described transitions. In addition, those skilled in the art will be able to adapt the described examples when the pulses of at least one of the described signals each correspond to a low level rather than a high level of the signal, and / or when at least one of the output bits of the flip-flop that implements the transition is active when it is at its low level (or low state).

[0180] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. An asynchronous finite state machine for controlling a high-side switch and a low-side switch of a switching converter, characterized in that: The state machine includes a plurality of states connected together by transitions, and the asynchronous finite state machine includes: a flip-flop for implementing each transition, wherein each flip-flop has an output terminal configured to supply a bit representing a state of the asynchronous finite state machine, the state being an arrival state of the transition implemented by the flip-flop, a data input terminal configured to receive a bit representing an initial state of the transition implemented by the flip-flop, and a control input terminal configured to receive a first binary signal dedicated to the flip-flop; a first combinatorial circuit configured to supply, for each transition, a second binary signal corresponding to the transition and indicating whether the transition needs to be implemented, based on an input signal of the asynchronous finite state machine and a bit supplied by an output terminal of the flip-flop; and a second circuit configured to generate, based on the second binary signal, a pulse of the first binary signal dedicated to a flip-flop implementing the transition and a pulse of the first binary signal dedicated to each flip-flop whose output is configured to supply a bit to a data input of the flip-flop implementing the transition, each time a transition is requested and in the absence of a pulse of the first binary signal.

2. The asynchronous finite state machine according to claim 1, characterized in that: Each flip-flop is configured such that the start of each pulse of the first binary signal dedicated to the flip-flop causes an update of the flip-flop.

3. The asynchronous finite state machine according to claim 1, characterized in that: The second circuit is configured to, each time a request is made to implement a transition and in the absence of a pulse of the first binary signal, generate a pulse of the first binary signal only for a trigger dedicated to implementing the transition and a pulse of the first binary signal dedicated to each trigger whose output is configured to supply a bit to a data input of the trigger implementing the transition.

4. The asynchronous finite state machine according to claim 1, characterized in that: The first combinatorial circuit does not include a state register and does not include a circuit for storing an input signal of the asynchronous finite state machine.

5. The asynchronous finite state machine according to claim 1, characterized in that: The asynchronous finite state machine comprises: at least one pair of transitions having the same initial state; and For each pair of transitions having the same initial state, the first combinational circuit includes a mutual exclusion circuit configured to supply, based on a plurality of the input signals of the asynchronous finite state machine, a second binary signal indicating whether a first transition in the pair of transitions needs to be implemented and a second binary signal indicating whether a second transition in the pair of transitions needs to be implemented, such that only one of the second binary signals indicates that a transition corresponding to the second binary signal is required.

6. The asynchronous finite state machine according to claim 1, characterized in that: The second circuit: A method for generating a pulse generator associated with each transition includes: receiving a second binary signal corresponding to the transition; and generating an output pulse each time a request is made to effect said transition and in the absence of a pulse of said first binary signal; as well as A third combinational circuit is included, the third combinational circuit configured to supply the first binary signal based on the output pulse of the pulse generator.

7. The asynchronous finite state machine according to claim 6, characterized in that: The third combination circuit is also configured to transmit a locked binary signal at a first level only when at least one of the first binary signals exhibits a pulse, and otherwise transmit a locked binary signal at a second level, and each pulse generator is configured not to transmit an output pulse when the locked binary signal is at the first level.

8. The asynchronous finite state machine according to claim 6, characterized in that: Each pulse generator is configured to cause, at each output pulse delivered by the pulse generator, switching of an output terminal of a flip-flop effecting a transition associated with the generator to end the output pulse.

9. The asynchronous finite state machine according to claim 6, characterized in that: Each pulse generator is configured to cause, at each output pulse delivered by said pulse generator, switching of a data input of a flip-flop effecting a transition associated with said generator to terminate said output pulse.

10. The asynchronous finite state machine according to claim 1, characterized in that: The second circuit is configured such that each pulse of the first binary signal has the same constant duration determined by a hold time of the flip-flop.

11. The asynchronous finite state machine according to claim 1, characterized in that: The second circuit is configured so that each time a request is made to implement a transition, the second circuit generates a pulse of the first binary signal dedicated to a trigger that implements the transition and a pulse of the first binary signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger that implements the transition, and switching of the output terminal of the trigger that implements the transition ends the pulse.

12. The asynchronous finite state machine according to claim 1, characterized in that: The second circuit is configured so that each time a request is made to implement a transition, the second circuit generates a pulse of the first binary signal dedicated to a trigger that implements the transition and a pulse of the first binary signal dedicated to each trigger whose output terminal is configured to supply a bit to a data input terminal of the trigger that implements the transition, and switching of the data input terminal of the trigger that implements the transition ends the pulse.

13. The asynchronous finite state machine according to claim 1, characterized in that: The asynchronous finite state machine is configured to implement: The first stage controls the high-voltage side switch of the switching converter to be in an on state and controls the low-voltage side switch of the converter to be in an off state; The second stage controls the low-voltage side switch to be in an on state and the high-voltage side switch to be in an off state respectively; and In the third stage, the two switches are controlled to be in the cut-off state. And wherein, for each state, the asynchronous finite state machine is configured to implement one of the first stage, the second stage, and the third stage.

14. The asynchronous finite state machine according to claim 13, characterized in that: The asynchronous finite state machine is configured to control the converter alternately in a continuous conduction mode and a discontinuous conduction mode, wherein the continuous conduction mode includes one or more implementations of a continuous process of the second phase, the third phase, and the first phase, and the discontinuous conduction mode includes one or more implementations of a continuous process of the second phase and the first phase.

15. The asynchronous finite state machine according to claim 13, characterized in that: The trigger precisely comprises a first trigger, a second trigger, a third trigger and a fourth trigger, and the first trigger, the second trigger, the third trigger and the fourth trigger are configured such that: A data input terminal of the first flip-flop receives a bit supplied by an output terminal of the second flip-flop and a bit supplied by an output terminal of the third flip-flop; Data input terminals of the third flip-flop and the fourth flip-flop each receive a bit supplied by an output terminal of the first flip-flop; and A data input terminal of the second flip-flop receives a bit supplied by an output terminal of the fourth flip-flop.

16. The asynchronous finite state machine according to claim 15, characterized in that: a bit supplied by the output terminal of the second flip-flop and a bit supplied by the output terminal of the third flip-flop representing a first state of the asynchronous finite state machine; a bit supplied by an output terminal of the first flip-flop representing a second state of the asynchronous finite state machine; a bit supplied by an output terminal of the fourth flip-flop representing a third state of the asynchronous finite state machine; and The asynchronous finite state machine is configured to implement the first phase, the second phase, and the third phase in the first state, the second state, and the third state, respectively.

17. A switching converter, characterized in that: The switching converter comprises: a high side switch coupling the connection node to a node configured to receive a power supply potential; a low side switch coupling the connection node to a node configured to receive a reference potential; an inductor coupling the connection node to an output terminal of the converter; and The asynchronous finite state machine according to claim 1, wherein the asynchronous finite state machine is used to control a high-side switch and a low-side switch of a switching converter.

18. An asynchronous finite state machine having a plurality of states connected together by transitions, characterized in that The asynchronous finite state machine comprises: a flip-flop for each transition, wherein the output of each flip-flop supplies a bit representing the arrived state of said asynchronous finite state machine, wherein a data input receives a bit representing the initial state of said transition, and a control input receives a first binary signal dedicated to said flip-flop; a first combinatorial circuit configured to process an input signal of the asynchronous finite state machine and to process bits at an output of the flip-flop to generate, for each transition, a second binary signal indicating that the transition is implemented; and a second circuit configured to process the second binary signal and, for each implementation of a transition, to generate a pulse of the first binary signal dedicated to a flip-flop implementing the transition and to generate a pulse of the first binary signal dedicated to each flip-flop whose output supplies a bit to a data input of the flip-flop implementing the transition.

19. The asynchronous finite state machine according to claim 18, characterized in that: When at least one pair of transitions have the same initial state, the first combinational circuit includes a mutual exclusion circuit configured to supply a second binary signal for controlling only one flip-flop associated with the pair of transitions, the second binary signal being provided to indicate implementation of the transitions.

20. The asynchronous finite state machine according to claim 18, characterized in that: The second circuit: A method for generating a pulse generator associated with each transition includes: receiving a second binary signal corresponding to the transition; and generating an output pulse each time a request is made to effectuate said transition; as well as A third combinational circuit is included, the third combinational circuit configured to supply the first binary signal based on the output pulse of the pulse generator.

21. The asynchronous finite state machine according to claim 18, characterized in that: The second circuit is configured such that each pulse of the first binary signal has the same constant duration determined by a hold time of the flip-flop.

22. A switch circuit, characterized in that: The switch circuit comprises: a plurality of transistor switches; and The asynchronous finite state machine of claim 18, wherein the asynchronous finite state machine is configured to control the plurality of transistor switches.

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