Electronic device

Abstract

Some embodiments of the present application disclose an electronic device comprising: a first wafer; the second wafer is arranged above the first wafer; the third wafer is arranged above the second wafer; the first conductive element is arranged between the first wafer and the second wafer and is used for providing a power supply path for the first wafer and the second wafer; and the second conductive element is arranged between the second wafer and the third wafer and is used for providing a non-power supply path for the second wafer and the third wafer. The electronic device provided by the utility model at least can avoid the influence of a power supply path on a non-power supply path.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to an electronic device. Background Art

[0002] In traditional electronic devices, the power supply path and the non-power supply path are both set on the same side of the electronic device, such as in the front end of line (FEOL) or back end of line (BEOL) of the electronic device. However, since the power supply path and the non-power supply path are set in the same loop, the heat generated in the power supply path will affect the non-power supply path. For example, when the non-power supply path is used as a signal path to transmit a signal, the heat generated in the power supply path will interfere with the signal transmitted in the non-power supply path and cause power loss and unnecessary coupling effects.

[0003] Reference below Figure 1 to Figure 2 The structure shown is described in detail. Figure 1 and Figure 2 Schematic cross-sectional views of an electronic device 10 and an electronic device 30 in the prior art are shown respectively. Figure 1 The electronic device 10 shown includes two substrates 12 and 14 stacked in sequence from bottom to top, and two chips 16 and 18 located above the substrates 14 and spaced apart laterally. Figure 1 FIG. 1 shows a power supply path 20 and a non-power supply path 22 of the electronic device 10. Figure 1 It can be seen that the power supply path 20 and the non-power supply path 22 are both disposed on the same side of the chips 16 , 18 , for example, both pass through the substrates 12 , 14 below the chips 16 , 18 to connect to the chips 16 , 18 . Figure 2 The illustrated electronic device 30 includes a substrate 32 and two dies 34 , 36 located above the substrate 32 and laterally spaced apart. Figure 2 The power supply path 38 and the non-power supply path 40 are shown in FIG. Figure 2 It can be seen that the power supply path 38 and the non-power supply path 40 are both arranged on the same side of the wafers 34 and 36, for example, both pass through the substrate 32 below the wafers 34 and 36 to connect to the wafers 34 and 36. Therefore, regardless of the electronic device 10 or the electronic device 30, their power supply path and non-power supply path are both located on the same side of the wafer, so that the heat generated by the power supply path affects the non-power supply path, for example, when the non-power supply path transmits a signal, it will affect the signal transmitted in the non-power supply path and cause power loss and unnecessary coupling effect.

[0004] In order to solve the above technical problems, Intel has developed electronic devices with backside power delivery to improve performance. Figure 3 A cross-sectional schematic diagram of an electronic device 50 with backside power delivery developed by Intel is shown. Figure 3 The electronic device 50 shown includes a substrate 52 , and three chips 54 , 56 , 58 located above the substrate 52 and stacked in sequence from bottom to top. Figure 3 FIG. 5 shows power supply paths 60, 62, 64 and non-power supply paths 66, 68, 70 in the electronic device 50. Figure 3 It can be seen that the power supply paths 60 and 62 can supply power from the substrate 52 to the back side of the wafers 54 and 56, the power supply path 62 can supply power from the substrate 52 through the wafer 54 to the back side of the wafer 56, and the power supply path 64 can supply power to the wafer 58 through the wafers 54 and 56. In addition, the non-power supply path 66 located on the active side of the wafer 54 can be connected downward to the substrate 52, and the non-power supply paths 68 and 70 located on the wafers 56 and 58 respectively pass through the wafers 56 and 54 to be connected downward to the substrate 52 respectively. Thus, the non-power supply path (for example, transmitting a signal) is provided through the active side, and the power supply path is provided through the back side to reduce the influence of the power supply path on the non-power supply path.

[0005] However, with the diversification and characteristics of packaging structures, especially the development of three-dimensional chip (3DIC) structures, this type of electronic device still has technical problems of the power supply path affecting the non-power supply path. For example, since the power supply path of the chips 56 and 58 still needs to pass through the chips 54 and 56, and the non-power supply paths 68 and 70 of the chips 56 and 58 still need to pass through the chips 54 and 56, the distance between the power supply path and the signal path passing through the chips 54 and 56 is also relatively close, so the electronic device 50 still has technical problems of the power supply path affecting the non-power supply path, such as interfering with the signal transmitted in the non-power supply path, causing power loss and unnecessary coupling effects, etc. Utility Model Content

[0006] In view of the above problems existing in the prior art, the present application proposes an electronic device, which can at least reduce the influence of the power supply path on the non-power supply path in the prior art.

[0007] According to one aspect of the present application, an electronic device is provided, which includes: a first chip; a second chip arranged above the first chip; a third chip arranged above the second chip; a first conductive element arranged between the first chip and the second chip and used to provide a power supply path between the first chip and the second chip; and a second conductive element arranged between the second chip and the third chip and used to provide a non-power supply path between the second chip and the third chip.

[0008] In one or more embodiments, the first conductive element and the second conductive element are flexible circuit boards.

[0009] In one or more embodiments, the first conductive element and the second conductive element extend respectively on the first lateral side and the second lateral side of the first chip to form a first extension portion and a second extension portion respectively, and the first extension portion and the second extension portion are laterally spaced apart from the first chip, wherein the first lateral side and the second lateral side are opposite sides of the first chip in the lateral direction.

[0010] In one or more embodiments, the electronic device further includes a first protection layer, wherein the first protection layer covers the first wafer and supports the first conductive element.

[0011] In one or more embodiments, the electronic device further includes a second protection layer located above the first protection layer, the second protection layer encapsulates the second wafer and covers the upper surface of the first conductive element, and the second protection layer supports the second conductive element.

[0012] In one or more embodiments, the electronic device further includes a third protection layer located above the second protection layer, wherein the third protection layer encapsulates the third wafer and covers an upper surface of the second conductive element.

[0013] In one or more embodiments, the first conductive element provides power to the back side of the first wafer and the back side of the second wafer.

[0014] In one or more embodiments, the electronic device further includes a conductive via extending from the first conductive element, the conductive via penetrating the second wafer and the second conductive element to supply power to the third wafer.

[0015] In one or more embodiments, the electronic device further includes a single-layer protection layer, wherein the single-layer protection layer covers the first chip, the second chip, the third chip, the first conductive element, and the second conductive element.

[0016] In one or more embodiments, the first protection layer supports at least the first extension of the first conductive element.

[0017] In one or more embodiments, the second protection layer supports at least the second extension portion of the second conductive element.

[0018] In one or more embodiments, an upper surface of the third protection layer is flush with an upper surface of the third wafer.

[0019] In one or more embodiments, an upper surface of the third protection layer is higher than and covers an upper surface of the third wafer.

[0020] In one or more embodiments, a first heat sink and a second heat sink are respectively disposed on the lower surface and the upper surface of the first conductive element, and the first heat sink and the second heat sink are both located between the first chip and the second chip.

[0021] In one or more embodiments, the first heat sink and the second heat sink directly contact the lower surface and the upper surface of the first conductive element, respectively.

[0022] In one or more embodiments, a third heat sink is disposed above the third wafer and in direct contact with the upper surface of the third wafer.

[0023] According to another aspect of the present application, an electronic device is provided, which includes: a first chip; a second chip, which is arranged above the first chip, and a first gap is provided between the first chip and the second chip; a third chip, which is arranged above the second chip, and a second gap is provided between the second chip and the third chip; a first conductive element, which passes through the first gap and supplies power to the first chip and the second chip; and a second conductive element, which passes through the second gap and is used to transmit signals between the second chip and the third chip.

[0024] In one or more embodiments, the back side of the first wafer and the back side of the second wafer face each other, and the active side of the second wafer and the active side of the third wafer face each other.

[0025] In one or more embodiments, the first conductive element is electrically connected to the back side of the first wafer and the back side of the second wafer through first solder balls and second solder balls, respectively.

[0026] In one or more embodiments, the electronic device further includes a substrate located below the first chip and facing the active side of the first chip, the second conductive element transmits signals of the second chip and the third chip downward through the substrate, and the first conductive element is electrically connected to the substrate.

[0027] The above technical solution of the present application provides a power supply path between the first chip and the second chip by a first conductive element disposed between the first chip and the second chip, and provides a non-power supply path between the second chip and the third chip by a second conductive element disposed between the second chip and the third chip, which can at least reduce the influence of the power supply path on the non-power supply path. The electronic device of another embodiment of the present application can at least avoid the heat generated by the first conductive element interfering with the transmission of the signal, and avoid power loss and unnecessary coupling effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. It is worth noting that according to the standard practice of the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, for the clarity of discussion, the size of each component can be arbitrarily increased or reduced.

[0029] Figure 1 A cross-sectional schematic diagram of an electronic device in the prior art is shown.

[0030] Figure 2 A cross-sectional schematic diagram of another electronic device in the prior art is shown.

[0031] Figure 3 A schematic cross-sectional view of an electronic device developed by Intel showing backside power delivery.

[0032] Figure 4 A schematic cross-sectional view of an electronic device according to an embodiment of the present application is shown.

[0033] Figure 5 A schematic cross-sectional view of an electronic device according to another embodiment of the present application is shown.

[0034] Figure 6 The embodiment according to the present application is shown Figure 4 A local enlarged schematic diagram of the area.

[0035] Figure 7 The embodiment according to the present application is shown Figure 4 A schematic cross-sectional view of an electronic device with the first wafer omitted.

[0036] Figure 8 Shows Figure 7 A local enlarged schematic diagram of the area including the conductive through hole.

[0037] Fig. 9 A schematic cross-sectional view of an electronic device according to another embodiment of the present application is shown.

[0038] Fig.10 A schematic cross-sectional view of an electronic device according to another embodiment of the present application is shown.

[0039] Fig.11 A schematic top view of an electronic device according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0041] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0042] In addition, the embodiments in the present application and the features in the embodiments may be combined with each other in the absence of conflicts. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments. It should be understood that the specific structures shown in the drawings are only for the sake of convenience of explanation and are not intended to limit the present application. When describing a specific figure, other structures not described in the drawings may be provided according to actual needs and are not intended to limit the present application.

[0043] Figure 4 FIG. 2 shows a partial cross-sectional schematic diagram of an electronic device 200 according to an embodiment of the present application. Figure 4As shown, the electronic device 200 includes: a first chip 202, a second chip 204 disposed above the first chip 202, and a third chip 206 disposed above the second chip 204. The electronic device 200 also includes a first conductive element 208 disposed between the first chip 202 and the second chip 204, and a second conductive element 210 disposed between the second chip 204 and the third chip 206. The first conductive element 208 is used to provide a power supply path between the first chip 202 and the second chip 204, and the second conductive element 210 is used to provide a non-power supply path between the second chip 204 and the third chip 206. Compared with the prior art in which the power supply path and the non-power supply path are arranged on the same side of the wafer or pass through the wafer, the electronic device 200 of the embodiment of the present application provides a power supply path between the first wafer 202 and the second wafer 204 by using the first conductive element 208 arranged between the first wafer 202 and the second wafer 204, and provides a non-power supply path between the second wafer 204 and the third wafer 206 by using the second conductive element 210 arranged between the second wafer 204 and the third wafer 206, so that the power supply path is separated from the non-power supply path, and at least the influence of the power supply path on the non-power supply path can be reduced. In addition, by providing the non-power supply path of the second wafer 204 and the third wafer 206 at the same time through the second conductive element 210 arranged between the second wafer 204 and the third wafer 206, the space for the non-power supply path can be saved, so that the non-power supply path can be arranged further away from the power supply path, so that the influence of the power supply path on the non-power supply path can be further reduced. In one embodiment, the second conductive element 210 is used to provide a signal path between the second wafer 204 and the third wafer 206.

[0044] In another aspect of the present application, another electronic device is provided, still referring to Figure 4The electronic device 200 includes a first chip 202, a second chip 204 disposed above the first chip 202, and a third chip 206 disposed above the second chip 204. A first gap 226 is provided between the first chip 202 and the second chip 204, and a first conductive element 208 passes through the first gap 226 and supplies power to the first chip 202 and the second chip 204. A second gap 228 is provided between the second chip 204 and the third chip 206, and a second conductive element 210 passes through the second gap 228 and is used to transmit signals between the second chip 204 and the third chip 206. The electronic device 200 of this embodiment of the present application supplies power to the first chip 202 and the second chip 204 through the first conductive element 208 passing through the first gap 226 between the first chip 202 and the second chip 204, and transmits signals of the second chip 204 and the third chip 206 through the second conductive element 210 passing through the second gap 228 between the second chip 204 and the third chip 206, so that power supply and signals are separated to achieve non-interference between power supply and signals, thereby at least preventing the heat generated in the first conductive element 208 for power supply from interfering with the signal transmitted by the second conductive element 210, and avoiding power loss and unnecessary coupling effects.

[0045] In some embodiments, the back side 202b of the first wafer 202 and the back side 204b of the second wafer 204 face each other, and the active side 202f of the second wafer 204 and the active side 206f of the third wafer 206 face each other. In one embodiment, the first conductive element 208 supplies power to the back side 202b of the first wafer 202 and the back side 204b of the second wafer 204. In addition, the second conductive element 210 provides a non-power supply path (e.g., a signal path for transmitting signals) for the second wafer 204 and the third wafer 206 from the active side 202f of the second wafer 204 and the active side 206f of the third wafer 206. In some embodiments, the electronic device 200 further includes a substrate 234 located below the first wafer 202 and facing the active side 202f of the first wafer 202, the first conductive element 208 is electrically connected to the substrate 234, and the second conductive element 210 transmits the signals of the second wafer 204 and the third wafer 206 downward through the substrate 234.

[0046] In some embodiments, the two opposite sides of the first wafer 202 in the lateral direction are respectively referred to as the first lateral side 202L1 and the second lateral side 202L2, and the first conductive element 208 and the second conductive element 210 extend respectively on the first lateral side 202L1 and the second lateral side 202L2 of the first wafer 202 to form the first extension portion 208A and the second extension portion 210A, respectively, and the first extension portion 208A and the second extension portion 210A are laterally spaced apart from the first wafer 202. In detail, the first conductive element 208 includes a first connecting portion 208L and a first extending portion 208A connected to the first connecting portion 208L, the first connecting portion 208L is located between the first wafer 202 and the second wafer 204 and is electrically connected to the first wafer 202 and the second wafer 204, and the first extending portion 208A is located outside the first wafer 202 and the second wafer 204 in the lateral direction and extends downward to be electrically connected to the substrate 234. The first conductive element 208 transmits the current from the first chip 202 and the second chip 204 to the substrate 234 (eg, Figure 4 as indicated by arrow 254).

[0047] In addition, the second conductive element 210 includes a second connecting portion 210L and a second extending portion 210A connected to the second connecting portion 210L, the first connecting portion 210L is located between the second chip 204 and the third chip 206 and is electrically connected to the second chip 204 and the third chip 206, and the second extending portion 210A is located outside the second chip 204 and the third chip 206 in the lateral direction and extends downward to be electrically connected to the substrate 234. The second conductive element 210 transmits the signal from the second chip 204 and the third chip 206 to the substrate 234 (such as Figure 4 The signal of the first chip 202 is directly transmitted to the substrate 234 via the solder balls (as shown by the arrow 256). Figure 4 The electronic device 200 of the embodiment of the present application arranges the first extension 208A and the second extension 210A of the first conductive element 208 and the second conductive element 210 on the first lateral side 202L1 and the second lateral side 202L2 of the first chip 202, respectively, so that the power supply path and the non-power supply path of the electronic device 200 are further away from each other, thereby facilitating further reducing the influence of the power supply path on the non-power supply path. Furthermore, in the embodiment where the second conductive element 210 is used to provide a signal path for the second chip 204 and the third chip 206, it is possible to more effectively avoid the power supply path from interfering with the signal transmitted in the signal path, and more effectively avoid power loss and unnecessary coupling effects.

[0048] In the embodiment of the present application, the first extension portion 208A and the second extension portion 210A are not limited to the first lateral side 202L1 and the second lateral side 202L2 of the first wafer 202, and may also be located at the same lateral side of the first wafer 202. In some embodiments, the first conductive element 208 and the second conductive element 210 are flexible circuit boards (e.g., flexible circuits), and the flexible circuit boards may also be referred to as soft boards. In some embodiments, the first conductive element 208 and the second conductive element 210 are formed by bending the soft boards, respectively. In some embodiments, the first conductive element 208 and the second conductive element 210 may be formed by a plurality of dielectric layers and conductive components (e.g., composed of metal formed by sputtering) located in the plurality of dielectric layers.

[0049] Figure 5 A schematic cross-sectional view of an electronic device 260 according to an embodiment of the present application is shown. Figure 5 The electronic device 260 is shown with Figure 4 The electronic device 200 shown is similar, and only the differences are described below. In some embodiments, the first extension 208A of the first conductive element 208 further extends away from the first chip 202 above the substrate 234 to form a power supply contact 252, and the electronic device 260 also includes a power supply bridge element 262 (e.g., an interposer) disposed above the power supply contact 252. In some embodiments, an external power element can be connected to the power supply contact 252 next to the first chip 202 through the power supply bridge element 262 to supply power to the electronic device 260. Further, the power supply bridge element 262 can be bridged with the power supply contact 252 next to the first chip 202 through a solder bump 264 formed in a solder printing process in a mature process. In addition, a power element 266 (e.g., a power management integrated circuit (PMIC) or an integrated voltage regulator (IVR)) can be independently disposed on the power supply bridge element 262 using the power supply bridge element 262 to supply power to the first conductive element 208. In addition, the first chip 202 , the second chip 204 , and the third chip 206 in the electronic device 260 may be chips in a system on chip (SOC) or a memory.

[0050] For simplicity, the power supply bridge element 262 and the power element 266 are omitted in the subsequent drawings. Figure 6 FIG. 2 shows an enlarged schematic diagram of a region of an electronic device 200 including a first wafer 202 and a second wafer 204 according to an embodiment of the present application. For clarity, Figure 6 The conductive via 218 is omitted in Figure 7 Detailed description is given in . Figure 4 and Figure 6 In some embodiments, the first conductive element 208 is electrically connected to the back side 202b of the first wafer 202 and the back side 204b of the second wafer 204 through the first solder ball 230 and the second solder ball 232, respectively. In one embodiment, the first solder ball 230 and the second solder ball 232 electrically connect the first connection portion 208L of the first conductive element 208 to the pads at the back side 202b of the first wafer 202 and the back side 204b of the second wafer 204, respectively. In some embodiments, the first heat sink 220 and the second heat sink 222 are respectively disposed on the lower surface and the upper surface of the first conductive element 208, and the first heat sink 220 and the second heat sink 222 are both located between the first wafer 202 and the second wafer 204. Accordingly, the first heat sink 220 is disposed between the first conductive element 208 and the first wafer 202, and the second heat sink 222 is disposed between the second conductive element 210 and the second wafer 204. In addition, the first solder ball 230 is located at the edge area of ​​the first wafer 202, and the first heat sink 220 is located at the center area of ​​the first wafer 202. Similarly, the second solder ball 232 is located at the edge area of ​​the second wafer 204, and the second heat sink 222 is located at the center area of ​​the second wafer 204. In some embodiments, the first heat sink 220 and the second heat sink 222 are directly in contact with the lower surface and the upper surface of the first conductive element 208, respectively. It is not difficult to understand that the lower surface and the upper surface of the first conductive element 208 are insulated from the first heat sink 220 and the second heat sink 222. In some cases, when the operating speed of the electronic device 200 is increased, the first conductive element 208 providing the power supply path will generate more heat. If the more heat cannot be conducted away in time, there is still a possibility of affecting the non-power supply path provided by the second conductive element 210. By providing the first heat sink 220 and the second heat sink 222 on the lower surface and the upper surface of the first conductive element 208, respectively, the heat generated by the first conductive element 208 can be conducted away in time. In this way, when the electronic device 200 operates at a higher speed, more heat generated by the first conductive element 208 is conducted away in time, so that even when the electronic device 200 operates at a higher speed, the influence of the first conductive element 208 on the non-power supply path provided by the second conductive element 210 can still be reduced. For example, when the second conductive element 210 is used to transmit a signal, interference with the signal transmitted in the second conductive element 210 can be avoided, and power loss and unnecessary coupling effects can be avoided.

[0051] In some embodiments, when the first conductive element 208 is a flexible circuit board, 20% of the area of ​​the lower surface and the upper surface of the first conductive element 208 is used for wiring to provide a power supply path, and 80% of the area of ​​the lower surface and the upper surface of the first conductive element 208 is used to contact the first heat sink 220 and the second heat sink 222, respectively, so that the heat generated by the first conductive element 208 is promptly conducted away. The first heat sink 220 and the second heat sink 222 can be metal (such as copper). In some cases, the first heat sink 220 and the second heat sink 222 may not be provided.

[0052] Figure 7 FIG. 2 is a cross-sectional schematic diagram of an electronic device 200 according to an embodiment of the present application, in which the first wafer 202 is omitted. Figure 4 and Figure 7 , the second connection portion 210L of the second conductive element 210 is electrically connected to the pads at the active side 204f of the second wafer 204 and the active side 206f of the third wafer 206 through the third solder ball 236 and the fourth solder ball 238, respectively. In some embodiments, the electronic device 200 further includes a conductive via 218 extending from the first conductive element 208, the conductive via 218 passing through the second wafer 204 and the second conductive element 210 to supply power to the third wafer 206. In order to more clearly illustrate the conductive via 218, Figure 8 Shows Figure 7 FIG. 2 is an enlarged schematic diagram of a region 240 including a conductive via 218. Figure 4 , Figure 7 and Figure 8In one embodiment, the conductive via 218 includes a first sub-via 218A, a second sub-via 218B, and a third sub-via 218C. The first sub-via 218A is led out from the first conductive element 208 and passes through the second wafer 204, the second sub-via 218B passes through the second conductive element 210, and the third sub-via 218C passes through the third wafer 206. The first sub-via 218A and the second sub-via 218B are copper-to-copper butt-jointed, and the second sub-via 218B and the third sub-via 218C can also be copper-to-copper butt-jointed. In some embodiments, the connection method between the first sub-via 218A and the second sub-via 218B and the connection method between the second sub-via 218B and the third sub-via 218C can both be one of micro-bump connection, solder paste connection, copper paste connection, etc.; the connection method between the first sub-via 218A and the second sub-via 218B and the connection method between the second sub-via 218B and the third sub-via 218C can be different from each other. The lower end of the first sub-via 218A is electrically connected to the first conductive element 208 through the pad and the second solder ball 232 at the back side 204b of the second chip 204. In some embodiments, the current from the first conductive element 208 can flow upward to the third chip 206 (such as the conductive via 218 on the left side) through the conductive via 218 on the left side. Figure 8 The current then flows back downward from the third chip 206 to the first conductive element 208 (eg, as shown in FIG. 242 ) through the conductive via 218 on the right side. Figure 8 (arrow 244). Although Figure 7 and Figure 8 Only two conductive vias 218 are shown, but the present application is not limited thereto, and more conductive vias 218 may also be formed. Figure 7 The second sub-via 218B is shown as passing through the end of the second conductive element 210 away from the second extension portion 210A. It is easy to understand that the end of the second conductive element 210 passed by the second sub-via 218B is set as a circuit without transmitting signals.

[0053] exist Figures 4 to 8In the illustrated embodiment, the electronic device 200 further includes a single-layer protective layer 246, which covers the first chip 202, the second chip 204, the third chip 206, the first conductive element 208, and the second conductive element 210. The single-layer protective layer 246 is located above the substrate 234, and the lateral opposite side walls of the single-layer protective layer 246 are aligned up and down with the lateral opposite side walls of the substrate 234. In some embodiments, the single-layer protective layer 246 can be a molding compound. By covering the first chip 202, the second chip 204, the third chip 206, the first conductive element 208, and the second conductive element 210 with a molding compound, the electronic device 200 can be prevented from failing. In other embodiments, the present application is not limited to a single-layer protective layer 246, and multiple protective layers can also be used. This will be discussed below in conjunction with Fig. 9 Provide detailed explanation.

[0054] Fig. 9 FIG. 4 is a schematic cross-sectional view of an electronic device 300 according to another embodiment of the present application. Fig. 9 The electronic device 300 is shown with Figure 4 The electronic device 200 shown is similar except that the single protective layer 246 is replaced by a first protective layer 212, a second protective layer 214, and a third protective layer 216. Fig. 9 As shown, the electronic device 300 may include a first protective layer 212, which covers the first wafer 202 and supports the first conductive element 208. In one embodiment, the first protective layer 212 at least supports the first extension portion 208A of the first conductive element 208. In this embodiment, the first protective layer 212 surrounds the first wafer 202 and is located below the first extension portion 208A to support at least the first extension portion 208A of the first conductive element 208. In addition, the first protective layer 212 may also be located between the first connection portion 208L and the first wafer 202 to support the first connection portion 208L of the first conductive element 208.

[0055] In some embodiments, the electronic device 300 may further include a second protective layer 214 located above the first protective layer 212, the second protective layer 214 encapsulating the second wafer 204 and covering the upper surface 208t of the first conductive element 208, and the second protective layer 214 supports the second conductive element 210. In one embodiment, the second protective layer 214 at least supports the second extension 210A of the second conductive element 210. In this embodiment, the second protective layer 214 surrounds the second wafer 204 and is located below the second extension 210A to support at least the second extension 210A of the second conductive element 210. In addition, the second protective layer 214 may also be located between the second connection portion 210L and the second wafer 204 to support the second connection portion 210L of the second conductive element 210. In some embodiments, the electronic device 300 may further include a third protective layer 216 located above the second protective layer 214, the third protective layer 216 encapsulating the third wafer 206 and covering the upper surface 210t of the second conductive element 210. In some embodiments, the first protective layer 212 , the second protective layer 214 and the third protective layer 216 may be made of the same molding compound, and therefore, the first protective layer 212 , the second protective layer 214 and the third protective layer 216 may sometimes be collectively referred to as a packaging structure.

[0056] The electronic device 300 of the embodiment of the present application uses the first protective layer 212 and the second protective layer 214 to support the first conductive element 208 and the second conductive element 210 respectively, and uses the second protective layer 214 and the third protective layer 216 to grasp the first conductive element 208 and the second conductive element 210 from the upper surface 208t of the first conductive element 208 and the upper surface 210t of the second conductive element 210 respectively, so when the first conductive element 208 and the second conductive element 210 are formed by a flexible circuit board, the first conductive element 208 and the second conductive element 210 can be prevented from being soft and collapsing, thereby improving the reliability of wafer stacking and flexible circuit board setting. Further, compared with a single protective layer, by forming the first protective layer 212, the second protective layer 214 and the third protective layer 216 respectively, the first protective layer 212, the second protective layer 214 and the third protective layer 216 can be better filled into the desired area to form a stronger support for the first conductive element 208 and the second conductive element 210.

[0057] exist Fig. 9 In the illustrated embodiment, the upper surface 216t of the third protection layer 216 is higher than and covers the upper surface 206t of the third wafer 206. It is easy to understand that the upper surface 206t of the third wafer 206 is the back side of the third wafer 206.

[0058] Fig.10 FIG. 4 is a schematic cross-sectional view of an electronic device 400 according to another embodiment of the present application. Fig.10The electronic device 400 is shown with Fig. 9 The electronic device 300 shown is similar to the electronic device 300 shown in the figure, and only the differences are described below. Fig.10 As shown, in the electronic device 400, the upper surface 216t of the third protective layer 216 is flush with the upper surface 206t of the third chip 206. In this embodiment, a third heat sink 224 is provided above the third chip 206 and is in direct contact with the upper surface 206t of the third chip 206. The electronic device 400 of the embodiment of the present application provides a heat dissipation path by providing a third heat sink 224 in direct contact with the upper surface 206t of the third chip 206, thereby improving the reliability of the electronic device 400. In some embodiments, the third heat sink 224 may also be a metal (e.g., copper). Fig.10 In the illustrated embodiment, the third heat sink 224 extends laterally beyond the lateral sides of the third chip 206 and directly contacts the upper surface 216 t of the third protection layer 216 .

[0059] Fig.11 FIG. 2 is a schematic top view of an electronic device 500 including a third heat sink 224 according to another embodiment of the present application. Fig.11 Some components are omitted and the conductive via 218 is enlarged, which does not mean that the conductive via 218 extends outside the third wafer 206 . Fig.11 The relative position of the third heat sink 224 and the conductive via 218 is shown. Fig.11 It can be seen that the third heat sink 224 is formed as a rectangle with a notch 224a, and the notch 224a is at the corner of the rectangle, and the conductive through hole 218 is arranged below the notch 224a. In some embodiments, the current from the first conductive element 208 can flow to the third chip 206 (such as Fig.11 The current then flows back from the third chip 206 to the first conductive element 208 (eg, Fig.11 arrow 250). Although Fig.11 It is shown that the third heat sink 224 extends laterally to the right beyond the third chip 206 , but the present application is not limited thereto.

[0060] Some embodiments of the present invention provide electronic devices by providing a power supply path between the first chip and the second chip through a first conductive element disposed between the first chip and the second chip, and providing a non-power supply path between the second chip and the third chip through a second conductive element disposed between the second chip and the third chip, so that the power supply path and the non-power supply path take different paths, which can at least avoid the influence of the heat generated by the power supply path on the non-power supply path. In the embodiment where the non-power supply path is used as a signal path, by making the power supply path and the signal path take different paths, the power supply and the signal do not interfere with each other, so that at least the heat generated in the power supply path can be avoided from interfering with the signal transmitted in the signal path, and power loss and unnecessary coupling effects can be avoided.

[0061] Another embodiment of the utility model provides an electronic device which supplies power to a first chip and a second chip through a first conductive element passing through a first gap, and transmits signals of the second chip and a third chip through a second conductive element passing through a second gap, thereby at least preventing the heat generated in the first conductive element from interfering with the signal transmitted by the second conductive element, and avoiding power loss and unnecessary coupling effects.

[0062] The electronic device of the embodiment of the present application grasps and supports the first conductive element and the second conductive element by the first protective layer, the second protective layer and the third protective layer, and matches the first conductive element and the second conductive element that meet the performance of the electronic device by utilizing the characteristics of the packaging structure. This not only reduces the impact of the power supply path, but also reduces and improves the reliability of the flexible circuit board setting. At the same time, the first conductive element, as an independent power supply path, can effectively achieve heat dissipation, grounding, and a non-interference structure. In addition, the electronic device of the embodiment of the present application can be achieved by using existing surface processing methods, process methods, process conditions, and structural applications, without the need to develop new process methods or manufacturing equipment.

[0063] It should be understood that the various features of the various embodiments of the present application can be replaced and combined. The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any combination of the various embodiments within the spirit and principle of the present application, as well as any modification, equivalent replacement, improvement, etc. made to the embodiments, shall be included in the protection scope of the present application.

Claims

1. An electronic device, characterized in that: include: a first wafer; A second chip, disposed above the first chip; A third chip is disposed above the second chip; A first conductive element is disposed between the first chip and the second chip and is used to provide a power supply path for the first chip and the second chip; as well as The second conductive element is disposed between the second chip and the third chip and is used for providing a non-power supply path between the second chip and the third chip.

2. The electronic device according to claim 1, characterized in that The first conductive element and the second conductive element are flexible printed circuit boards.

3. The electronic device according to claim 1, characterized in that: The first conductive element and the second conductive element extend respectively at a first lateral side and a second lateral side of the first wafer to form a first extension portion and a second extension portion respectively. The first extension and the second extension are laterally spaced apart from the first wafer, wherein the first lateral side and the second lateral side are opposite sides of the first wafer in a lateral direction.

4. The electronic device according to claim 3, characterized in that: The device also includes a first protection layer, which covers the first wafer and supports the first conductive element.

5. The electronic device according to claim 4, characterized in that: It also includes a second protective layer located above the first protective layer, the second protective layer envelops the second wafer and covers the upper surface of the first conductive element, and the second protective layer supports the second conductive element.

6. The electronic device according to claim 5, characterized in that The invention also includes a third protection layer located above the second protection layer, wherein the third protection layer encapsulates the third chip and covers the upper surface of the second conductive element.

7. The electronic device according to claim 1, characterized in that: The first conductive element supplies power to a back side of the first wafer and a back side of the second wafer.

8. The electronic device according to claim 1, characterized in that: The invention also includes a conductive via extending from the first conductive element, wherein the conductive via penetrates the second wafer and the second conductive element to supply power to the third wafer.

9. The electronic device according to claim 1, characterized in that: It also includes a single-layer protection layer, which covers the first chip, the second chip, the third chip, the first conductive element and the second conductive element.

10. The electronic device according to claim 1, characterized in that A first heat sink and a second heat sink are respectively disposed on the lower surface and the upper surface of the first conductive element. The first heat sink and the second heat sink are both located between the first chip and the second chip.

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