Electronic device

Abstract

Some embodiments of the present application provide an electronic device comprising: a lower redistribution structure; a wafer disposed over the lower redistribution structure and having a backside power supply network facing the lower redistribution structure; an upper redistribution structure disposed over the wafer and having an opening exposing a portion of the wafer; and a heat dissipation structure, wherein at least part of the heat dissipation structure is arranged in the opening and is connected to the wafer. According to the invention, the RDL is mainly divided into the upper RDL and the lower RDL, and the wafer is arranged between the upper RDL and the lower RDL, so that the warping degree of the electronic device is reduced.

Description

Technical Field

[0001] An embodiment of the present application relates to an electronic device. Background Art

[0002] The current panel-level fan-out package (PNL) specialty products have a warped surface, specifically, see Figures 1A to 1C , Figure 1A A cross-sectional view of a portion of a panel-level fan-out package (PNL) is shown. Figure 1B A cross-sectional view of a panel-level fan-out package (PNL) 10 with electronic components 14 connected thereto is shown, and Figure 1C Shows Figure 1B The warpage of the panel-level fan-out package (PNL) 10 at various stages is shown, wherein, in the abscissa, Debond represents the stage of debonding the carrier commonly used in the art from the panel-level fan-out package (PNL) 10, G / D represents the stage of grinding the surface of the molding compound (CPD) 12, and BSF represents the stage of using the back side film (BSF); the ordinate represents Figure 1B The warpage of the panel-level fan-out package (PNL) 10 is shown in FIG. Figure 1C In the drawings shown, PNL ASSY also represents the warpage amount of the PNL 10, and specific values ​​of the corresponding warpage are shown here.

[0003] See also Figure 1A and Figure 1C ,exist Figure 1B In the illustrated panel-level fan-out package (PNL) 10, a chip 13 such as a serial deserializer (SER), a computer component, etc. is disposed on a redistribution structure 11 of 8P7M (i.e., there are 8 dielectric layers and corresponding 7 metal layers), and then the corresponding chip 13 is packaged by a molding compound 12. It should be noted that Figure 1A and Figure 1B The 8P7M redistribution structure 11 shown is a schematic diagram, and those skilled in the art should understand the specific structure of the 8P7M redistribution structure 11 commonly used in the art, which will not be described in detail here. Figure 1C After debonding (DeBond), the warpage is pulled toward the crying face direction by the 8P7M redistribution structure 11, and the warpage is 3250μm at this time. After grinding the surface of the molding compound (G / D), the warpage can reach 10000μm, which exceeds the warpage specification of 2000μm in the field. Even using the back side film (BSF) cannot bring the warpage back to the specification, because the warpage can reach 6000μm at this time, which is much larger than the specification of 2000μm. Therefore, the above-mentioned panel-level fan-out package (PNL) 10 has the following problems:

[0004] 1. The redistribution structure 11 in the panel-level fan-out package (PNL) 10 requires 8P7M, and for telecommunications and interference prevention considerations, the circuit will be made thicker, resulting in a thick and multi-layer redistribution structure 11;

[0005] 2. The redistribution structure 11 is a high shrinkage material. The thicker it is, the more serious the warping will be.

[0006] 3. The shrinkage of the molding compound (CPD) 12 and the associated coefficient of thermal expansion (CTE) make it difficult to pull the warpage of the panel-level fan-out package (PNL) 10 back to within the specification of less than 2000um; and

[0007] 4. The existing redistribution structure 11 cannot be thinned.

[0008] In summary, in a package composed of panel-level fan-out packages (PNL) (i.e., 1PC PNL (1 PNL) is one package), the specification of PNL warpage is ±2000μm, while the warpage of current packages is >2000μm, so the current package yield is 0%. Utility Model Content

[0009] In order to solve the above problems, this application mainly divides the original 8P7M redistribution structure (RDL) used for functions and power supply into an upper redistribution structure and a lower redistribution structure, and sets the chip between the upper redistribution structure and the lower redistribution structure to balance the overall performance of warping.

[0010] An embodiment of the present application provides an electronic device, comprising: a lower redistribution structure; a chip, arranged above the lower redistribution structure and having a back power supply network facing the lower redistribution structure; an upper redistribution structure, arranged above the chip and having an opening exposing a portion of the chip; and a heat dissipation structure, at least a portion of the heat dissipation structure is arranged in the opening and connected to the chip.

[0011] In some embodiments, the heat dissipation structure is disposed on an active surface of the wafer facing the upper redistribution structure.

[0012] In some embodiments, the heat dissipation structure separates the conductive lines in the upper redistribution structure.

[0013] In some embodiments, a portion of the heat dissipation structure protrudes from the upper redistribution structure.

[0014] In some embodiments, the electronic device further includes: a sealant encapsulating the wafer, wherein a portion of the sealant is disposed between the wafer and the upper redistribution structure.

[0015] In some embodiments, the sealant covers a portion of the heat dissipation structure.

[0016] In some embodiments, the heat dissipation structure includes: a first portion covered by the sealant; and a second portion located in the opening, wherein in a top view, a coverage area of ​​the first portion is different from a coverage area of ​​the second portion.

[0017] In some embodiments, in a top view, the footprint of the second portion is smaller than the footprint of the first portion.

[0018] In some embodiments, in a top view, the footprint of the second portion is larger than the footprint of the first portion.

[0019] In some embodiments, a thermal interface material is filled between the second portion of the heat dissipation structure and the upper redistribution structure.

[0020] In some embodiments, a glue layer is filled between the second portion of the heat dissipation structure and the upper redistribution structure.

[0021] In some embodiments, the glue layer extends into the sealant.

[0022] In some embodiments, the electronic device further includes: a heat dissipation layer connected to the upper redistribution structure and the heat dissipation structure through a thermal interface material, wherein the thermal interface material is interposed between the heat dissipation layer and the upper redistribution structure and the heat dissipation structure.

[0023] In some embodiments, the upper redistribution structure has a dielectric layer, and a side surface of the dielectric layer is recessed from an upper surface of the dielectric layer away from the wafer.

[0024] In some embodiments, a portion of a side surface of the dielectric layer is connected to a side surface of the second portion of the heat dissipation structure.

[0025] In some embodiments, the heat dissipation structure includes a stacked conductive structure and a non-conductive structure.

[0026] In some embodiments, in a stacking direction of the first portion and the second portion of the heat dissipation structure, the first portion of the heat dissipation structure overlaps with a portion of the upper redistribution structure.

[0027] Other embodiments of the present application also provide an electronic device, characterized in that it includes: a chip; a lower redistribution structure arranged below the chip; a plurality of discrete upper redistribution structures arranged above the chip; and a heat dissipation structure interposed between adjacent upper redistribution structures of the plurality of discrete upper redistribution structures and connected to the chip.

[0028] In some embodiments, the heat dissipation structure is disposed on an active surface of the wafer facing the upper redistribution structure.

[0029] In some embodiments, the heat dissipation structure includes: a first portion; and a second portion located above the first portion and between the adjacent upper redistribution structure, wherein in a top view, a footprint of the first portion is different from a footprint of the second portion.

[0030] In summary, the electronic device provided in the present application can effectively reduce the warping degree of the corresponding electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0032] Figures 1A to 1C A prior art panel level fan-out package and the corresponding warpage are shown.

[0033] Figure 2A , Figure 2A-1 to Figure 2A-4 A comparison between a panel-level fan-out package in the prior art and the corresponding warpage and the warpage of the electronic device provided in the present application is shown.

[0034] Figure 3A , Figure 3A-1 as well as FIG. 3B to FIG. 3E An electronic device according to some embodiments of the present application is shown.

[0035] FIG. 4A to FIG. 4B An electronic device according to another embodiment of the present application is shown.

[0036] Figures 5 to 22 A process flow for forming an electronic device according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0037] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. In addition, when "approximately", "about", "substantially", etc. are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0038] Some embodiments of the present application provide an electronic device that utilizes backside power supply technology to divide the original 8P7M redistribution structure (RDL) for functions and power supply into an upper redistribution structure and a lower redistribution structure, thereby reducing the warping degree of the corresponding electronic device. Furthermore, the electronic device can utilize a heat dissipation structure to reduce the high heat generated when the chip is running. In addition, the electronic device provided by the present application can utilize a whole-piece heat dissipation layer to resist the warping behavior of the electronic device.

[0039] Specifically, see the Figure 2A , Figure 2A-1 to Figure 2A-4 , Figure 2A FIG. 4 shows the warpage of the corresponding panel-level fan-out package of the 8P7M redistribution structure 11 used in the prior art (where Q represents other devices). Figure 2A-1 FIG. 2 shows the warpage of an electronic device using a thinner 3P3M upper redistribution structure 101t on the top and a thicker 5P4M lower redistribution structure 101d on the bottom, and FIG. Figure 2A-2 Shown in Figure 2A-1 The warpage after forming a whole-piece heat sink layer on the structure shown. Similarly, Figure 2A-3 FIG. 2 shows the warpage of an electronic device using a thicker 5P4M upper redistribution structure 101t on the top and a thinner 3P3M lower redistribution structure 101d on the bottom, and FIG. Figure 2A-4 Shown in Figure 2A-3 The warping after forming a whole-piece heat dissipation layer on the structure shown in FIG. Figure 2A-2 to Figure 2A-4 In the figure, Q' represents other devices. Figure 2A-1 It can be seen from the figure that for the 8P7M redistribution structure 11 used in the prior art, the warpage of the panel-level fan-out package is as high as 8mm (forming a convex structure), and 8mm is the distance from the top to the bottom of the convex structure. In addition, for the 8P7M redistribution structure 11, since the 8P7M redistribution structure 11 is too large, it is difficult to process the warpage of the corresponding panel-level fan-out package to within the test standard of ±2mm. When within the test standard of ±2mm, it can ensure that the subsequent electronic devices 100 / 200 (see below) Figure 3A and Figure 4A )’s warpage is less than ±2000μm, i.e., guaranteed to be within specifications.

[0040] When Figure 2A-1 As shown in the figure, when a thinner 3P3M upper redistribution structure 101t is used at the top and a thicker 5P4M lower redistribution structure 101d is used at the bottom, the warping of the corresponding electronic device is only 5 mm (the thin upper and thick lower redistribution structure at this time makes the corresponding electronic device form a convex structure due to the warping), where 5 mm is the distance from the top to the bottom of the convex structure. Then, as shown in FIG. Figure 2A-2As shown in FIG. 1 , after forming the whole heat dissipation layer 106, the warping of the corresponding electronic device is only 1.5 mm (also a convex structure). Figure 2A-3 As shown in the figure, when a thicker 5P4M upper redistribution structure 101t is used at the top and a thinner 3P3M lower redistribution structure 101d is used at the bottom, the warping of the corresponding electronic device is only -6mm (the thick upper and thin lower redistribution structure at this time causes the corresponding electronic device to form a concave structure due to the warping), where 6mm is the distance from the top to the bottom of the convex structure, and "-6mm" indicates a concave structure. Afterwards, as shown in the figure, Figure 2A-4 As shown, after the whole-piece heat dissipation layer 106 is formed, the warping of the corresponding electronic device is only 1mm (also a concave structure). It can be seen that the original 8P7M redistribution structure (RDL) 11 for function and power supply is divided into an upper redistribution structure 101t and a lower redistribution structure 101d (3P3M / 5P4M structure or 5P4M / 3P3M structure), and because the whole-piece heat dissipation layer 106 does not deform, the lower redistribution structure 101d at the bottom becomes less and thinner, even if a crying face structure is still formed when warping occurs, the warping is significantly reduced compared to the original, thereby reducing the warping degree of the corresponding electronic device.

[0041] The embodiment of the present application provides an electronic device 100, see Figure 3A , the electronic device 100 comprises: a lower redistribution structure 101d; and a wafer 103 disposed above the lower redistribution structure 101d and having a back side power supply network BSPDN facing the lower redistribution structure 101d, from Figure 3A It can be seen that the chip 103 has multiple chips, including chips 103-1 to 103-4. In some embodiments, chips 103-1 to 103-4 may include computers, serial deserializers (SurDes), etc. In some specific embodiments, chip 103-1 and chip 103-4 are serial deserializers, and chip 103-2 and chip 103-3 are computers. Further, the electronic device 100 also includes an upper redistribution structure 101t, which is disposed above the chip 103 and has an opening 101to exposing a portion of the chip 103; and a heat dissipation structure 104, at least a portion of the heat dissipation structure 104 is disposed in the opening 101to and is connected to the chip 103. Further, from Figure 3A As can be seen in FIG. 1 , the heat dissipation structure 104 separates the conductive lines 101t1 in the upper redistribution structure 101t. Figure 3AThe heat dissipation structure 104 is disposed on the active surface 103s of the wafer 103 facing the upper redistribution structure 101t. In the embodiment, the conductive lines 101d1 disposed in the lower redistribution structure 101d remain unchanged, that is, they are not separated and can be disposed as required. Figure 3A As can be seen in FIG. 1 , the lower redistribution structure 101 d continuously extends from one side of the electronic device 100 to the other side of the electronic device 100 , and ends with the corresponding outermost encapsulant 102 .

[0042] Further in Figure 3A In the embodiment, the electronic device 100 further includes: a sealant 102, the sealant 102 covers the chip 103. Further, a portion of the sealant 102 is disposed between the chip 103 and the upper redistribution structure 101t, and covers a portion of the heat dissipation structure 104. Figure 3A It can be seen that the heat dissipation structure 104 includes a first portion 104A covered by a sealant 102, and a second portion 104B located in the opening 101to of the upper redistribution structure 101t, and the second portion 104B is located above the first portion 104A. In some embodiments, the electronic device 100 also includes a thermal interface material (TIM) 105, and a heat dissipation layer 106 connected to the upper redistribution structure 101t and the heat dissipation structure 104 through the thermal interface material 105. It can be seen that in the electronic device 100, the thermal interface material 105 is between the heat dissipation layer 106 and the upper redistribution structure 101t and the heat dissipation structure 104.

[0043] In addition, if Figure 3A As shown, the electronic device 100 further includes a through hole 103T extending through the wafer 103, the through hole 103T extending through the wafer 103 to connect with the upper circuit layer 103tt at the active surface 103s of the wafer 103 and the lower circuit layer 103dt at the back surface 103b of the wafer 103 opposite to the active surface 103s, so as to communicate. In some embodiments, a conductive column 104T extending through the sealant 102 is arranged around the first portion 104A of the heat dissipation structure 104, and the conductive column 104T is arranged directly above the corresponding wafer 103 to electrically connect with the corresponding through hole 103T through the upper circuit layer 103tt at the active surface 103s of the wafer 103.

[0044] Further, in the electronic device 100 of the present application, the electronic device 100 further includes an electronic component 107 disposed at a side of the lower redistribution structure 101d opposite to the wafer 103. In a specific embodiment, the electronic component 107 includes a plurality of electronic components, such as a first electronic component 107-1 to a fourth electronic component 107-4, wherein the first electronic component 107-1 and the fourth electronic component 107-4 may be external connectors, and the second electronic component 107-2 and the third electronic component 107-3 may be voltage regulator modules (VRMs). Further, as Figure 3A As shown, the electronic component 107 is connected to the lower redistribution structure 101d through the bumps 108, and the bottom filler 109 is arranged between the bumps 108 and between the electronic component 107 and the lower redistribution structure 101d. In some other embodiments, the first part 104A and the second part 104B of the heat dissipation structure 104 are fixed with adhesive layers 111A and 111B, respectively. In the electronic device 100 provided in the present application, the heat dissipation structure 104 includes a stacked conductive structure and a non-conductive structure, that is, one of the first part 104A and the second part 104B of the heat dissipation structure 104 is a conductive structure, and the other is a non-conductive structure, that is, for heat conduction. In some other embodiments, the first part 104A and the second part 104B of the heat dissipation structure 104 can both be conductive structures or non-conductive structures, for example, the first part 104A and the second part 104B formed of a metal such as copper or a metal paste such as copper paste. Figure 3A In the embodiment, a drilling or fixing hole S is formed on the electronic device 100, and therefore, a hole is opened in the heat dissipation layer 106 at a position corresponding to the pre-drilled hole for fixing and the like.

[0045] Figure 3A-1 Shows Figure 3A The power supply path of the electronic device 100 shown in FIG. Figure 3A-1 ) and I / O (input / output) paths (as shown by the gray arrows in Figure 3A-1 As shown by the white arrow in the figure, Figure 3A-1 The number in Figure 3A Some of the labels may be obscured by the power supply path, but they can be found from Figure 3A Found at the corresponding position in .

[0046] from Figure 3A-1It can be seen that the electronic device 100 of the present application is combined with the back side power supply design of the back side power supply network BSPDN, and the chip 103 (such as a computer) can receive power from the lower redistribution structure 101d and the electronic component 107 through the back side (the side at the back surface 103b), and the input / output (I / O) can be connected to the lower redistribution structure 101d through the upper redistribution structure 101t and the chip 103 (such as a serial deserializer), and connected to the outside through the electronic component 107 (such as a connector), as follows:

[0047] The power supply path is: Figure 3A-1 As can be seen in the figure, the power supply energy enters from the first electronic component 107-1 (which can be an external connector), enters the second electronic component 107-2 (which can be a voltage regulator module (VRM)) through the lower redistribution structure 101d, and enters the second chip 103-2 (which can be a computer) from the second electronic component 107-2. Further, the power supply energy is driven through the through hole 103T in the second chip 103-2 (which can be a computer) to the transistor layer, and then returns to the lower redistribution structure 101d through the through hole 103T and is exported.

[0048] The I / O path is: coming out from above the second chip 103-2 (which can be a computer), entering the first chip 103-1 (which can be a serial deserializer (Surdes)) through the upper redistribution structure 101t, and entering the lower redistribution structure 101d via the first chip 103-1 (which can be a serial deserializer (Surdes)) into the first electronic component 107-1 (which can be an external connector).

[0049] The first part 104A and the second part 104B of the heat dissipation structure 104 are fixed by adhesive layers 111A and 111B above the first chip 103-1 (which can be a serial deserializer (Surdes)) and the second chip 103-2 (which can be a computer), and the upper redistribution structure 101t is exposed (the upper redistribution structure 101t is partially laid out, that is, it includes a plurality of discrete upper redistribution structures 101t1, 101t2...101t n ), and finally a continuous whole-piece heat dissipation layer 106 is formed above the fan-out structure (above the upper redistribution structure 101t). This increases the heat dissipation efficiency and reduces the warping problem. In addition, considering that the chip 103 has a higher heat dissipation requirement, a heat dissipation structure 104 can be configured to connect the chip 103 and the heat dissipation layer 106. In particular, in the electronic device 100 of the present application, an opening 101to is designed in the upper redistribution structure 101t to accommodate the heat dissipation structure 104.

[0050] Next, see FIG. 3B to FIG. 3D , FIG. 3B to FIG. 3D Shows Figure 3AThe heat dissipation structure 104 in the region A of the electronic device 100 is shown in various specific embodiments. FIG. 3B to FIG. 3D In the cross-sectional view shown, the width W of the second portion 104B is B The width W of the first portion 104A is A That is, in the corresponding top view, the footprint of the first portion 104A is different from the footprint of the second portion 104B. Figure 3B In the cross-sectional view shown, the width W of the second portion 104B is B Smaller than the width W of the first portion 104A A That is, in the top view, the footprint of the second portion 104B is smaller than the footprint of the first portion 104A. In this case, the thermal interface material 105 is filled between the second portion 104B of the heat dissipation structure 104 and the upper redistribution structure 101t. Figure 3B It can also be seen in FIG. 1 that a portion of the heat dissipation structure 104 protrudes from the upper redistribution structure 101t, that is, the second portion 104B protrudes from the upper redistribution structure 101t. Specifically, the top surface 104Bt of the second portion 104B is higher than the top surface 101ts of the upper redistribution structure 101t. Figure 3C In the cross-sectional view shown, the width W of the second portion 104B is B Still smaller than the width W of the first portion 104A A , and the thermal interface material 105 is still filled between the second portion 104B of the heat dissipation structure 104 and the upper redistribution structure 101t, but the second portion 104B of the heat dissipation structure 104 is recessed from the upper redistribution structure 101t, that is, the top surface 104Bt of the second portion 104B is lower than the top surface 101ts of the upper redistribution structure 101t. Figure 3B and Figure 3C The width W of the second portion 104B is shown B Smaller than the width W of the first portion 104A A When (such as Figure 3B and Figure 3C As shown in FIG. 1 , when an etching process is performed to form an opening 101to in the upper redistribution structure 101t, the etching process may stop at the second portion 104A, that is, the etching range of the dielectric layer 101td in the upper redistribution structure 101t is smaller than the width W of the first portion 104A. A , and the width W of the second portion 104B B Therefore, the gap between the second portion 104B and the upper redistribution structure 101 t is filled by the thermal interface material 105 . Figure 3E A diagram showing the etching of the corresponding upper redistribution structure 101t to form the opening 101to is shown.

[0051] However, in Figure 3DIn the cross-sectional view shown, the width W of the second portion 104B is B Greater than the width W of the first portion 104A A , that is, in the top view, the footprint of the second portion 104B is larger than the footprint of the first portion 104A. In this case, the glue layer 110 is filled between the second portion 104B of the heat dissipation structure 104 and the upper redistribution structure 101t. In addition, in a further embodiment, as Figure 3D As shown, the glue layer 110 extends into the sealant 102 because when the width W of the second portion 104B is B Greater than the width W of the first portion 104A A When the etching process is performed to form the opening 101to in the upper redistribution structure 101t, the range of the opening 101to is larger than the width W of the first portion 104A. A Therefore, the sealant 102 is etched. In addition, due to the material structure of the sealant 102 and the small etching selectivity thereto, the sealant 102 can be etched. That is, the etching range of the dielectric layer 101td in the upper redistribution structure 101t is greater than the width W of the first portion 104A. A , the width W of the second portion 104B B Therefore, the gap between the second portion 104B and the upper redistribution structure 101t needs to be filled by dispensing glue. Figure 3E A diagram showing the etching of the corresponding upper redistribution structure 101t to form the opening 101to is shown.

[0052] Return to see Figure 3B and Figure 3C In the stacking direction C of the first portion 104A and the second portion 104B of the heat dissipation structure 104, the first portion 104A of the heat dissipation structure 104 overlaps with a portion of the upper redistribution structure 101t, that is, in these embodiments, the first portion 104A of the heat dissipation structure 104 extends beyond the second portion 104B above it and extends to below the upper redistribution structure 101t.

[0053] Next, see Figure 3A and Figure 4A and Figure 4B ,in, Figure 4B Shows Figure 4A A magnified view of area B from Figure 4A and Figure 4B As can be seen from the figure, the upper redistribution structure 101t has a dielectric layer 101td (in Figure 4A ), and the side of the dielectric layer 101td is recessed from the upper surface of the dielectric layer 101td away from the wafer 103. Figure 4BIn the figure, a portion of the side surface 101tds of the dielectric layer 101td is connected to the side surface 104Bs of the second portion 104B of the heat dissipation structure 104. This is because the upper redistribution structure 101t avoids the area of ​​the heat dissipation structure 104 when forming the conductive line 101tl therein. Therefore, only the dielectric layer 101td exists in the area of ​​the upper redistribution structure 101t close to the heat dissipation structure 104. Figure 4B In the structure shown, the side of the dielectric layer 101td is recessed from the upper surface of the dielectric layer 101td away from the chip 103 because on both sides of the heat dissipation structure 104, when the dielectric layer 101td next to the heat dissipation structure 104 is ablated in the subsequent reflow, there will be traces of part of the dielectric layer 101td being ablated and recessed next to the heat dissipation structure 104, and finally the thermal interface material 105 is inlaid or filled in the recessed place.

[0054] See also Figure 3A Some other embodiments of the present application further provide an electronic device 100, the electronic device 100 comprising: a chip 103; a lower redistribution structure 101d, arranged below the chip 103. In this embodiment, the electronic device 100 comprises a plurality of discrete upper redistribution structures 101t1, 101t2, ..., 101t n , disposed above the chip 103; and a heat dissipation structure 104, the heat dissipation structure 104 between a plurality of discrete upper redistribution structures 101t1, 101t2 ... ... 101t n The heat dissipation structure 104 is disposed between adjacent upper redistribution structures (such as 101t1 and 101t2) of the wafer 103 and connected to the wafer 103. Similar to the above embodiment, the heat dissipation structure 104 is disposed on the upper redistribution structures 101t1, 101t2, ... 101t n Similarly, the heat dissipation structure 104 includes: a first portion 104A; and a second portion 104B located above the first portion 104A and between adjacent upper redistribution structures (such as 101t1 and 101t2). FIG. 3B to FIG. 3D As discussed, in the top view, the footprint of the first portion 104A is different from the footprint of the second portion 104B. In some other embodiments, the footprint of the first portion 104A and the footprint of the second portion 104B may also be the same.

[0055] In the above electronic device, the upper redistribution structure 101t and the lower redistribution structure 101d may adopt a 3P3M / 5P4M structure. In some embodiments, a 5P4M / 3P3M structure may also be adopted. This may be determined according to actual conditions.

[0056] In the above embodiment, the first layer 104A and the second layer 104B of the heat dissipation structure 104, the heat dissipation layer 106, the through hole 103T, the conductive column 104T, and the conductive line 101tl in the upper redistribution structure 101t and the conductive line 101dl in the lower redistribution structure 101d can all include conductive materials such as metals or metal alloys such as copper, aluminum, silver, gold, etc. The adhesive layers 111A and 111B and the glue layer 110 can all include resin layers commonly used in the art, such as epoxy resin. In addition, the dielectric layer 101td in the upper redistribution structure 101t and the dielectric layer 101dd in the lower redistribution structure 101d are both formed of dielectric materials, including but not limited to polyimide (PI). The conductive lines and dielectric layers in the upper wiring layer 103tt and the lower wiring layer 103dt are respectively formed of the same or similar materials as the conductive lines 101tl and dielectric layers 101td in the upper redistribution structure 101t or the conductive lines 101dl and dielectric layers in the lower redistribution structure 101d, and are not described again here. The thermal interface material 105 includes but is not limited to an adhesive with high thermal conductivity, for example, greater than about 1 watt / (k*m), 5 watts / (k*m) or more. The sealant 102 may include a molding compound, a bottom filler, etc. The bottom filler 109 may include an epoxy resin flux, etc. The bump 108 may include a solder ball, and includes but is not limited to solder, copper, aluminum, silver, gold, etc.

[0057] See below Figures 5 to 13 To illustrate Figure 3A The electronic device 100 or Figure 4A The process of forming the electronic device 200 is shown.

[0058] See also Figure 5 , the wafer 103 is attached to the carrier 1001 through the adhesive layer 1002. In this embodiment, the back side power supply network BSPDN of the wafer 103 faces the carrier 1001. Specifically, the active surface 103s of the wafer 103 faces upward, and the back surface 103b faces downward, that is, facing the carrier 1001. Further, the wafer 103 is formed with an upper wiring layer 103tt at the active surface 103s, and a lower wiring layer 103dt is formed at the back surface 103b. In addition, the wafer 103 is formed with a through hole 103T penetrating therethrough. Later, see further Figure 5, a conductive pillar 104T is formed above the wafer 103, such as by plating or the like. In a specific embodiment, the back side power supply network BSPDN is a back side power supply network commonly used in the art. The wafer 103 may be, for example, a computer, a serial deserializer, or the like. The upper circuit layer 103tt and the lower circuit layer 103dt are formed with conductive circuits and corresponding dielectric layers (such as polyimide layers). The through hole 103T and the conductive pillar 104T are made of a conductive material such as a metal or a metal alloy such as copper, aluminum, silver, gold, etc. In the present embodiment, the through hole 103T and the conductive pillar 104T are made of copper. In some embodiments, the adhesive layer 1002 may include epoxy resin or the like, and the carrier 1001 may be a silicon carrier, or a glass carrier, a ceramic carrier, or the like.

[0059] Then, a metal layer 104A' such as copper is bonded between the conductive pillars 104T on the wafer 103, for example, bonded to the wafer 103 via the adhesive layer 111A. In some embodiments, the adhesive layer 111A may be formed of the same or similar material as the adhesive layer 1002, which will not be described again.

[0060] Next, see Figure 6 , a sealant 102' is formed on the carrier 1001, and the sealant 102' may be a molding compound, and in this embodiment, a molding compound. In some embodiments, the sealant 102' may be formed by transfer molding, compression molding, and the like. Figure 6 As shown, the sealant 102' is formed to seal the wafer 103 and the metal layer 104A' therein. Afterwards, the carrier 1001 and the adhesive layer 1002 are removed by a process such as peeling.

[0061] See also Figure 7 , a lower redistribution structure 101d is formed at the back surface 103b of the wafer 103. As described above, the lower redistribution structure 101d is a 5P4M structure, that is, it is composed of 5 dielectric layers 101dd and 4 layers of conductive lines 101dl. Specifically, the dielectric layer 101dd is formed on the lower line layer 103dt at the back surface 103b of the wafer 103 and on the sealant 102'. In some embodiments, the dielectric layer 104dd is formed of a polymer such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. In the present embodiment, the dielectric layer 104dd is formed of polyimide (PI), and the dielectric layer 101dd can be formed by any acceptable deposition process such as spin coating, chemical vapor deposition (CVD), lamination, etc., or a combination thereof.

[0062] Conductive line 101d1 is formed on dielectric layer 101dd. As an example of forming conductive line 101d1, a seed layer (not shown) is formed above dielectric layer 101dd. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. Afterwards, a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive line 101d1. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. Conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Afterwards, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process (such as using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process (such as wet or dry etching). The remaining portion of the seed layer and the conductive material form the conductive line 101d1. The process of forming the dielectric layer 101dd and the conductive line 101d1 is repeated until the lower redistribution structure 101d of the 5P4M structure is formed.

[0063] Afterwards, see Figure 8 After forming the lower redistribution structure 101d, a portion of the sealant 102' and the metal layer 104A' are removed by a planarization process such as grinding until the conductive pillar 104T is exposed, thereby forming the sealant 102 and the first layer 104A, which is a part of the heat dissipation structure 104 formed later.

[0064] See also Fig. 9 , a second layer 104B such as a copper layer is formed on the first layer 104A, for example, the second layer 104B is bonded to the first layer 104A through an adhesive layer 111B, thereby forming a heat dissipation structure 104. After the heat dissipation structure 104 is formed, an upper redistribution structure 101t is formed around the heat dissipation structure 104. Fig.10 As shown, the upper redistribution structure 101t includes a dielectric layer 101td and a conductive line 101tl, and the conductive line 101tl bypasses the heat dissipation structure 104, and the heat dissipation structure 104 divides the upper redistribution structure 101t into a plurality of discrete upper redistribution structures 101t1, 101t2, ..., 101t n , and located on a plurality of discrete upper redistribution structures 101t1, 101t2...101t nbetween adjacent upper redistribution structures (such as 101t1 and 101t2). The formation method and materials of the upper redistribution structure 101t are the same or similar to the formation method and materials of the lower redistribution structure 101d, and will not be described in detail here. In the present embodiment, the upper redistribution structure 101t is a 3P3M structure, that is, it is composed of three dielectric layers 101td and three layers of conductive lines 101tl. It is worth noting that after the upper redistribution structure 101t is formed, the surface of the heat dissipation structure 104 will be micro-etched so that there will be no residue of the dielectric layer 101td (such as polyimide (PI)) on the surface of the heat dissipation structure 104.

[0065] Further, see Fig.11 , by using a blade etc. Fig.10 The structure shown is sawn into various suitable shapes, such as square, rectangle, octagon, etc. In this embodiment, Fig.10 The structure shown is sawn into an octagon (in top view). In addition, the laser drilling process commonly used in the art is further used to drill holes. Fig.10 The structure shown is laser drilled to form a drilled or fixed hole S on the outside of the wafer 103 for later fixing.

[0066] Next, see Fig.12 The thermal interface material 105 and the heat dissipation layer 106 are formed on the upper redistribution structure 101t by printing, physical vapor deposition or chemical vapor deposition. In some embodiments, the thermal interface material 105 fills the gap between the second portion 104B of the heat dissipation structure 104 and the upper redistribution structure 101t. In other embodiments, the adhesive layer 110 (see Figure 3D ) fills the gap between the second portion 104B of the heat dissipation structure 104 and the upper redistribution structure 101t, see above for details. FIG. 3B to FIG. 3D In some embodiments, the thermal interface material 105 includes, but is not limited to, an adhesive having a high thermal conductivity, for example, greater than about 1 Watt / (k*m), 5 Watt / (k*m), or greater. The heat dissipation layer 106 may be a metal layer and may be made of a conductive material such as a metal or metal alloy such as copper, aluminum, silver, gold, etc.

[0067] Finally, see Fig.13, the electronic component 107 will be connected to the lower redistribution structure 101d through the bump 108. In some embodiments, the bump 108 may include a solder ball, and includes but is not limited to solder, copper, aluminum, silver, gold, etc. In the present embodiment, the bump 108 is a solder ball. After the electronic component 107 is connected to the lower redistribution structure 101d through the bump 108, an underfill 109 may be formed between the bumps 108 and between the lower redistribution structure 101d and the electronic component 107. The underfill 109 may reduce stress and protect the joints created by the reflow of the bump 108. The underfill 109 may be formed by a capillary flow process after the electronic component 107 is attached. In some embodiments, epoxy flux may be used as the underfill 109. Thereafter, Fig.13 The structure shown is flipped to obtain Figure 3A The electronic device 100 / Figure 4A An electronic device 200 is shown.

[0068] See below Figures 14 to 22 To illustrate Figure 3A The electronic device 100 or Figure 4A Another process for forming the electronic device 200 is shown.

[0069] Figures 14 to 17 See above Figures 5 to 8 The process described is the same and will not be described in detail here. Fig.18 After planarizing the sealant 102 , an upper redistribution structure 101 t is formed over the sealant 102 and the first layer 104A. The formation process of the upper redistribution structure 101 t is as described above and will not be described in detail here.

[0070] Afterwards, see Fig.19 After forming the upper redistribution structure 101t, an opening 101to is formed in the upper redistribution structure 101t over the first layer 104A of the copper layer using a laser ablation process, thereby separating the upper redistribution structure 101t into discrete upper redistribution structures 101t1, 101t2, ..., 101t n . Afterwards, see Fig. 20 , a second layer 104B such as a copper layer is formed in the opening 101to, and the second layer 104B is bonded to the first layer 104A by, for example, an adhesive layer 111B.

[0071] Next, Fig.21 and Fig. 22 The process described Fig.12 and Fig.13 The process described is the same and will not be described in detail here. Fig. 22 The structure shown is flipped to obtain Figure 3A The electronic device 100 / Figure 4A An electronic device 200 is shown.

[0072] From the above, we can see that Figures 5 to 22 In the process shown, the present application uses a post-chip process, which can improve the cost and yield compared to the first-chip process. In addition, the present application uses a panel-level fan-out package, which has a higher space advantage and functionality increase advantage in increasing the number of chips 103 and electronic components 107 compared to the chip 103 flush method.

[0073] In summary, the electronic device 100 / 200 has the following advantages:

[0074] 1) Using backside power supply technology, such as the wafer 103 having a backside power supply network BSPDN, the original 8P7M redistribution structure (RDL) 11 for function and power supply is divided into an upper redistribution structure 101t and a lower redistribution structure 101d, thereby reducing the warpage of the corresponding electronic device;

[0075] 2) using buried metal (such as the heat dissipation structure 104 partially buried in the upper redistribution structure 101t) and the top heat dissipation layer 106 to reduce the high heat generated by the chip 103 (such as a computer) during operation; and

[0076] 3) Using the top side heat dissipation layer 106, and further, using the whole piece heat dissipation layer 106 to resist the warping behavior of the electronic device 100 / 200.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An electronic device, characterized in that: include: Lower redistribution structure; a wafer disposed above the lower redistribution structure and having a backside power supply network facing the lower redistribution structure; an upper redistribution structure disposed above the wafer and having an opening exposing a portion of the wafer; as well as A heat dissipation structure, at least a portion of which is disposed in the opening and connected to the chip.

2. The electronic device according to claim 1, characterized in that The heat dissipation structure is disposed on an active surface of the wafer facing the upper redistribution structure.

3. The electronic device according to claim 1, characterized in that: The heat dissipation structure separates the conductive lines in the upper redistribution structure.

4. The electronic device according to claim 1, characterized in that: A portion of the heat dissipation structure protrudes from the upper redistribution structure.

5. The electronic device according to claim 1, characterized in that Also includes: a sealant encapsulating the wafer, Wherein, a portion of the sealant is disposed between the wafer and the upper redistribution structure.

6. The electronic device according to claim 5, characterized in that The sealant covers a portion of the heat dissipation structure.

7. The electronic device according to claim 5, characterized in that: The heat dissipation structure comprises: A first portion, coated with the sealant; and a second portion, located within the opening, Wherein, in a top view, a coverage area of ​​the first portion is different from a coverage area of ​​the second portion.

8. The electronic device according to claim 1, characterized in that: Also includes: a heat dissipation layer connected to the upper redistribution structure and the heat dissipation structure through a thermal interface material, Wherein, the thermal interface material is located between the heat dissipation layer and the upper redistribution structure and the heat dissipation structure.

9. The electronic device according to claim 7, characterized in that: The upper redistribution structure has a dielectric layer, a side surface of the dielectric layer is recessed from an upper surface of the dielectric layer away from the wafer, wherein a portion of the side surface of the dielectric layer is connected to a side surface of the second portion of the heat dissipation structure.

10. The electronic device according to claim 1, characterized in that The heat dissipation structure includes a stacked conductive structure and a non-conductive structure.

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