Novel combined reset circuit
By designing a new combined reset circuit, the output feature voltage and the voltage change of the output feature voltage and the USB charging interface of the wireless module after the wireless module is inserted. The problem of unusual crashes before the gate dog initialization was solved, and the automation and reliability of hardware power -to -power reset was realized.
Patent Information
- Application Number
- CN202421242629.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-02
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2034-06-02
AI Technical Summary
The prior art is difficult to realize the hardware power-on reset before the initialization of the wireless module watchdog, resulting in the failure to restore normality in an abnormal crash state.
Design a new combined reset circuit. By capturing the output feature voltage and the voltage changes when inserting the USB charging interface of the wireless module, the unidirectional pitch performance of the diode can be used to achieve logic or door circuit to further generate positive pulses through the micro -divide circuit. The negative pulse is then achieved through the anti -phase circuit of the triode, and the hardware of the wireless module is finally driven.
The wireless terminal resumed the normal condition before the abnormal crash state before the first dog initialization was completed. The automatic processing of the wireless module before watching the door was initialized. The cost was low and the performance was reliable. Stablize.
Smart Images
Figure CN222395659U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of combined reset circuits, and in particular relates to a novel combined reset circuit. Background Art
[0002] After the wireless module crashes, its external output voltage will suddenly change from 1.8V to above 1.95V. In view of this feature, a circuit is designed to collect characteristic values to reset the wireless module main control and restore it to normal. In addition, by capturing the voltage change of the charging interface under USB charging state, the wireless module main control is further reset so that the terminal can achieve hardware power-on reset and restore to normal. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a novel combination reset circuit in view of the shortcomings of the background technology; the unidirectional conduction performance of the diode is utilized to realize the logic OR gate circuit, and a positive pulse is further generated through a differential circuit, and then a negative pulse is realized through a transistor inverting circuit, and finally the hardware power-on reset of the wireless module is realized, so that the wireless terminal can return to normal in the abnormal dead state before the watchdog initialization is completed.
[0004] The utility model adopts the following technical solutions to solve the above technical problems:
[0005] A novel combination reset circuit, including a fixed reference voltage, a module abnormal output characteristic voltage, a comparator circuit, a logic or gate circuit, a differential circuit, an inverting circuit, a negative pulse signal, a DC boost circuit, a wireless module power-on reset, and a USB insertion characteristic voltage;
[0006] Among them, the output end of the fixed reference voltage and the module abnormal output characteristic voltage is connected to the input end of the comparator circuit, the output end of the comparator circuit is connected to the input end of the logic OR gate circuit, the output end of the logic OR gate circuit is connected to the input end of the differential circuit, the output end of the differential circuit is connected to the input end of the inverting circuit, the output end of the inverting circuit is connected to the input end of the negative pulse signal, the output end of the negative pulse signal is connected to the enable signal input end of the DC boost circuit, the output end of the DC boost circuit is connected to the power supply input end of the wireless module, and the output end of the USB insertion characteristic voltage is connected to the input end of the logic OR gate circuit.
[0007] As a further preferred solution of a new combination reset circuit of the utility model, it also includes an LDO power supply module, which is used to provide the required electric energy. The LDO power supply module includes a chip U304, a capacitor C314, a resistor R311, and a capacitor; the interface 1 of the chip U304 is respectively connected to one end of the resistor R311 and one end of the capacitor C314, the other end of the capacitor C314 is grounded, the other end of the resistor R311 is connected to the interface 3 of the chip U304, the interface 5 of the chip U304 is connected to one end of the capacitor C313, and the other end of the capacitor C313 is grounded.
[0008] As a further preferred embodiment of a novel combination reset circuit of the utility model, the power-on reset of the wireless module includes a wireless module DC-DC power supply circuit, and the wireless module DC-DC power supply circuit includes a chip U306, a capacitor C317, a capacitor C316, an inductor L302, a resistor R315, a resistor R317, and a capacitor C312. The interface 1 of the chip U306 is connected to one end of the inductor L302, and the other end of the inductor L302 is respectively connected to the interface 6 of the chip U306, one end of the capacitor C316, and one end of the capacitor C317. The other end of the capacitor C316 is grounded, and the other end of the capacitor C317 is grounded. The interface 3 of the chip U306 is connected to one end of the resistor R315, and the other end of the resistor R315 is connected to the MAIN-PWREN end. The interface 4 of the chip U306 is connected to one end of the resistor R317 and is grounded. The interface 5 of the chip U306 is respectively connected to the other end of the resistor R317 and one end of the capacitor C312 and the 3.3V voltage end, and the other end of the capacitor C312 is grounded.
[0009] As a further preferred embodiment of a novel combination reset circuit of the utility model, the comparator circuit includes resistor R146, resistor R147, resistor R149, resistor R150, chip U305A, REF-3V0 terminal, NB-1V8 terminal, and 2V0-HIGH terminal, the REF-3V0 terminal is connected to one end of resistor R147, the other end of resistor R147 is respectively connected to one end of resistor R146 and interface 2 of chip U305A, the other end of resistor R146 is grounded, interface 1 of chip U305A is respectively connected to one end of resistor R150 and 2V0-HIGH terminal, the other end of resistor R150 is grounded, interface 3 of chip U305A is connected to one end of resistor R149, and the other end of resistor R149 is grounded.
[0010] As a further preferred embodiment of a novel combination reset circuit of the utility model, the logic or gate circuit, the differential circuit, and the inverting circuit include a 2V0-HIGH terminal, a USB-HIGH terminal, a diode D113, a diode D114, a capacitor C127, a resistor R145, a transistor Q112, a resistor R153, a REF-3V0 terminal, and a MAIN-PWREN terminal, wherein the 2V0-HIGH terminal is connected to the positive electrode of the diode D113, and the negative electrode of the diode D113 is connected to the positive electrode of the diode D113. The positive electrode of the diode D114 is connected to the USB-HIGH terminal, one end of the capacitor C127 is respectively connected to one end of the resistor R145 and the base of the transistor Q112, the other end of the resistor R145 is grounded, the emitter of the transistor Q112 is grounded, the electrodes of the transistor Q112 are respectively connected to one end of the resistor R153 and the MAIN-PWREN terminal, and the other end of the resistor R153 is connected to the REF-3V0 terminal.
[0011] Compared with the prior art, the utility model adopts the above technical solution and has the following technical effects:
[0012] The utility model discloses a novel combined reset circuit, which captures the voltage characteristic value of the wireless module outputted externally when the wireless module crashes abnormally and the voltage mutation when the USB charging interface is inserted, realizes the logic OR gate circuit by using the unidirectional conduction performance of the diode, further generates a positive pulse by using the differential circuit, and then realizes the negative pulse by using the transistor inversion circuit, finally realizes the hardware power-on reset of the wireless module, so that the wireless terminal recovers to normal in the abnormal crash state before the watchdog initialization is completed; utilizes the output characteristic voltage after the wireless module crashes abnormally and the level change hardware when the USB charging is inserted to power on the wireless module reset, automatically handles the crash of the wireless module before the watchdog initialization is completed, and the solution is realized by using mature components, with low cost and reliable performance, no software participation is required in the whole process, and the hardware is automatically realized, which is reliable and stable. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.
[0014] Figure 1 This is a structural principle diagram of a novel combined reset circuit of the utility model;
[0015] Figure 2 This is a timing waveform diagram of the utility model when the USB charging is inserted;
[0016] Figure 3 It is a timing waveform diagram of the wireless module of the utility model under abnormal characteristic voltage state;
[0017] Figure 4 It is a circuit diagram of the LDO power supply circuit of the utility model;
[0018] Figure 5 It is a circuit diagram of the DC-DC power supply circuit of the wireless module of the utility model;
[0019] Figure 6 This is a circuit diagram of the USB insertion characteristic voltage of the utility model;
[0020] Figure 7 It is a circuit diagram of the comparator circuit of the utility model;
[0021] Figure 8 The utility model is a circuit diagram of an OR gate, a differential circuit and an inverting circuit. DETAILED DESCRIPTION
[0022] The technical solution of the utility model is further described in detail below in conjunction with the accompanying drawings:
[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model. The utility model is described in detail below based on the drawings and preferred embodiments. The purpose and effect of the utility model will become clearer. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not used to limit the utility model.
[0024] The patent mainly aims at the situation that the wireless module cannot return to normal when it crashes abnormally before the hardware watchdog is initialized. It proposes a method of externally capturing the voltage characteristic value output by the wireless module when it crashes abnormally and the voltage mutation when the USB charging port is inserted, and realizing a logic OR gate circuit by using the unidirectional conduction performance of the diode. It further generates a positive pulse through a differential circuit, and then realizes a negative pulse through a transistor inversion circuit, and finally realizes the hardware power-on reset of the wireless module, so that the wireless terminal can return to normal in the abnormal crash state before the watchdog is initialized.
[0025] System framework diagram Figure 1 As shown in the figure, the USB insertion level change waveform and the timing waveform when the wireless module output voltage suddenly changes are as follows Figure 2 and Figure 3 shown.
[0026] A new combination reset circuit, such as Figure 1 As shown, it includes a fixed reference voltage, a module abnormal output characteristic voltage, a comparator circuit, a logic or gate circuit, a differential circuit, an inverting circuit, a negative pulse signal, a DC boost circuit, a wireless module power-on reset, and a USB insertion characteristic voltage;
[0027] Among them, the output end of the fixed reference voltage and the module abnormal output characteristic voltage is connected to the input end of the comparator circuit, the output end of the comparator circuit is connected to the input end of the logic OR gate circuit, the output end of the logic OR gate circuit is connected to the input end of the differential circuit, the output end of the differential circuit is connected to the input end of the inverting circuit, the output end of the inverting circuit is connected to the input end of the negative pulse signal, the output end of the negative pulse signal is connected to the DC boost circuit enable signal input end, the output end of the DC boost circuit is connected to the wireless module power supply input end, and the output end of the USB insertion characteristic voltage is connected to the input end of the logic OR gate circuit.
[0028] It also includes an LDO power supply module, which is used to provide the required power. Figure 4 As shown, the LDO power supply module includes a chip U304, a capacitor C314, a resistor R311, and a capacitor; the interface 1 of the chip U304 is respectively connected to one end of the resistor R311 and one end of the capacitor C314, the other end of the capacitor C314 is grounded, the other end of the resistor R311 is connected to the interface 3 of the chip U304, the interface 5 of the chip U304 is connected to one end of the capacitor C313, and the other end of the capacitor C313 is grounded.
[0029] Figure 6 This is a circuit diagram of the USB insertion characteristic voltage of the utility model; Figure 5 As shown, the power-on reset of the wireless module includes a wireless module DC-DC power supply circuit, and the wireless module DC-DC power supply circuit includes a chip U306, a capacitor C317, a capacitor C316, an inductor L302, a resistor R315, a resistor R317, and a capacitor C312. The interface 1 of the chip U306 is connected to one end of the inductor L302, and the other end of the inductor L302 is respectively connected to the interface 6 of the chip U306, one end of the capacitor C316, and one end of the capacitor C317. The other end of the capacitor C316 is grounded, and the other end of the capacitor C317 is grounded. The interface 3 of the chip U306 is connected to one end of the resistor R315, and the other end of the resistor R315 is connected to the MAIN-PWREN end. The interface 4 of the chip U306 is connected to one end of the resistor R317 and is grounded. The interface 5 of the chip U306 is respectively connected to the other end of the resistor R317 and one end of the capacitor C312 and the 3.3V voltage end, and the other end of the capacitor C312 is grounded.
[0030] like Figure 7As shown, the comparator circuit includes resistor R146, resistor R147, resistor R149, resistor R150, chip U305A, REF-3V0 terminal, NB-1V8 terminal, and 2V0-HIGH terminal, the REF-3V0 terminal is connected to one end of resistor R147, the other end of resistor R147 is respectively connected to one end of resistor R146 and interface 2 of chip U305A, the other end of resistor R146 is grounded, interface 1 of chip U305A is respectively connected to one end of resistor R150 and 2V0-HIGH terminal, the other end of resistor R150 is grounded, interface 3 of chip U305A is connected to one end of resistor R149, and the other end of resistor R149 is grounded.
[0031] like Figure 8 As shown, the logic OR gate circuit, the differential circuit, and the inverting circuit include a 2V0-HIGH terminal, a USB-HIGH terminal, a diode D113, a diode D114, a capacitor C127, a resistor R145, a transistor Q112, a resistor R153, a REF-3V0 terminal, and a MAIN-PWREN terminal. The 2V0-HIGH terminal is connected to the positive electrode of the diode D113, the negative electrode of the diode D113 is respectively connected to one end of the capacitor C127 and the negative electrode of the diode D114, the positive electrode of the diode D114 is connected to the USB-HIGH terminal, one end of the capacitor C127 is respectively connected to one end of the resistor R145 and the base of the transistor Q112, the other end of the resistor R145 is grounded, the emitter of the transistor Q112 is grounded, the electrodes of the transistor Q112 are respectively connected to one end of the resistor R153 and the MAIN-PWREN terminal, and the other end of the resistor R153 is connected to the REF-3V0 terminal.
[0032] The LDO power supply module is mainly used to supply power to each module circuit in the circuit. The comparison processing module is mainly used to capture the output characteristic voltage of the wireless module in the case of abnormal freeze and the voltage change when the USB charging head is inserted. The characteristic voltage output by the module is further captured through the comparator and the fixed reference voltage. The comparator output result and the level state when the USB is inserted are output to the differential circuit through the OR gate circuit to generate a positive pulse signal, and then a negative pulse signal is generated through the inverting circuit, which further drives the enable end of the DC boost circuit to control the wireless module to power on, reset and restart to return to normal.
[0033] This patent cleverly uses the output characteristic voltage after the wireless module abnormally freezes and the level change hardware when the USB charging is inserted to power on and reset the wireless module, and automatically handles the freeze of the wireless module before the watchdog initialization is completed. The solution is implemented using mature components, with low cost and reliable performance. No software participation is required throughout the process, and the hardware is automatically implemented, which is reliable and stable.
[0034] The wireless master control module is powered on by pure hardware circuits, which is highly reliable. External hardware circuits use low-cost mature devices with high cost performance. The solution does not require software participation, and is automatically implemented by hardware circuits when abnormalities occur, which is stable and reliable.
[0035] Those skilled in the art can understand that the above are only preferred examples of the utility model and are not intended to limit the utility model. Although the utility model is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the utility model should be included in the protection scope of the utility model. All technical features in this embodiment can be freely combined according to actual needs.
[0036] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A novel combination reset circuit, characterized in that: Contains fixed reference voltage, module abnormal output characteristic voltage, comparator circuit, logic OR gate circuit, differential circuit, inverting circuit, positive pulse signal, DC boost circuit, wireless module power-on reset, USB insertion characteristic voltage; Among them, the output end of the fixed reference voltage and the module abnormal output characteristic voltage is connected to the input end of the comparator circuit, the output end of the comparator circuit is connected to the input end of the logic OR gate circuit, the output end of the logic OR gate circuit is connected to the input end of the differential circuit, the output end of the differential circuit is connected to the input end of the inverting circuit, the output end of the inverting circuit is connected to the input end of the negative pulse signal, the output end of the negative pulse signal is connected to the enable signal input end of the DC boost circuit, the output end of the DC boost circuit is connected to the power supply input end of the wireless module, and the output end of the USB insertion characteristic voltage is connected to the input end of the logic OR gate circuit.
2. A novel combination reset circuit according to claim 1, characterized in that: It also includes an LDO power supply module, which is used to provide required electric energy. The LDO power supply module includes a chip U304, a capacitor C314, a resistor R311, and a capacitor; an interface 1 of the chip U304 is respectively connected to one end of the resistor R311 and one end of the capacitor C314, the other end of the capacitor C314 is grounded, the other end of the resistor R311 is connected to an interface 3 of the chip U304, and an interface 5 of the chip U304 is connected to one end of the capacitor C313, and the other end of the capacitor C313 is grounded.
3. A novel combination reset circuit according to claim 1, characterized in that: The power-on reset of the wireless module includes a wireless module DC-DC power supply circuit, and the wireless module DC-DC power supply circuit includes a chip U306, a capacitor C317, a capacitor C316, an inductor L302, a resistor R315, a resistor R317, and a capacitor C312. The interface 1 of the chip U306 is connected to one end of the inductor L302, and the other end of the inductor L302 is respectively connected to the interface 6 of the chip U306, one end of the capacitor C316, and one end of the capacitor C317. The other end of the capacitor C316 is grounded, and the other end of the capacitor C317 is grounded. The interface 3 of the chip U306 is connected to one end of the resistor R315, and the other end of the resistor R315 is connected to the MAIN-PWREN end. The interface 4 of the chip U306 is connected to one end of the resistor R317 and is grounded. The interface 5 of the chip U306 is respectively connected to the other end of the resistor R317 and one end of the capacitor C312 and the 3.3V voltage end, and the other end of the capacitor C312 is grounded.
4. A novel combination reset circuit according to claim 1, characterized in that: The comparator circuit includes resistor R146, resistor R147, resistor R149, resistor R150, chip U305A, REF-3V0 terminal, NB-1V8 terminal, and 2V0-HIGH terminal. The REF-3V0 terminal is connected to one end of resistor R147, the other end of resistor R147 is respectively connected to one end of resistor R146 and interface 2 of chip U305A, the other end of resistor R146 is grounded, interface 1 of chip U305A is respectively connected to one end of resistor R150 and 2V0-HIGH terminal, the other end of resistor R150 is grounded, interface 3 of chip U305A is connected to one end of resistor R149, and the other end of resistor R149 is grounded.
5. A novel combination reset circuit according to claim 1, characterized in that: The logic OR gate circuit, the differential circuit, and the inverting circuit include a 2V0-HIGH terminal, a USB-HIGH terminal, a diode D113, a diode D114, a capacitor C127, a resistor R145, a transistor Q112, a resistor R153, a REF-3V0 terminal, and a MAIN-PWREN terminal. The 2V0-HIGH terminal is connected to the positive electrode of the diode D113, the negative electrode of the diode D113 is respectively connected to one end of the capacitor C127 and the negative electrode of the diode D114, the positive electrode of the diode D114 is connected to the USB-HIGH terminal, one end of the capacitor C127 is respectively connected to one end of the resistor R145 and the base of the transistor Q112, the other end of the resistor R145 is grounded, the emitter of the transistor Q112 is grounded, the electrodes of the transistor Q112 are respectively connected to one end of the resistor R153 and the MAIN-PWREN terminal, and the other end of the resistor R153 is connected to the REF-3V0 terminal.