High-sensitivity optical communication TIA chip
Through the use of external seals and thermal cover structures in TIA chip packaging, combined with the solid seal layer and thermal silicon grease layer, the problem of insufficient chip heat dissipation performance is solved, and the effect of high -efficiency heat dissipation and compact structure is suitable for miniaturization equipment.
Patent Information
- Application Number
- CN202323015793.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-08
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2033-11-08
AI Technical Summary
With the trend of miniaturization of TIA chip packaging technology, the heat dissipation performance of the chip is gradually insufficient, resulting in the reverse increase in performance power consumption when the volume is getting smaller and smaller, and more heat dissipation structures are needed to solve the heat dissipation problem.
The packaging structure adopts an outer frame and two sets of thermally conductive covers. The thermally conductive cover includes a solid sealing layer and a thermally conductive silicone grease layer. The solidifying layer is in direct contact with the core of the TIA chip. The thermally conductive silicone grease layer is connected to the solidifying layer and is connected through the reinforcement layer and Mesh grid layer enhances thermal conductivity efficiency.
While ensuring the stability of the package, it achieves a compact structure, maximizes the heat dissipation area and efficiency, solves the problem of insufficient chip heat dissipation performance, and is suitable for miniaturized equipment.
Smart Images
Figure CN222396023U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of TIA chips, and more specifically to a high-sensitivity optical communication TIA chip. Background Art
[0002] TIA chips are widely used in many fields. The most common fields are optical communication and fiber optic sensing. In the field of optical communication, TIA chips convert the optical signal received by the optical fiber receiver into an electrical signal, which is then digitized by a demodulator and finally transmitted to the target location. In the field of fiber optic sensing, TIA chips can convert the optical signal collected by the fiber optic sensor into an electrical signal for further analysis and processing. TIA chips are also widely used in medical equipment, such as electrocardiographs, oral oximeters, etc.
[0003] As the trend of equipment miniaturization becomes more and more popular, the packaging technology of TIA chips tends to be more miniaturized and applied to smaller and more diversified devices. However, due to the smaller and smaller size and the reverse increase in performance and power consumption, the heat dissipation of the packaged chip requires the installation of more heat dissipation structures, and its own heat dissipation performance is increasingly insufficient. Utility Model Content
[0004] The utility model aims to solve the problems existing in the prior art and provides a high-sensitivity optical communication TIA chip, which ensures the stability of the package while making the structure more compact and improving the heat dissipation performance of the packaged chip.
[0005] To achieve the above purpose, the utility model adopts the following technical solution.
[0006] A high-sensitivity optical communication TIA chip comprises a TIA chip core, wherein the four edges of the TIA chip core are fixedly connected with conductive modules, the outer side of the conductive module is fixedly connected with an outer sealing frame, two groups of thermal conductive covers are installed on the outer sealing frame, the two thermal conductive covers are respectively located at the top and bottom of the TIA chip core, and a reinforcement layer is fixedly connected to the side of the thermal conductive cover away from the TIA chip core.
[0007] As a further description of the above technical solution: the thermal conductive cover comprises a sealing layer and a thermal conductive silicone grease layer, one side of the sealing layer is directly contacted and fixed with the TIA chip core, and one side of the thermal conductive silicone grease layer is fixedly connected to the sealing layer.
[0008] As a further description of the above technical solution: the sealing layer is provided with evenly distributed through holes, the bottom of the thermal grease layer is provided with bumps that engage with the through holes, and the ends of the bumps are in contact with the surface of the TIA chip core.
[0009] As a further description of the above technical solution: the reinforcement layer is located in the horizontally and vertically staggered mesh grid layer, and the outer side of the reinforcement layer is fixedly connected to the outer sealing frame.
[0010] As a further description of the above technical solution: the bottom of the conductive module is fixedly connected with an external pin, and the bottom end of the external pin is plugged into the bottom of the outer sealing frame.
[0011] Compared with the prior art, the advantages of the present invention are:
[0012] This solution uses a packaging structure with an external packaging frame and two heat-conducting cover layers to ensure packaging stability while making the structure more compact and maximizing the external heat dissipation area to ensure heat dissipation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a front view cross-sectional structural schematic diagram of the utility model;
[0014] Figure 2 for Figure 1 A schematic diagram of the enlarged structure of the middle part A;
[0015] Figure 3 It is a schematic diagram of the top view structure of the utility model;
[0016] Figure 4 It is a schematic diagram of a partial three-dimensional split structure of the utility model.
[0017] Description of the numbers in the figure:
[0018] 1. TIA chip core; 2. Conductive module; 21. External pins; 3. External packaging frame; 4. Thermal conductive cover; 41. Solid sealing layer; 411. Through hole; 42. Thermal conductive silicone grease layer; 421. Bump; 5. Reinforcement layer. DETAILED DESCRIPTION
[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention;
[0020] See also Figures 1 to 4 In the utility model, a high-sensitivity optical communication TIA chip includes a TIA chip core 1, a conductive module 2 is fixedly connected to the four edges of the TIA chip core 1, an outer sealing frame 3 is fixedly connected to the outer side of the conductive module 2, two sets of thermal conductive covers 4 are installed on the outer sealing frame 3, the two thermal conductive covers 4 are respectively located at the top and bottom of the TIA chip core 1, and a reinforcement layer 5 is fixedly connected to the side of the thermal conductive cover 4 away from the TIA chip core 1.
[0021] In the utility model, the conductive modules 2 on the four edges of the TIA chip core 1 are connected and packaged through the outer packaging frame 3 to form a packaging main frame, and then the top and bottom surfaces of the TIA chip core 1 are reinforced and packaged through the thermal conductive cover 4, and the chip thermal conductive surface is maximized. The thermal conductive cover 4 is reinforced by the reinforcement layer, and a stable packaging shell is formed in cooperation with the outer packaging frame 3, so that the device has the advantages of ensuring a larger heat dissipation area and efficiency, and a more compact structure, which is suitable for installation and use in miniaturized equipment. It solves the problem in the prior art that due to the smaller and smaller volume and the reverse increase in performance and power consumption, the heat dissipation of the packaged chip requires the installation of more heat dissipation structures, and the heat dissipation performance of the packaged chip itself is increasingly insufficient.
[0022] See also Figure 2 and Figure 4 , wherein: the thermal conductive cover 4 includes a sealing layer 41 and a thermal conductive silicone grease layer 42 , one side of the sealing layer 41 is directly contacted and fixed with the TIA chip core 1 , and one side of the thermal conductive silicone grease layer 42 is fixedly connected to the sealing layer 41 .
[0023] In the present invention, the surface of the TIA chip core 1 is packaged and reinforced by the sealing layer 41 and the thermal grease layer 42, while ensuring the maximum external heat dissipation area to ensure efficient heat dissipation.
[0024] See also Figure 2 and Figure 4 , wherein: the sealing layer 41 is provided with evenly distributed through holes 411 , the bottom of the thermal grease layer 42 is provided with bumps 421 engaged with the through holes 411 , and the ends of the bumps 421 are in contact with the surface of the TIA chip core 1 .
[0025] In the present invention, the through hole 411 cooperates with the bump 421 to make the heat conduction efficiency of the device higher.
[0026] See also Figure 2 and Figure 3 , wherein: the reinforcement layer 5 is located in the mesh grid layer that is staggered horizontally and vertically, and the outer side of the reinforcement layer 5 is fixedly connected to the outer sealing frame 3.
[0027] In the utility model, the thermal grease layer 42 is stabilized by the reinforcement layer 5 in the shape of a mesh grid, and the structure of the mesh grid also ensures the heat conduction and heat dissipation efficiency of the thermal grease layer 42 .
[0028] See also Figure 1 , wherein: an external pin 21 is fixedly connected to the bottom of the conductive module 2 , and the bottom end of the external pin 21 is plugged into the bottom of the outer sealing frame 3 .
[0029] In the utility model, the external connection pin 21 is used to facilitate the external circuit.
[0030] The above is only a preferred specific implementation of the utility model; however, the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solution and improved ideas of the utility model within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model.
Claims
1. A high-sensitivity optical communication TIA chip, comprising a TIA chip core (1), characterized in that: The four edges of the TIA chip core (1) are fixedly connected to conductive modules (2), the outer side of the conductive module (2) is fixedly connected to an outer sealing frame (3), two groups of thermal conductive covers (4) are mounted on the outer sealing frame (3), the two thermal conductive covers (4) are respectively located at the top and bottom of the TIA chip core (1), and a reinforcement layer (5) is fixedly connected to the side of the thermal conductive cover (4) away from the TIA chip core (1).
2. A high-sensitivity optical communication TIA chip according to claim 1, characterized in that: The thermally conductive cover (4) comprises a sealing layer (41) and a thermally conductive silicone grease layer (42); one side of the sealing layer (41) is in direct contact with and fixed to the TIA chip core (1); and one side of the thermally conductive silicone grease layer (42) is fixedly connected to the sealing layer (41).
3. A high-sensitivity optical communication TIA chip according to claim 2, characterized in that: The sealing layer (41) is provided with evenly distributed through holes (411), the bottom of the thermal conductive silicone grease layer (42) is provided with a bump (421) that is snap-fitted with the through holes (411), and the end of the bump (421) is in contact with the surface of the TIA chip core (1).
4. The high-sensitivity optical communication TIA chip according to claim 1, characterized in that: The reinforcement layer (5) is located in the mesh grid layer that is staggered in the horizontal and vertical directions, and the outer side of the reinforcement layer (5) is fixedly connected to the outer sealing frame (3).
5. The high-sensitivity optical communication TIA chip according to claim 1, characterized in that: An external pin (21) is fixedly connected to the bottom of the conductive module (2), and the bottom end of the external pin (21) is plugged into the bottom of the outer sealing frame (3).