Package structure

Abstract

A package structure includes a substrate having a front side surface and a back side surface, and an electronic device formed on the front side surface of the substrate. The package structure includes a dielectric layer formed under and in direct contact with the backside surface of the substrate, and a first optical device formed within the dielectric layer. The package structure also includes a protection layer formed below or above the first optical device and a photoelectric effect material layer formed within the protection layer.

Description

Technical Field

[0001] The utility model relates to a semiconductor technology, in particular to a packaging structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material on a semiconductor substrate, and patterning the various material layers using photolithography techniques to form circuit components and elements thereon. Many integrated circuits are typically fabricated on a single semiconductor wafer, with individual chips on the wafer singulated by sawing along dicing lanes between the integrated circuits. Individual chips are typically packaged separately in multi-chip modules or other packaging types.

[0003] New packaging technologies have been developed, such as package on package (PoP), in which a top package with a device die is bonded to a bottom package with another device die. By adopting new packaging technologies, various packages with different or similar functions can be integrated together.

[0004] Although existing package structures and methods of making package structures are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Utility Model Content

[0005] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0006] In some embodiments, a package structure is provided, comprising: a substrate having a front surface and a back surface, and an electronic device formed on the front surface of the substrate. The package structure also comprises a first optical device formed below the back surface of the substrate and a protective layer formed below or above the first optical device. The package structure also comprises a photoelectric effect material layer formed in the protective layer.

[0007] According to one embodiment of the present invention, the device further comprises: a dielectric layer formed below the back surface of the substrate and in direct contact with the back surface; and an optical fiber adjacent to the first optical device.

[0008] According to one embodiment of the present invention, it further includes: a second optical device formed below the first optical device.

[0009] According to one embodiment of the utility model, it also includes: a substrate via structure connected to the electronic device and the photoelectric effect material layer; a plurality of nanostructures formed on the substrate; and a source / drain structure connected to the plurality of nanostructures, wherein the substrate via structure is connected to the source / drain structure.

[0010] According to one embodiment of the present invention, the first optical device includes an optical waveguide or a coupler.

[0011] In some embodiments, a package structure is provided, including: an optical interposer and a first die formed on the optical interposer. The first die includes an electronic device, a first optical device formed below the electronic device, and a graphene layer formed above or below the first optical device.

[0012] According to one embodiment of the present invention, the invention further includes: a bonding structure located between the optical intermediary layer and the first die, wherein the bonding structure includes a first bonding layer bonded to a second bonding layer, and a first conductive pad bonded to a second conductive pad.

[0013] According to one embodiment of the present invention, the optical device further comprises: a first grating coupler formed in the first crystal grain; and a second grating coupler formed in the optical intermediary layer.

[0014] According to one embodiment of the present invention, it further includes: an optical fiber formed adjacent to the first optical device or adjacent to an upper surface of the optical intermediate layer.

[0015] According to one embodiment of the present invention, it further includes: a second optical device formed below the graphene layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic perspective view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0017] FIG. 2A to FIG. 2C According to some embodiments of the present disclosure, Figure 1 The cross-sectional view of the semiconductor structure at various manufacturing stages is shown along the AA' line.

[0018] Figures 3A to 3G Schematic cross-sectional views showing various stages of forming a package structure according to some embodiments of the present disclosure.

[0019] Figure 4 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0020] Figure 5A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0021] Figure 6A-6F Schematic cross-sectional views showing various stages of forming a package structure according to some embodiments of the present disclosure.

[0022] Figure 7 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0023] Figure 8 FIG. 4 is a schematic cross-sectional view of a package structure 100 f according to some embodiments of the present disclosure.

[0024] Figure 9A-9D Schematic cross-sectional views showing various stages of forming a package structure according to some embodiments of the present disclosure.

[0025] Fig.10 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0026] Fig.11 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0027] Figure 12A-12C Schematic cross-sectional views showing various stages of forming a package structure according to some embodiments of the present disclosure.

[0028] Fig.13 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0029] Fig.14 A schematic cross-sectional view of a package structure according to some embodiments of the present disclosure is shown.

[0030] The reference numerals are as follows:

[0031] 100:Semiconductor device structure

[0032] 101: Base

[0033] 106: first semiconductor layer

[0034] 108: Second semiconductor layer

[0035] 112: Fin structure

[0036] 114: Groove

[0037] 116: Well Area Department

[0038] 118: Insulation material

[0039] 120: Isolation Area

[0040] 130: Sacrificial gate structure

[0041] 132: Sacrificial gate dielectric layer

[0042] 134: Sacrificial gate electrode layer

[0043] 136: mask layer

[0044] 138: Gate spacer

[0045] 144: Dielectric spacer layer

[0046] 146, 146n, 146p: Source / drain (S / D) region

[0047] 162,184: Contact Etch Stop Layer (CESL)

[0048] 163: first interlayer dielectric (ILD) layer

[0049] 164: Sacrificial dielectric layer

[0050] 170: Gate dielectric layer

[0051] 171: Covering layer

[0052] 172: Gate electrode layer

[0053] 174: Gate structure

[0054] 180: Silicide layer

[0055] 186: Second interlayer dielectric (ILD) layer

[0056] 188: Conductive contact

[0057] 202:Hard mask

[0058] 204,208: Opening

[0059] 206,210: Dielectric materials DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure is a specific example describing each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0061] Some variations of embodiments of the present invention are described below. In each view and illustrative embodiment, similar reference numerals are used to designate similar elements. It should be understood that additional operations may be provided before, during, and after this method, and for other embodiments of this method, some of the operations described may be replaced or removed.

[0062] The gate all around (GAA) transistor structure described below can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the formed pattern to have, for example, a smaller pitch than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern a gate all around (GAA) structure.

[0063] The fins described below may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the formed patterns to have, for example, smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins.

[0064] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows testing of the 3D package or 3DIC, using probes and / or probe cards or the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known qualified die to improve yield and reduce costs.

[0065] Embodiments of package structures and methods for forming the same are provided herein. An electronic device and an optical device are formed on two opposite sidewall surfaces of a substrate. The substrate may be a wafer, and the electronic device (e.g., a semiconductor device) and the optical device (e.g., a first optical device and a photoelectric effect material layer) are integrated into a wafer. Since the electronic device and the optical device are formed on a single wafer or chip, rather than on different chips, the passage of electronic signals and optical signals is reduced, and the transmission speed of the electronic signals and optical signals is increased.

[0066] Figure 1 A schematic perspective view of a semiconductor structure 10 according to some embodiments of the present disclosure is shown. The semiconductor structure 10 is an electronic device.

[0067] Please refer to Figure 1 , a substrate 102 is provided. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0068] In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are alternately stacked on the substrate 102. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure may include more or less first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and second semiconductor material layers.

[0069] The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed by low-pressure chemical vapor deposition (LPCVD), an epitaxial growth process, another suitable method or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD) or vapor phase epitaxy (VPE).

[0070] According to some embodiments, after forming the first semiconductor material layer 106 and the second semiconductor material layer 108 as a semiconductor material stack on the substrate 102, the semiconductor material stack is patterned to form a fin structure 104. In some embodiments, the fin structure 104 includes a base fin structure 104B and a semiconductor material stack consisting of the first semiconductor material layer 106 and the second semiconductor material layer 108.

[0071] After forming the fin structure 104, an isolation structure 116 is formed around the fin structure 104. After forming the isolation structure 116, a dummy gate structure 118 is formed across the fin structure 104 and extending on the isolation structure 116. The dummy gate structure 118 can be used to define the source / drain region and the channel region of the final semiconductor structure 10.

[0072] In some embodiments, the dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 120 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic vapor deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0073] In some embodiments, the dummy gate electrode layer 122 includes a conductive material. In some embodiments, the conductive material includes polysilicon (poly-Si), polysilicon-germanium (poly-SiGe), metal nitride, metal silicide, metal, or a combination thereof. In some embodiments, the dummy gate electrode layer 122 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof.

[0074] In some embodiments, a hard mask layer 124 is formed on the dummy gate structure 118. In some embodiments, the hard mask layer 124 includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide, and the nitride layer is silicon nitride.

[0075] According to some embodiments, after forming the dummy gate structure 118, gate spacers 126 are formed along and cover opposite sidewall surfaces of the dummy gate structure 118, and fin spacers 128 are formed along and cover opposite sidewall surfaces of the source / drain (S / D) region of the fin structure 104. The source / drain (S / D) structure or region may be referred to as a source or a drain, individually or collectively depending on the context.

[0076] The gate spacer 126 may be used to separate the source / drain (S / D) structure from the dummy gate structure 118 and support the dummy gate structure 118 , and the fin spacer 128 may be used to limit the lateral growth of the subsequently formed source / drain (S / D) structure and support the fin structure 104 .

[0077] In some embodiments, the gate spacer 126 and the fin spacer 128 are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or a combination thereof. The formation of the gate spacer 126 and the fin spacer 128 may include conformally depositing a dielectric material covering the dummy gate structure 118, the fin structure 104, and the isolation structure 116 on the substrate 102, and performing an anisotropic etching process, such as dry plasma etching, to remove a portion of the dielectric layer covering the upper surface of the dummy gate structure 118, the fin structure 104, and the isolation structure 116.

[0078] FIG. 2A to FIG. 2C According to some embodiments, Figure 1 The AA′ line in FIG. 2 is a schematic cross-sectional view of the semiconductor structure 10 at various manufacturing stages.

[0079] like Figure 2A As shown, a dummy gate structure 118 is formed on the fin structure 104. A gate spacer 126 is formed on the sidewall surface of the dummy gate structure 118. The dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122.

[0080] Next, if Figure 2B As shown, according to some embodiments, the source / drain (S / D) region of the fin structure 104 is recessed to form a source / drain (S / D) groove (not shown). Specifically, the portions of the first semiconductor material layer 106 and the second semiconductor material layer 108 not covered by the dummy gate structure 118 and the gate spacer 126 are removed.

[0081] According to some embodiments, after forming the source / drain (S / D) grooves, the first semiconductor material layer 106 exposed by the source / drain (S / D) grooves is laterally recessed to form a notch (not shown), and an inner spacer layer 134 is formed in the notch between the second semiconductor material layers 108.

[0082] According to some embodiments, the inner spacer layer 134 is used to separate the source / drain (S / D) structure and the gate structure formed in the subsequent manufacturing process. In some embodiments, the inner spacer layer 134 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination thereof. In some embodiments, the inner spacer layer 134 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, another suitable process, or a combination thereof.

[0083] After forming the inner spacer layer 134, a source / drain (S / D) structure 136 is formed in the source / drain (S / D) groove. In some embodiments, the source / drain (S / D) structure 136 is formed using an epitaxial growth process, such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), other suitable epitaxial growth processes or combinations thereof. In some embodiments, the source / drain (S / D) structure 136 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP or combinations thereof.

[0084] In some embodiments, the source / drain (S / D) structure 136 is in-situ doped during the epitaxial growth process. For example, the source / drain (S / D) structure 136 can be epitaxially grown SiGe doped with boron (B). For example, the source / drain (S / D) structure 136 can be epitaxially grown Si doped with carbon to form a silicon:carbon (Si:C) source / drain feature component, epitaxially grown Si doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain feature component, or epitaxially grown Si doped with both carbon and phosphorus to form a silicon carbon phosphorus (SiCP) source / drain feature component. In some embodiments, the source / drain (S / D) structure 136 is doped in one or more implantation processes after the epitaxial growth process.

[0085] Afterwards, if Figure 2C As shown, according to some embodiments, after forming the source / drain (S / D) structure 136, a contact etch stop layer (CESL) 138 is conformally formed to cover the source / drain (S / D) structure 136, and an interlayer dielectric (ILD) layer 140 is formed on the contact etch stop layer (CESL) 138.

[0086] In some embodiments, the contact etch stop layer (CESL) 138 includes a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layer (CESL) 138 can be conformally deposited on the semiconductor structure by chemical vapor deposition (CVD), atomic layer deposition (ALD), other application methods, or a combination thereof.

[0087] The interlayer dielectric (ILD) layer 140 may include multiple layers made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) and / or other suitable low-k dielectric materials. The interlayer dielectric (ILD) layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0088] According to some embodiments, the dummy gate structure 118 is replaced by the gate structure 142. Specifically, according to some embodiments, the dummy gate structure 118 and the first semiconductor material layer 106 are removed to form the nanostructure 108' using the second semiconductor material layer 108. The source / drain (S / D) structure 136 is connected to the nanostructure 108'.

[0089] According to some embodiments, the gate structure 142 surrounds the nanostructure 108 ′ to form a gate-all-around transistor structure. In some embodiments, the gate structure 142 includes an interface layer 144 , a gate dielectric layer 146 , and a gate electrode layer 148 .

[0090] In some embodiments, the interface layer 144 is an oxide layer surrounding the nanostructure 108' and formed on top of the base fin structure 104B. In some embodiments, the interface layer 144 is formed by performing a thermal process.

[0091] In some embodiments, the gate dielectric layer 146 is formed on the interface layer 144 so that the nanostructure 108' is surrounded (e.g., enclosed) by the gate dielectric layer 146. In addition, according to some embodiments, the gate dielectric layer 146 also covers the sidewalls of the gate spacer 126 and the sidewalls of the inner spacer layer 134. In some embodiments, the gate dielectric layer 146 includes one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer 146 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof.

[0092] In some embodiments, the gate electrode layer 148 is formed on the gate dielectric layer 146. In some embodiments, the gate electrode layer 148 includes one or more conductive material layers, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 148 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, another suitable method, or a combination thereof. Other conductive layers, such as work function metal layers, may also be formed within the gate structure 142, although they are not shown in the drawings. In some embodiments, the n-type work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination thereof. In some embodiments, the p-type work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride, tungsten nitride (WN), ruthenium (Ru), or a combination thereof.

[0093] Figure 3A-3G Schematic cross-sectional views showing various stages of forming a package structure 100 a according to some embodiments of the present disclosure.

[0094] like Figure 3A As shown, the substrate 102 has a front surface 102a and a back surface 102b. The semiconductor structure 10 is formed on the front surface 102a of the substrate 102. For the sake of clarity, some elements of the semiconductor structure 10 are not shown. The detailed structure of the semiconductor structure 10 can be referred to Figure 2C The number of semiconductor structures 10 can be adjusted according to actual applications.

[0095] A dielectric layer 152 is formed on the ILD layer 140, and a contact structure 154 is formed in the dielectric layer 152. The contact structure 154 is formed on the gate electrode layer 148 of the gate structure 142 and directly contacts therewith.

[0096] The dielectric layer 152 may include multiple layers made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) and / or other suitable low-K dielectric materials. The dielectric layer 152 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0097] The contact structure 154 includes a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt (Co), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum nitride (TaSiN), tantalum nitride carbide (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials or combinations thereof. In some embodiments, the contact structure 154 can be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0098] Next, if Figure 3BAs shown, according to some embodiments of the present disclosure, an interconnect structure 160 is formed on the dielectric layer 152. The interconnect structure 160 is a front-side interconnect structure. The interconnect structure 160 is formed in the back-end-of-line (BEOL). The interconnect structure 160 can be used as a redistribution layer (RDL) structure for wiring.

[0099] The interconnect structure 160 includes a conductive layer 162, a contact plug 164, and a dielectric layer 166. The conductive layer 162 and the contact plug 164 are buried in the dielectric layer 166. In some embodiments, the conductive layer 162 and the contact plug 164 are made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, a combination thereof, or other suitable materials. In some embodiments, the conductive layer 162 and the contact plug 164 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another suitable deposition process.

[0100] Afterwards, if Figure 3C As shown, according to some embodiments of the present disclosure, the inverted Figure 3B The structure shown is attached to a carrier substrate 170. In some embodiments, the dielectric layer 166 is attached to the carrier substrate 170 by an adhesive layer (not shown). The adhesive layer is used as a temporary adhesive layer. The adhesive layer can be glue or tape. In some embodiments, the adhesive layer is photosensitive and can be easily peeled off from the carrier substrate 170 by light irradiation. For example, the carrier substrate 170 is irradiated with ultraviolet (UV) light or laser to peel off the adhesive layer. In other embodiments, the adhesive layer is heat-sensitive and can be easily peeled off from the carrier substrate 170 when it is heated.

[0101] The carrier substrate 170 is used to provide temporary mechanical and structural support in subsequent process steps. The carrier substrate 170 includes glass, silicon oxide, aluminum oxide, metal, combinations thereof and / or the like.

[0102] Next, according to some embodiments of the present disclosure, the substrate 102 is thinned using the carrier substrate 170 as a support. In some embodiments, the substrate 102 is thinned starting from the back surface 102b. In some embodiments, the remaining substrate 102 is approximately in the range of 5nm to 100nm. In some other embodiments, the substrate 102 is completely removed.

[0103] Next, if Figure 3DAs shown, according to some embodiments of the present disclosure, a dielectric layer 172 is formed on and in direct contact with the backside surface 102b of the substrate 102, and then a through-substrate via (TSV) structure 174 is formed through the dielectric layer 172 and the substrate 102. The through-substrate via (TSV) structure 174 may be referred to as a silicon via. Specifically, the through-substrate via (TSV) structure 174 penetrates the dielectric layer 172 and the substrate 102. In some embodiments, some of the through-substrate via (TSV) structures 174 are connected to and in direct contact with the source / drain (S / D) structure 136. In some embodiments, some of the through-substrate via (TSV) structures 174 are in direct contact with the conductive plug 164, and some of the through-substrate via (TSV) structures 174 are connected to the conductive layer 162 through the conductive plug 164.

[0104] The substrate through-hole (TSV) structure 174 is formed by forming a number of trenches (not shown) extending from the backside surface 102b of the substrate 102 to the upper surface of the dielectric layer 172. Afterwards, a liner (not shown) and a barrier layer (not shown) are filled into each trench, and a conductive material is formed on the barrier layer and in each trench. Next, once the trenches are filled, the excess liner, barrier layer and conductive material are removed by a planarization process (e.g., a chemical mechanical polishing (CMP) process).

[0105] In some embodiments, the liner includes silicon nitride, however any other suitable dielectric material may be used as an alternative. In some embodiments, the barrier layer includes tantalum nitride, however other materials such as tantalum, titanium, titanium nitride or the like may also be used. In some embodiments, the conductive material of the substrate through hole (TSV) structure 174 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. The liner, barrier layer and conductive material may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or another suitable deposition process. In some embodiments, each of the substrate through hole (TSV) structures 174 has a width in the range of approximately 15nm to 300nm.

[0106] Afterwards, if Figure 3EAs shown, according to some embodiments of the present disclosure, a dielectric layer 178 is formed on and in direct contact with the dielectric layer 172, and a first optical device 180, a conductive layer 182, and a contact plug 184 are formed in the dielectric layer 178. The first optical device 180 is used to transmit an optical signal. The first optical device 180 provides an optical medium for optical transmission. The optical signal can be collected and guided by the first optical device 180. The first optical device 180 can be controlled by the semiconductor device 10.

[0107] In some embodiments, dielectric layer 178 includes a low-k dielectric material and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide.

[0108] The first optical device 180 may be an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a buried channel waveguide, a diffused waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler, etc.), or the like. In some embodiments, the first optical device 180 is a waveguide made of silicon nitride (SiN). In some embodiments, the material of the first optical device 180 may be a translucent material.

[0109] In some embodiments, the first optical device 180 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or other suitable deposition processes. The first optical device 180 can be formed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0110] In some embodiments, the conductive layer 182 and the contact plug 184 are made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, a combination thereof, or other suitable materials. In some embodiments, the conductive layer 182 and the contact plug 184 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another suitable deposition process.

[0111] Afterwards, if Figure 3F As shown, according to some embodiments of the present disclosure, a photoelectric effect material layer 186, a conductive layer 187 and a protective layer 188 are formed. The photoelectric effect material layer 186 and the conductive layer 187 are buried in the protective layer 188. The photoelectric effect material layer 186 is in direct contact with the conductive layer 187 to transmit optical signals. The protective layer 188 is used to protect the photoelectric effect material layer 186. The photoelectric effect material layer 186 is electrically connected to the source / drain (S / D) structure 136 of the semiconductor structure 10 through the conductive plug 184, the conductive layer 182 and the substrate through-hole (TSV) structure 174.

[0112] It should be noted that the first optical device 180 and the photoelectric effect material layer 186 are formed on the back surface 102b of the substrate 102 for transmitting optical signals, and the photoelectric effect material layer 186 is electrically connected to the source / drain (S / D) structure 136 of the semiconductor structure 10 through the conductive layer 187, the conductive plug 184, the conductive layer 182 and the substrate through-hole (TSV) structure 174 for transmitting the electronic signal of the semiconductor structure 10.

[0113] In some embodiments, the photoelectric effect material layer 186 includes graphene. In some embodiments, the photoelectric effect material layer 186 is a two-dimensional material. The photoelectric effect material layer 186 can be one or more layers according to the actual application. In some embodiments, the photoelectric effect material layer 186 is a single layer and is attached or bonded to the dielectric layer 178. In some embodiments, the photoelectric effect material layer 186 is made of graphene, and the thickness of the single layer of graphene is about 0.35nm.

[0114] In some embodiments, the conductive layer 187 includes a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, a combination thereof, or another suitable material. In some embodiments, the protective layer 188 includes aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), or a combination thereof. In some embodiments, the conductive layer 187 and the protective layer 188 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0115] Afterwards, if Figure 3G As shown, according to some embodiments of the present disclosure, an internal connection structure 190 is formed on the protective layer 188. Next, for the sake of clarity, the Figure 3G The front-side interconnect structure 160 is formed above the semiconductor device 10, and the back-side interconnect structure 190 is formed below the protection layer 188.

[0116] The interconnect structure 190 includes a contact plug 192, a conductive layer 194, a dielectric layer 196, a UBM layer 197, and a conductive connector 198. The contact plug 192 and the conductive layer 194 are buried in the dielectric layer 196. In some embodiments, the contact plug 192 and the conductive layer 194 include a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, a combination thereof, or other suitable materials. In some embodiments, the contact plug 192 and the conductive layer 194 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another suitable deposition process.

[0117] In some embodiments, the UBM layer 197 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), nickel (Ni), gold (Au), chromium (Cr), copper (Cu), copper alloy, another suitable material or a combination thereof. In some embodiments, the conductive connector 198 includes copper (Cu), copper alloy or another suitable material. In some embodiments, the UBM layer 197 and the conductive connector 198 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or another suitable deposition process.

[0118] The thickness of the conductive layer 194 of the interconnect structure 190 is greater than the thickness of the conductive layer 162 of the interconnect structure 160. The thick conductive layer 194 has a low resistance to provide a fast path for power and ground. In addition, the power delivery network (PDN) is also improved.

[0119] like Figure 3G As shown, the first region 11, the second region 12 and the third region 13 have different functions. The first region 11 is a phase shifter region, and the refractive index of the photoelectric effect material layer 186 can be changed by providing different voltages. In addition, the photoelectric effect material layer 186 can be controlled by the semiconductor device 10 through the substrate through-hole (TSV) structure 174. The second region 12 is a heater region, and the refractive index of the photoelectric effect material layer 186 can be changed by a heating process. The third region 13 is a photodetector region, and the photoelectric effect material layer 186 is a sensor of light or other electromagnetic radiation.

[0120] The semiconductor device 10 is formed on the front surface 102a of the substrate 102, and the first optical device 180 and the photoelectric effect material layer 186 buried in the protective layer 188 are formed on the back surface 102b of the substrate 102. The semiconductor device 10 can receive and process electronic signals, and the first optical device 180 and the photoelectric effect material layer 186 can receive and process optical signals. The substrate 102 can be a chip, and the electronic device (e.g., the semiconductor device 10) and the optical device (e.g., the first optical device 180 and the photoelectric effect material layer 186) are integrated into a chip. It should be noted that there is no bonding layer between the electronic device (such as the semiconductor device 10) and the optical device (such as the first optical device 180 and the photoelectric effect material layer 186). Since the electronic device and the optical device are formed on a single chip or chip, rather than on different chips, the channels of the electronic signal and the optical signal are reduced. In other words, the wiring of the optical signal or the electronic signal is reduced. Therefore, the transmission speed of the electronic signal and the optical signal can be improved.

[0121] Furthermore, the back-side inner connection structure 190 and the first optical device 180 are formed on the back-side surface 102 b of the substrate, and the back-side inner connection structure 190 and the first optical device 180 share a back-side area or a wiring area to save the wiring area.

[0122] Figure 4 FIG. 1 is a cross-sectional view of a package structure 100 b according to some embodiments of the present disclosure. The package structure 100 b is similar to or the same as Figure 3GThe process and materials used to form the semiconductor device structure 100b may be similar to or the same as the process and materials used to form the semiconductor device structure 100a, and the detailed description thereof will not be repeated here.

[0123] Figure 4 and Figure 3G The difference between the two is that an additional optical fiber 202 is formed adjacent to the first optical device 180. The optical fiber 202 serves as an input / output port of an optical signal of the first optical device 180. By placing the optical fiber 202 adjacent to the first optical device 180, the optical signal leaving the optical fiber 202 is guided through the first optical device 180. The optical signal is coupled through the optical fiber 202.

[0124] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a package structure 100c according to some embodiments of the present disclosure. The package structure 100c is similar to or the same as Figure 3G The process and materials used to form the semiconductor device structure 100c may be similar to or the same as the process and materials used to form the semiconductor device structure 100a, and the detailed description thereof will not be repeated here.

[0125] Figure 5 and Figure 3G The difference is that the second optical device 206 is formed in the dielectric layer 196 of the back-side inner connection structure 190. The second optical device 206 is formed below the photoelectric effect material layer 186. The second optical device 206 cooperates with the first optical device 180 to more effectively transmit optical signals. In addition, by forming the second optical device 206, cross-talk can be further reduced.

[0126] The second optical device 206 may be an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a built-in channel waveguide, a diffused waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler, etc.), or the like. In some embodiments, the second optical device 206 is a waveguide made of silicon nitride (SiN). In some embodiments, the material of the second optical device 206 may be a translucent material. In some embodiments, the second optical device 206 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0127] Figure 6A-6F Schematic cross-sectional views of various stages of forming a package structure 100d according to some embodiments of the present disclosure are shown. The package structure 100d is similar to or the same as Figure 3GThe process and materials used to form the semiconductor device structure 100d may be similar to or the same as the process and materials used to form the semiconductor device structure 100a, and the detailed description thereof will not be repeated here.

[0128] like Fig. 6A As shown, an optical interposer 210 is provided, and the optical interposer 210 includes a substrate 212, and then a dielectric layer 214 is formed on the substrate 212. Next, a bonding layer 226 is formed on the dielectric layer 214. After that, a substrate through hole (TSV) structure 234 is formed, which passes through the substrate 212 and the dielectric layer 214. The substrate through hole (TSV) structure 234 penetrates the substrate 212 to provide a fast channel for power, data and ground lines in the substrate 212.

[0129] The optical interposer 210 can receive various signals, whether electronic or optical, convert the signals into optical signals if necessary, transmit the optical signals as needed, convert the optical signals into electronic signals, and then send the electronic signals to the desired components.

[0130] The conductive layer 216 is formed in the dielectric layer 214, and the third optical device 220 is formed in the dielectric layer 214. The grating coupler 222 is formed in the dielectric layer 214. The grating coupler 222 is formed on the upper surface of the dielectric layer 214.

[0131] The substrate 212 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 202 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0132] In some embodiments, dielectric layer 214 includes a low-k dielectric material, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, para-xylene, bis-benzocyclobutene (BCB), or polyimide. In some embodiments, dielectric layer 214 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0133] In some embodiments, the conductive layer 216 includes a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, a combination thereof, or another suitable material. In some embodiments, the conductive layer 216 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another suitable deposition process.

[0134] The third optical device 220 may be an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a built-in channel waveguide, a diffused waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler, etc.), or the like. In some embodiments, the third optical device 220 is a waveguide made of silicon nitride (SiN). In some embodiments, the material of the third optical device 220 may be a translucent material. In some embodiments, the third optical device 220 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0135] In some embodiments, the grating coupler 222 is used to receive a signal from the third optical device 220. In some embodiments, the grating coupler 222 can be used to receive and redirect a signal from the optical fiber 202 (shown in FIG. Fig. 6F ), the off-plane signal transmitted by the first optical device 180 and the second optical device 206 is sent to the third optical device 220.

[0136] A conductive pad 228 is formed in the bonding layer 226, and the conductive pad 228 is electrically connected to the conductive layer 216 and directly contacts therewith. In some embodiments, the bonding layer 226 includes silicon oxide. In some other embodiments, the bonding layer 226 includes a polymer material, such as benzocyclobutene (BCB) polymer, polyimide (PI) or polybenzoxazole (PBO) or other suitable materials. The conductive pad 228 is formed on the upper surface of the bonding layer 226. In some embodiments, the conductive pad 228 includes a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy or other suitable materials. In some embodiments, the conductive pad 228 is formed by electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or other suitable deposition processes.

[0137] A through substrate via (TSV) trench (not shown) is formed through the substrate 212 and the dielectric layer 214 to expose the conductive layer 216 from the backside surface of the substrate 212. Next, a liner (not shown) may be formed in the through substrate via (TSV) trench, a diffusion barrier layer (not shown) may be formed on the liner, and a conductive material may be formed in the diffusion barrier layer. After the through substrate via (TSV) trench is filled, the excess liner, diffusion barrier layer, and conductive material are removed by a planarization process such as a chemical mechanical polishing (CMP) process.

[0138] In some embodiments, the liner is made of an insulating material, such as an oxide, a nitride, or other suitable material. In some embodiments, the diffusion barrier layer is tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), or another suitable material. In some embodiments, the conductive material is made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or another suitable material.

[0139] In some embodiments, the liner, diffusion barrier layer and conductive material are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or another suitable deposition process.

[0140] After forming the TSV structure 234, a plurality of UBM layers 236 are formed below the TSV structure 234, and a plurality of conductive connectors 238 are formed below the UBM layer 236. The conductive connectors 238 are electrically connected to the conductive layer 216 through the TSV structure 234.

[0141] In some embodiments, the UBM layer 236 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), nickel (Ni), gold (Au), chromium (Cr), copper (Cu), copper alloy, other suitable materials or combinations thereof. In some embodiments, the conductive connector 238 includes copper (Cu), copper alloy or another suitable material. In some embodiments, the UBM layer 236 and the conductive connector 238 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or another suitable deposition process.

[0142] Afterwards, if Figure 6B As shown, according to some embodiments of the present disclosure, the crystal grains 20a and 20b are prepared. The crystal grains 20a and 20b are prepared by the following steps. A bonding layer 326 is formed on Figure 5 The semiconductor structure 100c is formed below the dielectric layer 196 of the inner connection structure 190, and then Figure 5 The structure 100 c is cut into the dies 20 a and 20 b. The conductive pad 328 is formed in the bonding layer 326 .

[0143] The die 20a includes the semiconductor structure 10 and the first optical device 180, the second optical device 206 and the photoelectric effect material layer 186. The die 20b also includes the semiconductor structure 10, the first optical device 180, the second optical device 206 and the photoelectric effect material layer 186. Each of the die 20a and 20b includes an electronic device and an optical device (formed on opposite sidewall surfaces of the optical fiber 202).

[0144] The grating coupler 322 is formed in the dielectric layer 196 of the inner connection structure 190. In some embodiments, the grating coupler 322 is used to receive a signal from the second optical device 206. In some embodiments, the grating coupler 322 can be used to receive and redirect a signal from the optical fiber 202 (shown in FIG. Fig. 6F )The incoming, deviated-from-surface signal is sent to the second optical device 206.

[0145] The conductive pads 328 of the dies 20a, 20b face the conductive pads 228 of the optical interposer 210, and the bonding layers 326 of the dies 20a, 20b face the bonding layers 226 of the optical interposer 210. In addition, the grating coupler 222 faces the grating coupler 322.

[0146] In some embodiments, the conductive pad 328 includes a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, or another suitable material. In some embodiments, the conductive pad 328 is formed by electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another suitable deposition process.

[0147] Afterwards, if Figure 6C As shown, according to some embodiments of the present disclosure, the die 20 a and the die 20 b are bonded to the optical interposer 210 .

[0148] Before bonding the die 20a and the die 20b to the optical interposer 210, the die 20a, 20b are aligned with the optical interposer 210 so that the conductive pads 328 on the die 20a, 20b can be bonded to the conductive pads 228 on the optical interposer 210, and the bonding layers 326 of the die 20a, 20b can be bonded to the bonding layers 226 of the optical interposer 210. In some embodiments, the alignment of the die 20a, 20b with the optical interposer 210 can be achieved by using an optical sensing method.

[0149] After alignment, the dies 20a, 20b and the optical interposer 210 are bonded together by a hybrid bonding process. The dies 20a, 20b and the optical interposer 210 are hybrid bonded together by applying pressure and heat.

[0150] Hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding. Figure 6C As shown, a bonding structure 350 is formed between the die 20a, 20b and the optical interposer 210. The bonding structure 350 is a hybrid bonding structure, including the conductive pads 228, 328 bonded by metal to metal and the bonding layers 226, 326 bonded by non-metal to non-metal. The bonding structure 350 has a metal bonding interface 350a between the conductive pads 228 and 328, but due to the reflow process, there may not be a clear non-metal interface between the bonding layers 226 and 326. In this way, the fusion of the die 20a, 20b and the optical interposer 210 forms a hybrid bonding device. In some embodiments, the bonded die is baked, annealed, pressed or otherwise treated to strengthen or complete the bonding.

[0151] In addition, although a hybrid bonding process is described above, it is intended to be illustrative rather than limiting. In some other embodiments, the die 20a, 20b may be bonded to the optical interposer 210 by direct surface bonding, metal-to-metal bonding, or other bonding processes. The direct surface bonding process forms an oxide-to-oxide bond or a substrate-to-substrate bond by a cleaning and / or surface activation process, and then applying pressure, heat, and / or other bonding process steps to the connected surfaces. In other embodiments, the first semiconductor device 201 and the optical interposer 100 are achieved by metal-to-metal bonding, which is achieved by melting the conductive components. Any suitable bonding process may be utilized, and all of the above methods are fully covered within the scope of the embodiments of the present invention.

[0152] Additionally, in some embodiments, the electrical connections that exist between the die 20 a, 20 b and the optical interposer 210 (e.g., the electrical connections between the conductive pad 228 and the conductive pad 328 ) are the paths that each signal (whether optical or electronic) follows in order to communicate between the die 20 a, 20 b and the optical interposer 210 .

[0153] Next, if Fig.6D As shown, according to some embodiments of the present disclosure, a packaging layer 354 is formed on the die 20a, 20b and the optical interposer 210. In some embodiments, before forming the packaging layer 354, a primer layer (not shown) is formed, and there is an interface between the primer layer and the packaging layer 354. The packaging layer 354 surrounds and protects the die 20a, 20b and the optical interposer 210.

[0154] The encapsulation layer 354 is made of a molding compound material. The molding compound material may include a polymer material, such as an epoxy resin having a filler dispersed therein. In some embodiments, a liquid molding compound material is applied to the die 20a, 20b. A thermal process is then used to cure the liquid molding compound material and convert it into the encapsulation layer 354.

[0155] Afterwards, if Fig. 6E As shown, according to some embodiments of the present disclosure, a portion of the encapsulation layer 354 and a portion of the bonding layer 226 are removed to expose the upper surface of the dielectric layer 214 of the optical interposer 210. As a result, the sidewall surface of the encapsulation layer 354 is not aligned with the sidewall surface of the dielectric layer 214 of the optical interposer 210. Furthermore, a portion of the upper surface of the optical interposer 210 is not covered by the encapsulation layer 354.

[0156] Next, if Fig. 6F As shown, according to some embodiments of the present disclosure, an optical fiber 202 is formed adjacent to the die 20b. The optical fiber 202 is used as an input / output port for optical signals of the second optical device 206. By placing the optical fiber 202 adjacent to the second optical device 206 of the die 20b, the optical signal leaving the optical fiber 202 is guided through the second optical device 206.

[0157] Figure 7 FIG. 1 is a cross-sectional view of a package structure 100e according to some embodiments of the present disclosure. The package structure 100e is similar to or the same as Fig. 6F The process and materials used to form the semiconductor device structure 100e may be similar to or the same as the process and materials used to form the semiconductor device structure 100d, and the detailed description thereof will not be repeated here.

[0158] Figure 7 and Fig. 6F The difference between the two is that the grating coupler 358 is formed in the dielectric layer 214 of the optical interposer 210. The optical fiber 202 is formed adjacent to the grating coupler 358 and faces the grating coupler 358. The optical fiber 202 serves as an input / output port of an optical signal of the grating coupler 358. By placing the optical fiber 202 adjacent to the grating coupler 358, the optical signal leaving the optical fiber 202 is guided through the grating coupler 358.

[0159] The grating coupler 358 can be used to receive and redirect the optical fiber 202 (shown in FIG. Figure 7 )The incoming, deviated-from-surface signal is sent to the third optical device 220.

[0160] Figure 8FIG. 1 is a cross-sectional schematic diagram of a package structure 100 f according to some embodiments of the present disclosure. The package structure 100 f is similar to or the same as Fig. 6F The process and materials used to form the semiconductor device structure 100f may be similar to or the same as the process and materials used to form the semiconductor device structure 100d, and the detailed description thereof will not be repeated here.

[0161] Figure 8 and Fig. 6F The difference is that the optical fiber 202 is adjacent to the third optical device 220 of the optical interposer 210. The optical fiber 202 serves as an input / output port for optical signals of the third optical device 220. By placing the optical fiber 202 adjacent to the third optical device 220, the optical signal leaving the optical fiber 202 is guided through the third optical device 220.

[0162] Figure 9A-9D 1 is a cross-sectional schematic diagram showing various stages of forming a package structure 100g according to some embodiments of the present disclosure. The package structure 100d is similar to or the same as Figure 3G The process and materials used to form the semiconductor device structure 100g may be similar to or the same as the process and materials used to form the semiconductor device structure 100a, and the detailed description thereof will not be repeated here. Fig.9D and Figure 3G The difference between the two is that the photoelectric effect material layer 186 and the protective layer 188 are manufactured before the first optical device 180 is formed.

[0163] like Fig. 9A As shown, according to some embodiments of the present disclosure, a dielectric layer 172 is formed on the backside surface 102 b of the substrate 102 , and then a through substrate via (TSV) structure 174 is formed through the dielectric layer 172 and the substrate 102 .

[0164] Afterwards, if Fig. 9B As shown, according to some embodiments of the present disclosure, a photoelectric effect material layer 186, a conductive layer 187 and a protective layer 188 are formed on the dielectric layer 178. The photoelectric effect material layer 186 and the conductive layer 187 are buried in the protective layer 188. The photoelectric effect material layer 186 is in direct contact with the conductive layer 187 to transmit electronic signals. The protective layer 188 is used to protect the photoelectric effect material layer 186.

[0165] In some embodiments, the photoelectric effect material layer 186 includes graphene. In some embodiments, the photoelectric effect material layer 186 is a two-dimensional material. The photoelectric effect material layer 186 can be one or more layers depending on the actual application. In some embodiments, the photoelectric effect material layer 186 is attached or bonded to the dielectric layer 178. In some embodiments, the photoelectric effect material layer 186 is made of graphene, and the thickness of the graphene is about 0.35nm.

[0166] Next, if Fig. 9C As shown, according to some embodiments of the present disclosure, a dielectric layer 178 is formed on the protection layer 188 , and a first optical device 180 , a conductive layer 182 , and a contact plug 184 are formed in the dielectric layer 178 .

[0167] In some embodiments, dielectric layer 178 includes a low-k dielectric material and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, paraxylene, bis-benzocyclobutene (BCB), or polyimide.

[0168] The first optical device 180 may be an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a built-in channel waveguide, a diffused waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler, etc.), or the like. In some embodiments, the third optical device 220 is a waveguide made of silicon nitride (SiN). In some embodiments, the material of the first optical device 180 may be a translucent material. In some embodiments, the first optical device 180 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0169] Afterwards, if Fig.9D As shown, according to some embodiments of the present disclosure, an internal connection structure 190 is formed on the dielectric layer 178. The internal connection structure 190 is a back-side internal connection structure. The internal connection structure 160 can be used as a redistribution layer (RDL) structure for wiring. Next, the inverted Fig. 9C structure.

[0170] The interconnect structure 190 includes a contact plug 192, a conductive layer 194, a dielectric layer 196, a UBM layer 197, and a conductive connector 198. The contact plug 192 and the conductive layer 194 are buried in the dielectric layer 196.

[0171] Fig.10 FIG. 1 is a cross-sectional schematic diagram of a package structure 100h according to some embodiments of the present disclosure. The package structure 100h is similar to or the same as Fig.9DThe process and materials used to form the semiconductor device structure 100h may be similar to or the same as the process and materials used to form the semiconductor device structure 100g, and the detailed description thereof will not be repeated here.

[0172] Fig.10 and Fig.9D The difference between the first optical device 180 and the second optical device 180 is that an additional optical fiber 202 is formed beside the first optical device 180. The optical fiber 202 serves as an input / output port of an optical signal of the first optical device 180. With the optical fiber 202 adjacent to the first optical device 180, the optical signal leaving the optical fiber 202 is guided through the first optical device 180.

[0173] Fig.11 FIG. 1 is a cross-sectional schematic diagram of a package structure 100i according to some embodiments of the present disclosure. The package structure 100i is similar to or the same as Fig.9D The process and materials used to form the semiconductor device structure 100i may be similar to or the same as the process and materials used to form the semiconductor device structure 100g, and the detailed description thereof will not be repeated here.

[0174] Fig.11 and Fig.9D The difference between the two is that the second optical device 206 is formed in the back inner connection structure 190. The second optical device 206 cooperates with the first optical device 180 to more effectively transmit optical signals.

[0175] The second optical device 206 may be an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a built-in channel waveguide, a diffused waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler, etc.), or the like. In some embodiments, the second optical device 206 is a waveguide made of silicon nitride (SiN). In some embodiments, the material of the second optical device 206 is a translucent material. In some embodiments, the second optical device 206 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0176] Figure 12A-12C 1 is a cross-sectional view of various stages of forming a package structure 100j according to some embodiments of the present disclosure. The package structure 100 is similar to or the same as Figure 3G The process and materials used to form the semiconductor device structure 100j may be similar to or the same as the process and materials used to form the semiconductor device structure 100a, and the detailed description thereof will not be repeated here.

[0177] like Fig. 12A As shown, according to some embodiments of the present disclosure, an optical intermediary layer 210 is provided, and Fig.9D The crystal grains 20c and 20d are prepared from the semiconductor structure 100g. The crystal grains 20c and 20d are prepared by the following steps. The bonding layer 326 is formed at Fig.9D The semiconductor structure 100g is then formed below the dielectric layer 196 of the inner connection structure 190. Fig.9D The structure of FIG. 1 is cut into the grains 20 c and 20 d. The conductive pad 328 is formed in the bonding layer 326. The grating coupler 322 is formed in the dielectric layer 196.

[0178] The optical interposer 210 includes a substrate 212 and a dielectric layer 214 formed on the substrate 212. A bonding layer 226 is formed on the dielectric layer 214, and a conductive pad 228 is formed in the bonding layer 226. Afterwards, a substrate through-hole (TSV) structure 234 is formed through the substrate 212 and the dielectric layer 214. The substrate through-hole (TSV) structure 234 penetrates the substrate 212 to provide a fast path for power, data, and ground in the substrate 212. A conductive layer 216 is formed on the dielectric layer 214, and a third optical device 220 is formed in the dielectric layer 214. A grating coupler 222 is formed in the dielectric layer 214. The conductive pad 328 of the die 20c, 20d faces the conductive pad 328 of the optical interposer 210 and is ready for a bonding process. In addition, the grating coupler 222 faces the grating coupler 322.

[0179] Afterwards, if Fig. 12B As shown, according to some embodiments of the present disclosure, the dies 20 c and 20 d are bonded to the optical interposer 210 .

[0180] Before bonding the die 20c, 20d to the optical interposer 210, the die 20c, 20d and the optical interposer 210 are aligned so that the conductive pads 328 on the die 20c, 20d can be bonded to the conductive pads 228 on the optical interposer 210, and the bonding layer 326 of the die 20c, 20d can be bonded to the bonding layer 226 of the optical interposer 210. In some embodiments, the alignment of the die 20c, 20d and the optical interposer 210 can be achieved by using an optical sensing method. All of the conductive pads 228 and 328 can be aligned, some of the conductive pads 228 and 328 can be offset, or all of the conductive pads 228 and 328 can be offset. In some embodiments, the conductive pads 328 on the die 20c, 20d and the conductive pads 228 on the optical interposer 210 are aligned. In some embodiments, some of the conductive pads 328 on the die 20c, 20d and the conductive pads 228 on the optical interposer 210 are aligned.

[0181] After alignment, the dies 20c, 20d and the optical interposer 210 are bonded together by a hybrid bonding process. The dies 20c, 20d and the optical interposer 210 are hybrid bonded together by applying pressure and heat.

[0182] Hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding. Fig. 12B As shown, a hybrid bonding structure 350 is formed between the die 20c, 20d and the optical interposer 210. The hybrid bonding structure 350 includes conductive pads 228, 328 bonded by metal to metal and bonding layers 226, 326 bonded by non-metal to non-metal. The bonding structure 350 has a metal bonding interface 350a between the conductive pads 228 and 328, but due to the reflow process, there may be no clear non-metal interface between the bonding layers 226 and 326. In this way, the fusion of the die 20c, 20d and the optical interposer 210 forms a hybrid bonding device. In some embodiments, the bonded die is baked, annealed, pressed or otherwise treated to strengthen or complete the bonding.

[0183] According to some embodiments of the present disclosure, after the hybrid bonding process is performed, a packaging layer 354 is formed on the dies 20c, 20d and the optical interposer 210. In some embodiments, before forming the packaging layer 354, a primer layer (not shown) is formed, and an interface is provided between the primer layer and the packaging layer 354. The packaging layer 354 surrounds and protects the dies 20c, 20d and the optical interposer 210.

[0184] The encapsulation layer 354 is made of a molding compound material. The molding compound material may include a polymer material, such as an epoxy resin having a filler dispersed therein. In some embodiments, a liquid molding compound material is applied to the die 20c, 20d. A thermal process is then used to cure the liquid molding compound material and convert it into the encapsulation layer 354.

[0185] Next, if Fig. 12C As shown, according to some embodiments of the present disclosure, a portion of the encapsulation layer 354 and a portion of the bonding layer 226 are removed to expose the upper surface of the dielectric layer 214. As a result, the sidewall surface of the encapsulation layer 354 is not aligned with the sidewall surface of the dielectric layer 214 of the optical interposer 210.

[0186] Next, according to some embodiments of the present disclosure, an optical fiber 202 is formed adjacent to the die 20b. The optical fiber 202 is used as an input / output port of an optical signal of the second optical device 206. By placing the optical fiber 202 adjacent to the second optical device 206, the optical signal leaving the optical fiber 202 is guided through the second optical device 206.

[0187] Fig.13FIG. 1 is a cross-sectional schematic diagram of a package structure 100k according to some embodiments of the present disclosure. The package structure 100k is similar to or the same as Fig. 12C The process and materials used to form the semiconductor device structure 100k may be similar to or the same as the process and materials used to form the semiconductor device structure 100j, and the detailed description thereof will not be repeated here.

[0188] Fig.13 and Fig. 12C The difference between the two is that the grating coupler 358 is formed in the dielectric layer 214 of the optical interposer 210. The optical fiber 202 is formed adjacent to the grating coupler 358 and faces the grating coupler 358. The optical fiber 202 serves as an input / output port of an optical signal of the grating coupler 358. By placing the optical fiber 202 adjacent to the grating coupler 358, the optical signal leaving the optical fiber 202 is guided through the grating coupler 358.

[0189] Fig.14 FIG. 1 is a cross-sectional schematic diagram of a package structure 1001 according to some embodiments of the present disclosure. The package structure 1001 is similar to or the same as Fig. 12C The process and materials used to form the semiconductor device structure 1001 may be similar to or the same as the process and materials used to form the semiconductor device structure 100j, and the detailed description thereof will not be repeated here.

[0190] Fig.14 and Fig. 12C The difference is that the optical fiber 202 is adjacent to the third optical device 220 of the optical interposer 210. The optical fiber 202 serves as an input / output port for optical signals of the third optical device 220. By placing the optical fiber 202 adjacent to the third optical device 220, the optical signal leaving the optical fiber 202 is guided through the third optical device 220.

[0191] Embodiments of package structures and embodiments of methods for forming the same are provided herein. A semiconductor structure (or electronic device) is formed on the front surface of a substrate, and a first optical device and a photoelectric effect material layer are formed on the back surface of the substrate. The substrate may be a wafer, and the electronic device (e.g., semiconductor device) and the optical device (e.g., first optical device and photoelectric effect material layer) are integrated into a wafer. It should be noted that there is no bonding layer between the electronic device (e.g., semiconductor device) and the optical device (e.g., first optical device and photoelectric effect material layer). Since the electronic device and the optical device are formed on a single wafer or chip without a bonding layer, rather than on different chips, the channels for electronic signals and optical signals are reduced, and the transmission speed of the electronic signals and optical signals can be improved.

[0192] In some embodiments, a package structure is provided. The package structure includes a substrate having a front surface and a back surface, and an electronic device formed on the front surface of the substrate. The package structure includes a first optical device formed below the back surface of the substrate. The package structure also includes a protective layer formed below or above the first optical device and a photoelectric effect material layer formed in the protective layer.

[0193] In some embodiments, the package structure further includes a dielectric layer formed below and in direct contact with the back surface of the substrate; and an optical fiber adjacent to the first optical device. In some embodiments, the package structure further includes a second optical device formed below the first optical device. In some embodiments, the package structure further includes a substrate through-hole (TSV) structure connected to the electronic device and the photoelectric effect material layer. Furthermore, in some embodiments, the electronic device includes a plurality of nanostructures formed on the substrate and a source / drain (S / D) structure connected to the nanostructures, wherein the substrate through-hole (TSV) structure is connected to the source / drain (S / D) structure. In some embodiments, the first optical device includes an optical waveguide or a coupler. In some embodiments, the package structure further includes a front-side internal connection structure formed above the electronic device and a back-side internal connection structure formed below the protective layer. In some embodiments, the electronic device and the first optical device are formed in a grain. In some embodiments, the photoelectric effect material layer includes a graphene layer.

[0194] In some embodiments, a package structure is provided. The package structure includes an optical interposer and a first die formed on the optical interposer. The first die includes an electronic device, a first optical device formed below the electronic device, and a graphene layer formed above or below the first optical device.

[0195] In some embodiments, the package structure further includes a bonding structure located between the optical intermediary layer and the first die, wherein the bonding structure includes a first bonding layer bonded to a second bonding layer and a first conductive pad bonded to a second conductive pad. In some embodiments, the package structure further includes a first grating coupler formed in the first die and a second grating coupler formed in the optical intermediary layer. In some embodiments, the package structure further includes an optical fiber formed adjacent to the first optical device or adjacent to an upper surface of the optical intermediary layer. In some embodiments, the package structure further includes a second optical device formed below the graphene layer. In some embodiments, the package structure further includes a second die formed above the optical intermediary layer, wherein the second die is adjacent to the first die, and the second die includes another graphene layer. Furthermore, in some embodiments, the package structure further includes a packaging layer surrounding the first die and the second die, wherein a portion of an upper surface of the optical intermediary layer is not covered by the packaging layer.

[0196] In some embodiments, a method for forming a package structure is provided. The method includes forming an electronic device on a front surface of a substrate and forming a first optical device on a back surface of the substrate. The method includes forming a photoelectric effect material layer on the optical device and forming a protective layer on the photoelectric effect material layer.

[0197] In some embodiments, the method further comprises removing a portion of the substrate and forming a through substrate via (TSV) structure through the substrate. In some embodiments, the method further comprises forming a first grating coupler below the first optical device and forming a first bonding layer below the first grating coupler. In some embodiments, the method further comprises forming an optical interposer below the first optical device.

[0198] The above briefly describes the characteristic components of several embodiments of the utility model, so that those skilled in the art can more easily understand the types of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A package structure, characterized in that: include: A substrate having a front surface and a back surface; an electronic device formed on the front surface of the substrate; a first optical device formed below the back surface of the substrate; a protective layer formed below or above the first optical device; as well as A photoelectric effect material layer is formed in the protective layer.

2. The package structure according to claim 1, characterized in that: Also includes: a dielectric layer formed below and in direct contact with the backside surface of the substrate; as well as An optical fiber is adjacent to the first optical device.

3. The package structure according to claim 1 or 2, characterized in that: Also includes: A second optical device is formed below the first optical device.

4. The package structure according to claim 1 or 2, characterized in that: Also includes: A substrate via structure connected to the electronic device and the photoelectric effect material layer; a plurality of nanostructures formed on the substrate; as well as A source / drain structure is connected to the plurality of nanostructures, wherein the substrate via structure is connected to the source / drain structure.

5. The package structure according to claim 1, wherein: The first optical device includes an optical waveguide or a coupler.

6. A package structure, characterized in that: include: an optical intermediary layer; as well as A first die is formed on the optical interposer, wherein the first die comprises: an electronic device; a first optical device formed below the electronic device; and A graphene layer is formed above or below the first optical device.

7. The package structure according to claim 6, characterized in that: Also includes: A bonding structure is located between the optical intermediate layer and the first die, wherein the bonding structure includes a first bonding layer bonded to a second bonding layer, and a first conducting pad bonded to a second conducting pad.

8. The package structure according to claim 6 or 7, characterized in that: Also includes: a first grating coupler formed in the first die; as well as A second grating coupler is formed in the optical intermediary layer.

9. The package structure according to claim 6 or 7, characterized in that: Also includes: An optical fiber is formed adjacent to the first optical device or adjacent to an upper surface of the optical intermediary layer.

10. The package structure according to claim 6 or 7, characterized in that: Also includes: A second optical device is formed below the graphene layer.

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