DSI3 simulation circuit capable of outputting voltage, test simulation device and system

Abstract

The embodiment of the utility model provides a DSI3 simulation circuit capable of outputting voltage, a test simulation device and a test simulation system, and relates to the technical field of simulation. The DSI3 simulation circuit comprises a main equipment simulation output channel used for being connected with a DSI3 bus, and the main equipment simulation output channel comprises a signal amplification module, a first triode, a second triode and at least one resistor; a collector electrode of the first triode is connected to a voltage source, an emitter electrode of the first triode is connected to a signal output end of the DSI3 simulation circuit through at least one resistor, an emitter electrode of the second triode is connected to the signal output end through at least one resistor, and a collector electrode of the second triode is connected to a grounding end; the output end of the signal amplification module is connected to the base electrode of the first triode and the base electrode of the second triode. The negative feedback end of the signal amplification module is connected to the signal output end. The DSI3 simulation circuit can send voltage signals to the bus, and the hardware requirement for feeding back voltage to the DSI3 bus is met.

Description

Technical Field

[0001] The utility model relates to the technical field of simulation, and in particular to a DSI3 simulation circuit capable of outputting voltage, a test simulation device and a system. Background Art

[0002] The DSI3 (Distributed System Interface) bus is used to connect the master device node and the slave device node to realize the master-slave device node communication. It is a master-slave one-to-many asynchronous single-line current and voltage type communication; in which the master device node transmits data to the slave device node in the form of voltage on a communication line, and the slave device node returns the data in the form of current.

[0003] The DSI3 bus is often used to connect ECUs and sensors for test simulation. In the prior art, the sensor can only be simulated by a simulation device to communicate with the ECU through the DSI3 bus to perform simulation testing on the ECU. In such simulation sensors, there is no need to feed back voltage to the DSI bus. Therefore, in this field, there is usually no simulation device that can feed back voltage to the DSI3 bus, which cannot meet the simulation test requirements. Utility Model Content

[0004] The purpose of the utility model is to provide a DSI3 simulation circuit, a test simulation device and a system capable of outputting voltage. The DSI3 simulation circuit can send a voltage signal to the bus to meet the hardware requirement of feeding back voltage to the DSI3 bus; at the same time, an adjustable voltage output with load output capability is realized, which is convenient for meeting the voltage requirements of different slave device nodes.

[0005] To achieve the above-mentioned purpose, the utility model provides a DSI3 simulation circuit capable of outputting voltage, comprising: a master device simulation output channel for connecting to a DSI3 bus, the master device simulation output channel comprising: a signal amplification module, a first transistor, a second transistor and at least one resistor; the collector of the first transistor is connected to a voltage source, the emitter of the first transistor is connected to the signal output end of the DSI3 simulation circuit through at least one resistor, the emitter of the second transistor is connected to the signal output end through at least one resistor, and the collector of the second transistor is connected to a ground end; the output end of the signal amplification module is respectively connected to the base of the first transistor and the base of the second transistor, and the negative feedback end of the signal amplification module is connected to the signal output end; the signal amplification module is used to amplify the received DSI3 master device simulation voltage signal, and send the amplified DSI3 master device simulation voltage signal to the base of the first transistor and the base of the second transistor respectively.

[0006] The present invention also provides a test simulation device, comprising: a control module and at least one data transmission channel, the data transmission channel comprising: a digital-to-analog converter, and the above-mentioned DSI3 simulation circuit capable of outputting voltage; the digital-to-analog converter is connected between the control module and the signal amplification module, and is used to convert the received first digital signal into the DSI3 master device simulation voltage signal and send it to the signal amplification module.

[0007] In one embodiment, the signal amplification module includes: a first operational amplifier and a second operational amplifier; the non-inverting input terminal of the first operational amplifier is grounded, the inverting input terminal of the first operational amplifier is used to receive the DSI3 master device simulation voltage signal, the output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is grounded, the output terminal of the second operational amplifier is respectively connected to the base of the first transistor and the base of the second transistor, and the inverting input terminal of the second operational amplifier is also connected to the signal output terminal.

[0008] In one embodiment, the DSI3 simulation circuit also includes: a first current limiting transistor and a second current limiting transistor; the base of the first current limiting transistor is connected to the emitter of the first transistor, and the emitter of the first current limiting transistor is connected to the signal output end; the base of the second current limiting transistor is connected to the emitter of the second transistor, and the emitter of the second current limiting transistor is connected to the signal output end.

[0009] In one embodiment, the DSI3 simulation circuit also includes: at least one switch module, the control end of the switch module is used to receive an external control signal; the switch module is connected between the emitter of the first transistor and the signal output end, and the switch module is connected between the emitter of the second transistor and the signal output end.

[0010] In one embodiment, the at least one resistor includes a first resistor and a second resistor; the emitter of the first transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the signal output end; the emitter of the second transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the signal output end.

[0011] In one embodiment, the at least one resistor includes a third resistor; the emitter of the first transistor is connected to the first end of the third resistor, the emitter of the second transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the signal output end. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1is a circuit structure diagram of a DSI3 simulation circuit according to the first embodiment of the present invention, wherein the first transistor Q1 and the second transistor Q2 are connected to the signal output terminal through different resistors;

[0013] Figure 2 is another circuit structure schematic diagram of the DSI3 simulation circuit in the first embodiment of the present invention, wherein the first transistor Q1 and the second transistor Q2 are both connected to the signal output terminal through the same resistor;

[0014] Figure 3 is a schematic diagram of a DSI3 bus voltage VBUS output by a DSI3 emulation circuit in a first embodiment of the present invention;

[0015] Figure 4 is another circuit structure schematic diagram of the DSI3 simulation circuit of the test simulation device according to the first embodiment of the present invention, wherein a current-limiting transistor is further provided in the DSI3 simulation circuit;

[0016] Figure 5 is another circuit structure diagram of the DSI3 simulation circuit of the test simulation device according to the first embodiment of the present invention, wherein the DSI3 simulation circuit is further provided with a switch module;

[0017] Figure 6 is a schematic diagram of a test simulation device according to a second embodiment of the present invention;

[0018] Figure 7 1 is a circuit structure diagram of a current detection circuit of a test simulation device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings to describe the various embodiments of the present invention in detail, so as to more clearly understand the purpose, characteristics and advantages of the present invention. It should be understood that the embodiments shown in the accompanying drawings are not intended to limit the scope of the present invention, but are only intended to illustrate the essential spirit of the technical solution of the present invention.

[0020] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other cases, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0021] Unless the context requires otherwise, throughout the specification and claims, the word "comprise" and variations such as "include" and "have" should be construed in an open, inclusive sense, ie, should be interpreted as "including, but not limited to."

[0022] References throughout the specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0023] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or / and" unless the context clearly dictates otherwise.

[0024] In the following description, in order to clearly demonstrate the structure and working mode of the utility model, many directional words will be used for description, but the words "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

[0025] The first embodiment of the utility model relates to a DSI3 simulation circuit capable of outputting voltage. The DSI3 simulation circuit is connected to a DSI3 bus and is used for outputting a DSI3 master device simulation voltage signal to the DSI3 bus.

[0026] Moreover, in specific applications, the output voltage can be adjusted based on the input voltage to achieve an output with adjustable voltage width.

[0027] Therefore, the DSI3 simulation circuit can send voltage signals to the slave device nodes connected to the bus to meet the hardware requirements when the master device node simulation is required. Since the output voltage range of the DSI3 simulation circuit is adjustable, it can be applied to slave device nodes with various different voltage requirements. This will be used as an example for explanation later.

[0028] like Figure 1 and Figure 2 As shown, the master device simulation output channel of the DSI3 simulation circuit includes: a signal amplification module 100, a first transistor Q1, a second transistor Q2 and at least one resistor.

[0029] The collector of the first transistor Q1 is connected to the voltage source VQ, the emitter of the first transistor Q1 is connected to the signal output end of the DSI3 simulation circuit through at least one resistor, the emitter of the second transistor Q2 is connected to the signal output end of the DSI3 simulation circuit through at least one resistor, and the collector of the second transistor Q2 is connected to the analog ground AGND.

[0030] The output end of the signal amplifying module 100 is connected to the base of the first transistor Q1 and the base of the second transistor Q2 respectively, and the negative feedback end of the signal amplifying module 100 is connected to the signal output end of the DSI3 simulation circuit.

[0031] The signal amplifying module 100 is used to amplify the received DSI3 master device simulation voltage signal, and send the amplified DSI3 master device simulation voltage signal to the base of the first transistor Q1 and the base of the second transistor Q2 respectively.

[0032] In this embodiment, the signal output end of the DSI3 simulation circuit is connected to the DSI3 bus, and there are slave device nodes on the DSI3 bus. The DSI3 simulation circuit is used to output a voltage signal to the DSI3 bus based on the received DSI3 master device simulation voltage signal, that is, to send a voltage signal to the slave device node connected to the DSI3 bus.

[0033] exist Figure 1 In the example, a DSI3 simulation circuit includes two resistors, namely a first resistor R1 and a second resistor R2: the emitter of the first transistor Q1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the signal output end, the emitter of the second transistor Q2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the signal output end, that is, the second end of the first resistor R1 is connected to the second end of the second resistor R2, and the connection between the two is connected to the signal output end.

[0034] exist Figure 2 In the example, the DSI3 simulation circuit includes a third resistor R3: wherein the emitter of the first transistor Q1 is connected to the first end of the third resistor R3, the emitter of the second transistor Q2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the signal output end. That is, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2, the connection between the first transistor Q1 and the second transistor Q2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the signal output end, that is, the second end of the third resistor R3 forms the output end of the voltage output module, which is used to output a voltage signal to the bus.

[0035] exist Figure 1 and Figure 2In the example, the first transistor Q1 is an NPN transistor and the second transistor Q2 is a PNP transistor. In addition, the signal output end of the DSI3 simulation circuit is also grounded through a TVS transient suppression diode D1.

[0036] In this embodiment, the first transistor Q1 and the second transistor Q2 are connected in a push-pull output manner to form a push-pull circuit structure. When no voltage signal is sent to the DSI3 bus, the output voltage VOUT of the signal amplification module 100 controls the first transistor Q1 to close. At this time, the second transistor Q2 is disconnected, and the DSI3 bus voltage VBUS output by the DSI3 simulation circuit is pulled up. Therefore, the output voltage can generate a falling edge and a rising edge on the bus by controlling the first transistor Q1 and the second transistor Q2. The falling edge and the rising edge are the voltage signals that the simulated master device node needs to send to the bus, that is, the information that the simulated master device node needs to send to the slave device node.

[0037] by Figure 1 For example, the DSI3 master device simulation voltage signal input to the signal amplification module 100 is amplified by the signal amplification module 100, and the signal amplification module 100 outputs a voltage VOUT to the first transistor Q1 and the second transistor Q2. At this time, the first transistor Q1 is closed and the second transistor Q2 is disconnected. The output voltage VOUT of the signal amplification module 100 determines the current of the first transistor Q1. The current flowing through the first transistor Q1 also determines the voltage drop of the first resistor R1, thereby determining the magnitude of the DSI3 bus voltage VBUS output to the bus by the signal output end of the DSI3 simulation circuit. Small; for example, the output voltage VOUT of the signal amplification module 100 changes, the current flowing through the first transistor Q1 becomes larger, the voltage drop of the first resistor R1 increases, and the output DSI3 bus voltage VBUS decreases, thereby the output DSI3 bus voltage VBUS can be controlled by the output voltage VOUT of the signal amplification module 100, that is, the DSI3 bus voltage VBUS output to the bus of the DSI3 simulation circuit is adjustable in a wide voltage range; that is to say, when outputting to the DSI3 bus, it can be adjusted to any voltage within the 25V voltage specified by the DSI3 protocol.

[0038] Furthermore, the signal output terminal of the DSI3 simulation circuit is also connected to the negative feedback terminal of the signal amplification module 100, forming a negative feedback, so that the change of the output voltage VOUT of the signal amplification module 100 can adapt to the DSI3 bus voltage VBUS output by the DSI3 simulation circuit, so that the DSI3 bus voltage VBUS output by the DSI3 simulation circuit can reach the required output voltage V HIGH ; The voltage V HIGH The size of can be determined based on the voltage required by the currently connected slave device node. Figure 3As shown, V HIGH Characterizes the size of the DSI3 bus voltage VBUS when the first transistor Q1 is closed and pulled up, V LOW Characterizes the DSI3 bus voltage VBUS when the second transistor Q2 is closed and pulled down, T BIT Indicates the interval between two adjacent signal transmissions.

[0039] In one example, the DSI3 simulation circuit also includes: a first current limiting transistor Q3 and a second current limiting transistor Q4, a first current limiting transistor Q3 and a second current limiting transistor Q4; the base of the first current limiting transistor Q3 is connected to the emitter of the first transistor Q1, and the emitter of the first current limiting transistor Q3 is connected to the signal output end; the base of the second current limiting transistor Q4 is connected to the emitter of the second transistor Q2, and the emitter of the second current limiting transistor Q4 is connected to the signal output end of the DSI3 simulation circuit.

[0040] Please refer to Figure 4 ,exist Figure 1 A current limiting transistor is added to the DSI3 simulation circuit, wherein the base of the first current limiting transistor Q3 is connected to the emitter of the first transistor Q1, the collector of the first current limiting transistor Q3 is connected to the base of the first transistor Q1, and the emitter of the first current limiting transistor Q3 is connected to the end of the first resistor R1 that is not connected to the first transistor Q1; the base of the second current limiting transistor Q4 is connected to the emitter of the second transistor Q2, the collector of the second current limiting transistor Q4 is connected to the base of the second transistor Q2, and the emitter of the second current limiting transistor Q3 is connected to the end of the second resistor R2 that is not connected to the second transistor Q2. Among them, the first current limiting transistor Q3 is an NPN transistor and the second current limiting transistor Q4 is a PNP transistor as an example. In addition, the base of the first transistor Q1 can be electrically connected to the collector, and the base of the second transistor Q2 can be electrically connected to the collector.

[0041] exist Figure 4 In the embodiment, the base and emitter of the first current limiting transistor Q3 are connected to the two ends of the first resistor R1, so when the voltage drop across the two ends of the first resistor R1 is too large, the first current limiting transistor Q3 is turned on, and the output voltage VOUT of the signal amplification module 100 directly passes through the first current limiting transistor Q3, and the first transistor Q1 is disconnected. Similarly, the second current limiting transistor Q4 can also play a similar role to the first current limiting transistor Q3, which will not be described in detail here.

[0042] It should be noted that Figure 4 So Figure 1 The circuit structure of the DSI3 simulation circuit is used as an example to illustrate. Figure 2Or the circuit structure of other DSI3 simulation circuits can also play the role of current limiting by adding current limiting transistors; in addition, other current limiting circuit structures besides current limiting transistors can be added to the circuit to achieve the purpose of current limiting, which are all within the protection scope of this application.

[0043] In some embodiments, the DSI3 simulation circuit also includes: at least one switch module, the control end of the switch module is used to receive an external control signal; a switch module is connected between the emitter of the first transistor Q1 and the signal output end of the DSI3 simulation circuit, and a switch module is connected between the emitter of the second transistor Q2 and the signal output end of the DSI3 simulation circuit.

[0044] Please refer to Figure 5 ,exist Figure 4 Two switching transistors are added to the basis of the DSI3 simulation circuit, namely the first switching transistor Q5 and the second switching transistor Q6. The emitter of the first switching transistor Q5 is connected to the first resistor R1, and the collector of the first switching transistor Q5 is connected to the emitter of the second switching transistor Q6. The base of the first switching transistor Q5 receives an external control signal through the resistor R4, and the base of the second switching transistor Q6 receives an external control signal through the resistor R5. The connection between the first switching transistor Q5 and the second switching transistor Q6 forms the signal output end of the DSI3 simulation circuit.

[0045] The first switch transistor Q5 and the second switch transistor Q6 are both controlled to be on and off by an external control signal, so that when the DSI3 simulation circuit is not externally connected to the slave device node, the first switch transistor Q5 and the second switch transistor Q6 are both controlled to be off.

[0046] It should be noted that Figure 4 In the example, the switch transistors are set in both the branches where the first transistor Q1 and the second transistor Q2 are located. However, only one switch transistor can be set at the signal output end of the DSI3 simulation circuit. Figure 1 For example, a switch transistor is set at the connection between the first resistor R1 and the second resistor R2 to realize the on-off control of the DSI3 simulation circuit. In addition, other components such as MOS tubes can also be used as switches to realize the on-off control of the DSI3 simulation circuit, which can be used in this embodiment.

[0047] In an example, Figure 4 and Figure 5As shown, taking the signal amplification module 100 as a two-stage amplification circuit as an example, it mainly includes: a first operational amplifier U1A and a second operational amplifier U1B, the non-inverting input terminal of the first operational amplifier U1A is grounded AGND, the inverting input terminal of the first operational amplifier U1A is used to receive the DSI3 master device simulation voltage signal, the output terminal of the first operational amplifier U1A is connected to the inverting input terminal of the second operational amplifier U1B, the non-inverting input terminal of the second operational amplifier U1B is grounded, the output terminal of the second operational amplifier U1B is respectively connected to the base of the first transistor Q1 and the base of the second transistor Q2, and the inverting input terminal of the second operational amplifier U1B is also connected to the signal output terminal of the DSI3 simulation circuit.

[0048] Specifically, the inverting input terminal of the first operational amplifier U1A receives the input DSI3 master device simulation voltage signal through the resistor R6, the output terminal of the first operational amplifier U1A is connected to the inverting input terminal of the second operational amplifier U1B through the resistor R7, the non-inverting input terminal of the second operational amplifier U1B is grounded AGND, the output terminal of the second operational amplifier U1B is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the collector of the first transistor Q1 through the resistor R8, the output terminal of the second operational amplifier U1B is also connected to the cathode of the diode D3, and the anode of the diode D3 is connected to the collector of the second transistor Q2 through the resistor R9. It also includes some peripheral circuits of the operational amplifier, for example, the VDD terminal of the first operational amplifier U1A is connected to the voltage source VQ, the VDD terminal of the first operational amplifier U1A is also connected to the analog ground AGND through the capacitor C1, the ground terminal of the first operational amplifier U1A is connected to the VSS terminal, and the ground terminal of the first operational amplifier U1A is also connected to the analog ground AGND through the capacitor C2; the output terminal and the inverting input terminal of the first operational amplifier U1A are also connected through the first resistor R10, and the output terminal of the first operational amplifier U1A is also connected to the inverting input terminal of the first operational amplifier U1A through a series resistor R11 and a capacitor C3.

[0049] In addition, the inverting input terminal of the second operational amplifier U1B is the negative feedback terminal of the signal amplification module, and the signal output terminal of the DSI3 simulation circuit is also connected to the inverting input terminal of the second operational amplifier U1B through a resistor R12, thereby realizing a negative feedback connection between the signal amplification module 100 and the signal output terminal of the DSI3 simulation circuit. The signal output terminal of the DSI3 simulation circuit is also connected to the inverting input terminal of the second operational amplifier U1B through a series resistor R13 and a capacitor C4.

[0050] exist Figure 4In the embodiment, the input DSI3 master device simulation voltage signal is output after passing through the first operational amplifier U1A and the second operational amplifier U1B. The voltage of the DSI3 master device simulation voltage signal is amplified to the set voltage value; the DSI3 bus voltage VBUS output by the DSI3 simulation circuit is connected to the second operational amplifier U1B through negative feedback, so that the DSI3 bus voltage VBUS follows the output of the operational amplifier, and the output DSI3 bus voltage VBUS is pulled up and down based on the push-pull circuit structure; the current is amplified from the voltage source VQ through the first transistor Q1, and is limited by the first current limiting transistor Q3. After passing through the first switch transistor Q5, it flows into the bus, realizing an adjustable wide voltage output with load output capability, and can meet different voltage requirements without making structural improvements to the circuit.

[0051] The second embodiment of the present application relates to a test simulation device, please refer to Figure 6 The test simulation device includes: a control module 1 and at least one data transmission channel 2, the data transmission channel 2 includes: a digital-to-analog converter 21, and a DSI3 simulation circuit 22 capable of outputting voltage in the first embodiment; the signal output end of the DSI3 simulation circuit 22 is connected to the DSI3 bus; the input end of the digital-to-analog converter 21 is connected to the control module 1, and the output end of the digital-to-analog converter 21 is connected to the input end of the signal amplification module of the DSI3 simulation circuit 22, that is, the digital-to-analog converter 21 is connected between the control module 1 and the signal amplification module of the DSI3 simulation circuit 22. Figure 6 The test simulation device includes N data transmission channels 2, namely CH1 to CHN, where N is an integer greater than or equal to 1.

[0052] In one example, the control module 1 can send a first digital signal representing the information to be sent to at least one data transmission channel 2, and the control module 1 can receive a first digital signal representing the voltage to be sent from a host computer or a connected PC, that is, the control module 1 can only be used to transmit signals. In other examples, the control module 1 can also be used to generate a first digital signal.

[0053] In the specified data transmission channel:

[0054] The digital-to-analog converter 21 is used to convert the received first digital signal to obtain a corresponding first analog voltage signal, and send the first analog voltage signal as a DSI3 master device simulation voltage signal to the DSI3 simulation circuit 22; the DSI3 simulation circuit 22 outputs a corresponding voltage signal to the DSI3 bus based on the DSI3 master device simulation voltage signal. It can be seen that the digital-to-analog converter can be used to convert the first digital signal into a DSI3 master device simulation voltage signal and send it to the signal amplification module.

[0055] Furthermore, each data transmission channel of the test simulation device also includes: an analog-to-digital converter 23 and a current detection circuit 24; the current detection circuit 24 is used to detect the current in the bus and send the first current detection signal obtained by the detection to the analog-to-digital converter 23; the analog-to-digital converter 23 is used to perform analog-to-digital conversion on the first current detection signal and then send it to the control module 1.

[0056] In one example, the current detection circuit includes: a first amplification module and a current detection module.

[0057] The current detection module is used to detect the current in the bus and send the detected second current detection signal to the first amplification module.

[0058] The first amplifying module is used to amplify the second current detection signal to obtain a first current detection signal and output it to the analog-to-digital converter.

[0059] The following is a specific circuit structure diagram of a current detection circuit. Please refer to Figure 7 It should be noted that other existing current detection circuits can also be used in this application to implement the current detection function.

[0060] In the current detection circuit, the non-phase input terminal of the differential amplifier U3 is connected to the bus through the resistor R14, and the inverting input terminal of the differential amplifier U3 is connected to the bus through the resistor R15. A capacitor C5 is connected between the non-phase input terminal and the inverting input terminal of the differential amplifier U3. The output terminal of the differential amplifier U3 is connected to the first end of the resistor R16, and the second end of the resistor R16 is connected to the analog-to-digital converter. The second end of the resistor R16 is also connected to the analog ground AGND through the capacitor C6. Among them, the non-inverting input terminal of the differential amplifier U3 is also connected to the analog ground AGND through a resistor R17, and a capacitor C7 is connected in parallel across the resistor R17. The output terminal of the differential amplifier U3 is also connected to the inverting input terminal of the differential amplifier U3 through a resistor R18, and a capacitor C8 is connected in parallel across the resistor R18. The power supply terminal of the differential amplifier U3 is connected to the voltage source VQ through a resistor R19, and the power supply terminal of the differential amplifier U3 is also connected to the analog ground AGND through a capacitor C9, and a capacitor C10 is connected in parallel across the capacitor C9. The ground terminal of the differential amplifier U3 is connected to the VSS terminal through a resistor R20, and the ground terminal of the differential amplifier U3 is also connected to the analog ground AGND through a capacitor C11, and a capacitor C12 is connected in parallel across the capacitor C10.

[0061] From the above, in the test simulation device, a single data transmission channel can send a voltage signal to the DSI3 bus, and at the same time, the current detection circuit can be used to detect the current signal on the bus. That is to say, a single data transmission channel can meet the hardware requirements of sending electrical signals to the bus and detecting the current signal on the bus when the master device node is simulated.

[0062] In one example, the data transmission channel also includes: a current control circuit; the current control circuit is connected to a digital-to-analog converter; the digital-to-analog converter is used to convert a received second digital signal (for example, from a control module or a host computer) to obtain a corresponding second analog signal, and send the second analog signal to the current control circuit; the current control circuit is used to control the current on the bus based on the second analog signal, so as to transmit the required information through changes in the current.

[0063] In one example, the data transmission channel also includes: a voltage detection circuit; the voltage detection circuit is used to detect the voltage in the bus and send the detected first voltage detection signal to the analog-to-digital converter; the analog-to-digital converter is also used to perform analog-to-digital conversion on the first voltage detection signal and send it to the control module.

[0064] The above test simulation device is further described in detail below, as follows:

[0065] The test simulation device includes: a control module and at least one data transmission channel, each data transmission channel includes: a signal detection circuit and a signal output circuit respectively connected to the control module. The control module and the data transmission channel can be respectively arranged on different circuit boards, or arranged on the same circuit board.

[0066] The signal detection circuit is used to detect the current and / or voltage on the bus, and send the detected current detection signal and / or voltage detection signal to the control module.

[0067] The control module is used to send a digital signal (originating from the control module or a host computer or other devices) to a digital-to-analog converter in at least one data transmission channel.

[0068] The digital-to-analog converter converts the received digital signal to obtain a corresponding analog voltage signal, and sends the analog voltage signal as a DSI3 master device simulation voltage signal to the DSI3 simulation circuit.

[0069] The DSI3 emulation circuit is used to emulate a voltage signal based on the DSI3 master device and output a corresponding voltage signal to the DSI3 bus.

[0070] The data transmission channel of the test simulation device of this embodiment integrates the functions of detecting the voltage signal and current signal in the bus, sending a voltage signal to the bus, and controlling the current in the bus, that is, a single data transmission channel has a path for detecting and outputting voltage signals, and a path for detecting and controlling current. Thus, the communication possibilities between the simulation board and the DSI3 bus are effectively enriched. Furthermore, a hardware foundation is provided for more diverse simulation possibilities and uses of the simulation device. The test simulation device can be a device based on the DIS3 protocol, which can be in the form of a board, a circuit board, a device, etc.

[0071] As described above, since the test simulation device integrates the circuit part for feeding back voltage to the DSI3 bus, the circuit part for feeding back current to the DSI3 bus, the circuit part for detecting voltage from the DSI3 bus, and the circuit part for detecting current from the DSI3 bus, the communication possibilities between the simulation board and the DSI3 bus are effectively enriched. Furthermore, the hardware foundation is provided for more diverse simulation possibilities and uses of the test simulation device.

[0072] The test simulation device of this embodiment is described in further detail below, wherein only one data transmission channel in the test simulation device is schematically taken as an example.

[0073] The control module may include at least one of the following: a processor, a microcontroller, and an FPGA circuit. Taking the control module as an FPGA circuit as an example, the FPGA circuit can be connected to the PC and RTPC via a CAN bus or a CANFD bus, or an Ethernet module. The FPGA circuit is also connected to the signal detection circuit and the signal output circuit in each data transmission channel.

[0074] Take any data transmission channel in the test simulation device as an example:

[0075] The signal detection circuit includes: an analog-to-digital converter connected to the control module, and a current detection circuit and a voltage detection circuit connected to the analog-to-digital converter.

[0076] The current detection circuit is used to detect the current in the bus, and send the detected first current detection signal to the analog-to-digital converter, which performs analog-to-digital conversion on the first current detection signal and then sends it to the control module.

[0077] The voltage detection circuit is used to detect the voltage in the bus, and send the detected first voltage detection signal to the analog-to-digital converter, which performs analog-to-digital conversion on the first voltage detection signal and sends it to the control module. The voltage signal sent by the voltage detection circuit is detected by the analog-to-digital converter, and can automatically adapt to the bus voltage value of different master device nodes.

[0078] In one example, the current detection circuit includes: a first amplifying module and a current detection module, the input end of the first amplifying module is connected to the output end of the current detection module, and the output end of the first amplifying module is connected to an input end of an analog-to-digital converter.

[0079] The current detection module is used to detect the current in the bus and send the second current detection signal obtained by the detection to the first amplification module.

[0080] The first amplifying module is used to amplify the second current detection signal to obtain a first current detection signal and output it to the analog-to-digital converter.

[0081] In one example, the voltage detection circuit includes: a voltage detection module and a voltage divider module, the output end of the voltage detection module is connected to the voltage divider module, and the output end of the voltage divider module is connected to another input end of the analog-to-digital converter.

[0082] The voltage detection module is used to detect the voltage of the bus and send the detected second voltage detection signal to the voltage dividing module.

[0083] The voltage dividing module is used to divide the second voltage detection signal to obtain a first voltage detection signal and output it to the control module.

[0084] There are two detection paths formed in the signal detection circuit, one is the current detection path, including an analog-to-digital converter, a first amplification module and a current detection module; the other is the voltage detection path, including an analog-to-digital converter, a voltage divider module and a voltage detection module.

[0085] The signal output circuit includes: a digital-to-analog converter connected to the control module, and a DSI3 simulation circuit and a current control circuit connected to the digital-to-analog converter. The DSI3 simulation circuit is the DSI3 simulation circuit in the first embodiment.

[0086] The digital-to-analog converter is used to convert the received digital signal into a corresponding analog signal, and send the first analog signal representing the voltage to be emitted to the DSI3 simulation circuit, and send the second analog signal representing the current to be emitted to the current control circuit.

[0087] The DSI3 simulation circuit is used for outputting a corresponding second voltage signal to the bus based on the first analog signal.

[0088] The current control circuit is used for controlling the current on the bus to produce a corresponding change based on the second analog signal.

[0089] In one example, the DSI3 simulation circuit includes: a second amplification module and a voltage output module, wherein the input end of the second amplification module is connected to the first output end of the digital-to-analog converter, and the output end of the second amplification module is connected to the voltage output module. The second amplification module can be understood as the signal amplification module in the first embodiment.

[0090] The second amplifying module is used for amplifying the received first analog signal and outputting the amplified signal to the voltage output module.

[0091] The voltage output module is used to output a corresponding second voltage signal to a bus based on the amplified first analog signal.

[0092] In one example, the current control circuit includes: a third amplifying module and a current control module. The input end of the third amplifying module is connected to the second output end of the digital-to-analog converter, and the output end of the third amplifying module is connected to the current control module.

[0093] The third amplifying module is used to amplify the received second analog signal and output the amplified signal to the current control module.

[0094] The current control module is used to control the current on the bus to produce corresponding changes based on the amplified second analog signal.

[0095] Two output paths are formed in the signal output circuit, one is a current control path, including a digital-to-analog converter, a third amplification module and a current control module; the other is a voltage output path, including a digital-to-analog converter, a second amplification module and a voltage output module.

[0096] The test simulation device is used as a simulation master device node, wherein the current detection module and the voltage output module are connected to the slave device node through a bus.

[0097] The test simulation device uses the above-mentioned voltage output path to emit voltage to the bus. The specific process is: the control module generates a corresponding digital signal based on the required output voltage and sends it to the digital-to-analog converter. The digital-to-analog converter converts the digital signal into a first analog signal representing the information to be emitted, and then transmits it to the second amplification module. After being amplified by a set multiple by the second amplification module, it is transmitted to the voltage output module. The voltage output module then outputs the corresponding second voltage signal to the bus based on the amplified first analog signal. The slave device node can detect the information sent by the simulated master device node on the bus.

[0098] The test simulation device can use the above-mentioned current detection path to detect the current in the bus. The specific process is: the current detection module detects the current signal on the bus to obtain a second current detection signal sent from the device node. The second current detection signal is transmitted to the first amplification module to be amplified to obtain the first current detection signal, and then transmitted to the analog-to-digital converter. The first current detection signal is an analog signal. The analog-to-digital converter converts it into a corresponding digital signal and feeds it back to the control module. The control module can obtain the information sent from the device node on the bus based on the digital signal sent by the analog-to-digital converter.

[0099] In this embodiment, the control module receives a digital signal representing the information to be sent from the connected PC or host computer, or generates a corresponding digital signal based on the voltage to be sent, wherein the size of the voltage to be sent determined by the control module can be determined based on the required voltage of the currently connected slave device node.

[0100] The test simulation device is used to simulate a slave device node, in which the voltage detection module and the current control module are connected to the master device node through a bus; the test simulation device uses the above-mentioned current control path to control the current on the bus to output a signal. The specific process is: the control module generates a corresponding digital signal based on the required current and sends it to the digital-to-analog converter. The digital-to-analog converter converts the digital signal into a second analog signal representing the current to be emitted and sends it to the third amplification module. After amplification by the third amplification module, it is input into the current control module. The current control module controls the current on the bus to produce corresponding changes based on the amplified second analog signal. The master device node obtains the information emitted by the simulated slave device node based on the detected current on the bus.

[0101] The test simulation device uses the above-mentioned voltage detection path to detect the voltage in the bus. The specific process is: the voltage detection module detects the voltage emitted by the master device node on the bus, obtains a second voltage detection signal and transmits it to the voltage divider module. After voltage division by the voltage divider module, a voltage signal suitable for inputting an analog-to-digital converter is obtained and input into the analog-to-digital converter. The voltage signal is an analog signal, and the analog-to-digital converter converts it into a corresponding digital signal and feeds it back to the control module. The control module can obtain the information sent by the master device node on the bus based on the digital signal sent by the analog-to-digital converter.

[0102] The third embodiment of the utility model relates to a test system, comprising the test simulation device described in the second embodiment.

[0103] Preferred embodiments of the present invention have been described in detail above, but it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide further embodiments.

[0104] These and other changes can be made to the embodiments in light of the above detailed description.In general, in the claims, the terms used should not be considered limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which these claims are entitled.

Claims

1. A DSI3 simulation circuit capable of outputting voltage, characterized in that: include: A master device simulation output channel for connecting to a DSI3 bus, the master device simulation output channel comprising: a signal amplification module, a first transistor, a second transistor and at least one resistor; The collector of the first transistor is connected to a voltage source, the emitter of the first transistor is connected to a signal output terminal of the DSI3 simulation circuit through at least one resistor, the emitter of the second transistor is connected to the signal output terminal through at least one resistor, and the collector of the second transistor is connected to a ground terminal; The output end of the signal amplification module is connected to the base of the first transistor and the base of the second transistor respectively, and the negative feedback end of the signal amplification module is connected to the signal output end; The signal amplification module is used to amplify the received DSI3 master device simulation voltage signal, and send the amplified DSI3 master device simulation voltage signal to the base of the first transistor and the base of the second transistor respectively.

2. The DSI3 simulation circuit according to claim 1, characterized in that: The signal amplification module includes: a first operational amplifier and a second operational amplifier; the non-inverting input terminal of the first operational amplifier is grounded, the inverting input terminal of the first operational amplifier is used to receive the DSI3 master device simulation voltage signal, the output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is grounded, the output terminal of the second operational amplifier is respectively connected to the base of the first transistor and the base of the second transistor, and the inverting input terminal of the second operational amplifier is also connected to the signal output terminal.

3. The DSI3 simulation circuit according to claim 1, characterized in that: The DSI3 simulation circuit also includes: a first current limiting transistor and a second current limiting transistor; the base of the first current limiting transistor is connected to the emitter of the first transistor, and the emitter of the first current limiting transistor is connected to the signal output end; the base of the second current limiting transistor is connected to the emitter of the second transistor, and the emitter of the second current limiting transistor is connected to the signal output end.

4. The DSI3 simulation circuit according to claim 1, characterized in that: The DSI3 simulation circuit further includes: at least one switch module, wherein a control terminal of the switch module is used to receive an external control signal; The switch module is connected between the emitter of the first transistor and the signal output end, and the switch module is connected between the emitter of the second transistor and the signal output end.

5. The DSI3 simulation circuit according to claim 1, characterized in that: The at least one resistor includes a first resistor and a second resistor; The emitter of the first transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the signal output end; The emitter of the second transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the signal output end.

6. The DSI3 simulation circuit according to claim 1, characterized in that: The at least one resistor includes a third resistor; The emitter of the first transistor is connected to the first end of the third resistor, the emitter of the second transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the signal output end.

7. A test simulation device, characterized in that: include: A control module and at least one data transmission channel, the data transmission channel comprising: a digital-to-analog converter, and a DSI3 emulation circuit capable of outputting a voltage as claimed in any one of claims 1 to 6; The digital-to-analog converter is connected between the control module and the signal amplification module, and is used to convert the received first digital signal into the DSI3 master device simulation voltage signal and send it to the signal amplification module.

8. A testing system, characterized in that: The method comprises at least one test simulation device as claimed in claim 7.

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