Multi-communication comprehensive tester

Abstract

The utility model relates to the technical field of aerospace testing, in particular to a multi-communication comprehensive tester, which adopts a COME CPU (central processing unit) main board, a test resource carrier board and a digital multimeter, the test resource carrier board adopts an FPGA (field programmable gate array) chip, and the digital multimeter adopts an FPGA chip. A matrix switch interface, a synchronous 485 bus interface, an asynchronous 422 bus interface, a 1553B bus interface, a synchronous 422 bus interface, an AD acquisition module, a DA output module, an IO channel and a single-pole single-throw relay are expanded on the FPGA chip; according to the utility model, the test resource carrier plate with high integration level is adopted, and the tester is optimally designed, so that the integration level and the portability of the equipment can be improved, and the equipment can be more conveniently carried and used and is suitable for use and test requirements of different sites and requirements.

Description

Technical Field

[0001] The utility model relates to the technical field of aerospace testing, in particular to a multi-communication integrated tester. Background Art

[0002] In the aerospace field, electronic equipment used in aircraft, ships, missiles, etc. needs to be fully tested and verified, including communication systems, navigation systems, radar systems, etc. After the test, functions such as data analysis and report generation are used to help users understand equipment performance and problems.

[0003] The test equipment with a single test function in the prior art has poor comprehensive test capabilities. In addition, the test functions used in electronic equipment such as aviation and aerospace equipment are complex and often require the use of a large number of test equipment, which is inconvenient to carry and use. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a multi-communication integrated tester to solve the problems of poor comprehensive testing capability and low equipment integration of the test equipment with a single test function used in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the utility model provides a multi-communication integrated tester, the tester adopts a COME CPU mainboard, a test resource carrier board and a digital multimeter, the COME CPU mainboard and the test resource carrier board are connected to each other through a PCIe bus communication; the COME CPU mainboard is provided with a USB2.0 interface, and the digital multimeter is connected to the COME CPU mainboard through the USB2.0 interface;

[0006] The test resource carrier board adopts an FPGA chip, and the following are expanded on the FPGA chip:

[0007] A matrix switch interface, wherein the matrix switch interface is a high-density switch interface consisting of 128 cross points and is used for signal switching;

[0008] Synchronous 485 bus interface, the synchronous 485 bus interface adopts isolated synchronous RS485 bus protocol for data communication;

[0009] Asynchronous 422 bus interface, wherein the asynchronous 422 bus interface adopts isolated asynchronous RS422 bus protocol for data communication;

[0010] 1553B bus interface, wherein the 1553B bus interface adopts FC-AE-1553B protocol chip to realize FC-AE-1553B bus test resources;

[0011] Synchronous 422 bus interface, the asynchronous 422 bus interface uses an isolated synchronous RS422 bus protocol for data communication;

[0012] AD acquisition module, the AD acquisition module adopts ADC chip for sampling analog-to-digital data acquisition;

[0013] A DA output module, wherein the DA output module uses a converter chip to output isolated DAC data;

[0014] IO channel, the IO channel uses a TLL driver chip to realize external input and output;

[0015] A single-pole single-throw relay is used for testing the switch control of the resource carrier board.

[0016] In one embodiment of the utility model, a VGA display interface and an Ethernet interface are also provided on the COME CPU mainboard, and a first aviation socket is provided on the VGA display interface and the Ethernet interface for leading out a test signal, and the electronic device to be tested is connected to the tester through the first aviation socket; a second aviation socket is provided on the test resource carrier board, and the test equipment is connected to the test resource carrier board through the second aviation socket; the test end of the digital multimeter is connected to the second aviation socket for measuring the test electrical signal.

[0017] In one embodiment of the present invention, the synchronous 485 bus interface, the asynchronous 422 bus interface, and the synchronous 422 bus interface all use a transceiver model SIT3491ISO.

[0018] In one embodiment of the present invention, the AD acquisition module uses an ADC chip of model ADCS8162, which is a 16-bit chip and uses an 8-channel synchronous sampling analog-to-digital data acquisition system DAS.

[0019] In one embodiment of the present invention, the DA output module uses a converter of model GP8101 / 2.

[0020] In one embodiment of the present invention, the FPGA chip is of model JFM7K325T.

[0021] In one embodiment of the present invention, the FPGA chip is connected to a DDR3 SDRAM, and the DDR3 SDRAM uses two SCB13H4G00AF-13KI chips produced by Unigroup Guoxin.

[0022] In one embodiment of the present invention, the FPGA chip is also connected to a SPI flash, and the FPGA chip is connected to a Flash memory of model EFM25F128A.

[0023] As described above, the multi-communication integrated tester of the utility model has the following beneficial effects:

[0024] 1. By simultaneously expanding the matrix switch interface, asynchronous 422 bus interface, synchronous 422 bus interface, 1553B bus interface, and synchronous 485 bus interface on the test resource carrier, multiple communication protocols can be integrated on the same test platform, which is convenient for access to multiple types of test systems, solves the singleness of the test function of the test platform, and improves the comprehensive test capability of the tester;

[0025] 2. The utility model adopts a test resource carrier with high integration and optimizes the design of the tester, which can improve the integration and portability of the equipment, making the equipment more convenient to carry and use, and adapting to the testing needs of different venues and requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a block diagram of the multi-communication comprehensive tester disclosed by the utility model.

[0027] Figure 2 Shown is a block diagram of a test resource carrier board of a multi-communication integrated tester disclosed in the utility model.

[0028] Figure 3 Shown is a functional block diagram of the COME CPU mainboard of the multi-communication comprehensive tester disclosed in the utility model.

[0029] Figure 4 Shown is an interface diagram of the DDR3 SDRAM of the multi-communication integrated tester disclosed in the utility model.

[0030] Figure 5 Displayed is a Flash chip function diagram of the multi-communication comprehensive tester disclosed in the utility model.

[0031] Figure 6 Shown is an isolated 1553B bus interface diagram of the multi-communication integrated tester disclosed in the utility model.

[0032] Figure 7 Shown is a schematic diagram of isolated analog quantity acquisition of the multi-communication comprehensive tester disclosed in the utility model.

[0033] Figure 8 Shown is a schematic diagram of analog signal conditioning and acquisition circuits of the multi-communication integrated tester disclosed in the utility model.

[0034] Fig. 9 Shown is a schematic diagram of an analog signal output circuit of a multi-communication integrated tester disclosed in the utility model.

[0035] Fig.10Shown is the functional block diagram of the FC-AE-1553B multi-communication integrated tester disclosed in the utility model.

[0036] Component number description

[0037] COME CPU main board 1; test resource carrier board 2; digital multimeter 3; first aviation plug socket 4; second aviation plug socket 5; FPGA chip 6; matrix switch interface 7; asynchronous 422 bus interface 8; 1553B bus interface 9; synchronous 485 bus interface 10; AD acquisition module 11; DA output module 12; IO channel 13; single-pole single-throw relay 14; synchronous 422 bus interface 15. DETAILED DESCRIPTION

[0038] The following is a description of the implementation of the present invention by means of specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0039] See also Figures 1 to 10 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the utility model, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the utility model without affecting the effects and purposes that can be achieved by the utility model. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the utility model. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the utility model without substantially changing the technical content.

[0040] See also Figure 1-3The utility model provides a multi-communication integrated tester, which adopts a COMECPU mainboard 1, a test resource carrier board 2 and a digital multimeter 3. The COME CPU mainboard 1 is connected to the test resource carrier board 2 through a PCIe bus communication; a USB2.0 interface is provided on the COME CPU mainboard 1, and the digital multimeter 3 is connected to the COME CPU mainboard 1 through the USB2.0 interface; a VGA display interface and an Ethernet interface are also provided on the COME CPU mainboard 1, and a first aviation socket 4 is provided on the VGA display interface and the Ethernet interface for leading out a test signal, and the electronic device to be tested is connected to the tester through the first aviation socket 4; a second aviation socket 5 is provided on the test resource carrier board 2, and the test equipment is connected to the test resource carrier board 2 through the second aviation socket 5; the test end of the digital multimeter 3 is connected to the second aviation socket 5 for measuring the test electrical signal.

[0041] See also Figure 2-10 The test resource carrier board 2 adopts an FPGA chip, and a matrix switch interface 7, a synchronous 485 bus interface 10, an asynchronous 422 bus interface 8, a 1553B bus interface 9, a synchronous 422 bus interface 15, an AD acquisition module 11, a DA output module 12, an IO channel 13, and a single-pole single-throw relay 14 are expanded on the FPGA chip 6. The matrix switch interface 7 is a high-density switch interface composed of 128 cross points for signal switching; the synchronous 485 bus interface 10 adopts an isolated synchronous RS485 bus protocol for data communication; the asynchronous 422 bus interface 8 adopts an isolated asynchronous RS422 bus protocol for data communication; the 1553B bus interface 9 adopts an FC-AE-1553B protocol chip to implement FC-AE-1553B bus test resources; the synchronous The 422 bus interface 15 adopts the isolated synchronous RS422 bus protocol for data communication; the AD acquisition module 11 adopts the ADC chip for sampling analog-to-digital data; the DA output module 12 adopts the converter chip for outputting isolated DAC data; the IO channel 13 adopts the TLL driver chip to realize external input and output; the single-pole single-throw relay 14 is used for switch control of the test resource carrier board 2; the utility model can integrate multiple communication protocols on the same test platform by simultaneously expanding the matrix switch interface 7, asynchronous 422 bus interface 8, synchronous 422 bus interface 15, 1553B bus interface 9, and synchronous 485 bus interface 10 on the test resource carrier board 2, so as to facilitate access to various types of test systems, solve the singleness of the test function of the test platform, and improve the comprehensive test capability of the tester.

[0042] The FPGA chip 6 is of the JFM7K325T model, which belongs to the JFM7 product series and is a high-performance FPGA with field programmable features. The JFM7 series FPGA integrates powerful and flexibly configured programmable resources to implement input and output interfaces, general digital logic, memory, digital signal processing, clock management and other functions. It also provides abundant dedicated clock and wiring resources, which are suitable for implementing complex and high-speed data word logic circuits.

[0043] The synchronous 485 bus interface 10, the asynchronous 422 bus interface 8, and the synchronous 422 bus interface 15 all use a transceiver of model SIT3491ISO, which is a full-duplex RS-422 / 485 transceiver with capacitor isolation, and the bus port ESD protection capability HBM reaches more than 15KV, and the functions of the RS-422 / 485 transceiver fully meet the requirements of EIA-422 and TIA / EIA-485 standards; SIT3491ISO includes a driver and a receiver, both of which can be enabled and disabled independently; when both are disabled, the driver and the receiver both output high impedance; SIT3491ISO has a 1 / 8 load, allowing 256 SIT3491ISO transceivers to be connected in parallel on the same communication bus, and can achieve error-free data transmission of more than 16Mbps. In addition, SIT3491ISO also has functions such as failure safety, current limiting protection, overvoltage protection and overheating protection.

[0044] The AD acquisition module 11 uses an ADC chip of model ADCS8162, which is a 16-bit chip and adopts an 8-channel synchronous sampling analog-to-digital data acquisition system DAS; and ADCS8162 adopts a single-power supply working mode, has on-chip filtering and high input impedance, so there is no need to drive the operational amplifier and external bipolar power supply; in addition, the 3dB cutoff frequency of the ADCS8162 anti-aliasing filter is 22KHZ, and when the sampling rate is 200Ksps, it has a 40dB anti-aliasing suppression characteristic; the flexible digital filter is pin-driven, which can improve the signal-to-noise ratio and reduce the 3dB bandwidth.

[0045] See also Figure 7-8 The DA output module 12 uses a converter model GP8101 / 2. GP8101 is a PWM signal to analog signal converter, equivalent to a DAC with a PWM signal input and an analog signal output. This chip can linearly convert a PWM signal with a duty cycle of 0% to 100% into an analog voltage of 0-5V or 0-10V, and the output voltage accuracy is less than 1%; GP8101M can process high-frequency modulated PWM signals, and is used in conjunction with a high-frequency modulated APC chip to isolate analog signals.

[0046] See also Figure 4-5 , the FPGA chip 6 is connected with a DDR3 SDRAM, and the DDR3SDRAM uses two SCB13H4G00AF-13KI of Unigroup Guoxin; the particle interface rate of DDR3 SDRAM is 800MHz, the bit width is 16bits, and the single capacity is 512MB. Two SCB13H4G00AF-13KI are used in parallel to expand the memory capacity, realize 32bits of data bit width, and better access bandwidth; the FPGA chip 6 is also connected with an SPI flash, and the FPGA chip 6 is connected with a Flash memory of model EFM25F128A; this model is a 128M-bit serial interface Flash memory, which is a non-volatile memory, can be written and read multiple times, can be used as a program storage medium in the whole system, and can also be used as a storage medium for small-capacity data, supports standard SPI, dual-port SPI, quad-port SPI, QPI interface, has a write protection function, can be programmed from 1 to 256 bytes at a time, and can perform sector and full chip erase operations.

[0047] In summary, the utility model adopts a highly integrated test resource carrier board 2, optimizes the design of the tester, and can improve the integration and portability of the device, so that the device can be more convenient to carry and use, and adapt to the use and testing needs of different sites and requirements. Therefore, the utility model effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A multi-communication integrated tester, characterized in that: The tester adopts a COME CPU mainboard, a test resource carrier board and a digital multimeter, and the COME CPU mainboard and the test resource carrier board are connected to each other through a PCIe bus communication; the COME CPU mainboard is provided with a USB2.0 interface, and the digital multimeter is connected to the COME CPU mainboard through the USB2.0 interface; The test resource carrier board adopts an FPGA chip, and the following are expanded on the FPGA chip: A matrix switch interface, wherein the matrix switch interface is a high-density switch interface consisting of 128 cross points and is used for signal switching; Synchronous 485 bus interface, the synchronous 485 bus interface adopts isolated synchronous RS485 bus protocol for data communication; Asynchronous 422 bus interface, wherein the asynchronous 422 bus interface adopts isolated asynchronous RS422 bus protocol for data communication; 1553B bus interface, wherein the 1553B bus interface adopts FC-AE-1553B protocol chip to realize FC-AE-1553B bus test resources; Synchronous 422 bus interface, the asynchronous 422 bus interface uses an isolated synchronous RS422 bus protocol for data communication; AD acquisition module, the AD acquisition module adopts ADC chip for sampling analog-to-digital data acquisition; A DA output module, wherein the DA output module uses a converter chip to output isolated DAC data; IO channel, the IO channel uses a TLL driver chip to realize external input and output; A single-pole single-throw relay is used for testing the switch control of the resource carrier board.

2. The multi-communication integrated tester according to claim 1, characterized in that: The COME CPU mainboard is also provided with a VGA display interface and an Ethernet interface, and the VGA display interface and the Ethernet interface are provided with a first aviation socket for leading out a test signal, and the electronic device to be tested is connected to the tester through the first aviation socket; the test resource carrier is provided with a second aviation socket, and the test equipment is connected to the test resource carrier through the second aviation socket; The test end of the digital multimeter is connected to the second aviation socket for measuring the test electrical signal.

3. The multi-communication integrated tester according to claim 1, characterized in that: The synchronous 485 bus interface, the asynchronous 422 bus interface and the synchronous 422 bus interface all use a transceiver of model SIT3491ISO.

4. The multi-communication integrated tester according to claim 1, characterized in that: The AD acquisition module uses an ADC chip of model ADCS8162, which is a 16-bit chip and adopts an 8-channel synchronous sampling analog-to-digital data acquisition system DAS.

5. The multi-communication integrated tester according to claim 1, characterized in that: The DA output module adopts a converter of model GP8101 / 2.

6. The multi-communication integrated tester according to claim 1, characterized in that: The FPGA chip is of model JFM7K325T.

7. The multi-communication integrated tester according to claim 1, characterized in that: The FPGA chip is connected to a DDR3 SDRAM, and the DDR3 SDRAM uses two SCB13H4G00AF-13KI chips produced by Unigroup Guoxin.

8. The multi-communication integrated tester according to claim 7, characterized in that: The FPGA chip is also connected to a SPI flash, and the FPGA chip is connected to a Flash memory of model EFM25F128A.

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