Waveform generator

Abstract

A waveform generator is applied to the field of waveform generation and comprises a storage unit; the waveform data generation system comprises a first processing unit and a second processing unit; the first processing unit is used for generating digital waveform data and storing the digital waveform data to a preset address of the storage unit; the second processing unit comprises a waveform generation module, and the waveform generation module is used for obtaining a preset address, obtaining digital waveform data from the storage unit based on the preset address, and processing the digital waveform data to obtain processed digital waveform data; and the waveform output channel is used for at least performing digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform and outputting the analog waveform. The waveform generation module changes from passive acquisition of waveform data to active acquisition of waveform data, so that the first processing unit removes an intermediate device for reading the waveform data, and the waveform can be flexibly output.

Description

Technical Field

[0001] The present application relates to the technical field of waveform generation, and in particular to a waveform generator. Background Art

[0002] A waveform generator is an electronic test device used to generate function signals such as waveforms. It is an important signal source. Some waveform generators also have modulation functions, which can modulate the output signal with additional functions such as amplitude modulation and frequency modulation. Therefore, waveform generators are widely used in circuit teaching, development and design, and electronic product testing.

[0003] In the current technical solution, the waveform generator usually generates waveforms based on independent CPU and FPGA, where the waveform data is generated by the CPU and stored in its corresponding storage, and then transmitted to the corresponding storage of the FPGA. Then the FPGA reads the waveform data from its own corresponding storage and sends it to the digital-to-analog converter for digital-to-analog conversion, and finally outputs the corresponding waveform after passing through a low-pass filter. However, since the CPU and FPGA need to store data separately, the entire system requires two DRAM memories and DRAM controllers, which is costly and wastes storage space, and the transmission process of waveform data is relatively complicated.

[0004] There are also technical solutions that generate waveforms based on SOC (System on Chip), which integrates CPU and FPGA. Although it can reduce the DRAM memory on the FPGA side, it sacrifices the flexibility of waveform output, so that the output of sequence waveforms is limited. Therefore, new technical solutions need to be proposed. Utility Model Content

[0005] The main technical problem solved by the present application is that the waveform generator has high cost and the waveform generation process is inflexible.

[0006] According to a first aspect, an embodiment provides a waveform generator, comprising:

[0007] A storage unit for storing data;

[0008] A waveform data generating system, comprising a first processing unit and a second processing unit, wherein the second processing unit comprises a waveform generating module; the first processing unit and the waveform generating module are respectively connected to the storage unit, and the first processing unit is also connected to the waveform generating module; the first processing unit is used to generate digital waveform data, and store the digital waveform data to a preset address of the storage unit, and send the preset address to the waveform generating module; the waveform generating module obtains the preset address, obtains the digital waveform data from the storage unit based on the preset address, and processes the digital waveform data to obtain the processed digital waveform data;

[0009] A waveform output channel is connected to the waveform generation module to obtain the processed digital waveform data; the waveform output channel is used to perform at least digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform, and output the analog waveform.

[0010] In some embodiments, the waveform data generating system further includes a storage control unit, the first processing unit and the waveform generating module are respectively connected to the storage unit through the storage control unit, and the storage control unit is used to control the storage unit to store data and read data;

[0011] The first processing unit outputs the digital waveform data to the storage control unit, and the storage control unit controls the storage unit to store the digital waveform data to the preset address;

[0012] The waveform generation module outputs the preset address to the storage control unit, and the storage control unit reads the digital waveform data from the storage unit according to the preset address and outputs it to the waveform generation module.

[0013] In some embodiments, the second processing unit further includes a bus interface, and the waveform generating module outputs the preset address to the storage control unit through the bus interface, and obtains the digital waveform data from the storage control unit.

[0014] In some embodiments, the waveform data generation system is a system on a chip.

[0015] In some embodiments, the first processing unit is a CPU, and the second processing unit is an FPGA.

[0016] In some embodiments, the storage unit is a DRAM memory, and the storage control unit is a DRAM controller.

[0017] In some embodiments, the waveform output channel includes a digital-to-analog converter and a low-pass filter connected in sequence;

[0018] The digital-to-analog converter is connected to the waveform generating module to obtain the processed digital waveform data; the digital-to-analog converter performs digital-to-analog conversion on the processed digital waveform data to obtain analog waveform data, and outputs the analog waveform data to the low-pass filter; the low-pass filter performs low-pass filtering on the analog waveform data to obtain an analog waveform, and outputs the analog waveform.

[0019] According to a second aspect, an embodiment provides a waveform generator, comprising:

[0020] A storage unit for storing data;

[0021] A waveform data generating system, comprising a first processing unit and a second processing unit; the first processing unit and the second processing unit are respectively connected to the storage unit, and the first processing unit is also connected to the second processing unit; the first processing unit is used to generate digital waveform data, the digital waveform data includes at least one waveform segment data, the first processing unit stores the at least one waveform segment data to the preset addresses corresponding to the storage unit, and sends each of the preset addresses to the second processing unit; the second processing unit obtains each of the preset addresses, obtains the corresponding waveform segment data from the storage unit based on each of the preset addresses, and processes the at least one waveform segment data to obtain processed digital waveform data;

[0022] A waveform output channel is connected to the second processing unit to obtain the processed digital waveform data; the waveform output channel is used to perform at least digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform, and output the analog waveform.

[0023] In some embodiments, the waveform data generating system is a system on chip, the first processing unit is a CPU, and the second processing unit is an FPGA.

[0024] In some embodiments, the waveform data generating system further includes a storage control unit, the first processing unit and the second processing unit are respectively connected to the storage unit through the storage control unit, and the storage control unit is used to control the storage unit to store data and read data;

[0025] The first processing unit outputs the at least one waveform segment data to the storage control unit, and the storage control unit controls the storage unit to store the at least one waveform segment data to the corresponding preset address respectively;

[0026] The second processing unit outputs each of the preset addresses to the storage control unit, and the storage control unit reads the corresponding waveform segment data from the storage unit according to each of the preset addresses and outputs the data to the second processing unit.

[0027] According to the waveform generator of the above embodiment, the first processing unit generates digital waveform data and stores the digital waveform data in a preset address of the storage unit. The waveform generation module obtains the preset address and obtains the digital waveform data from the storage unit according to the preset address. The waveform generation module processes the digital waveform data and sends it to the waveform output channel. Finally, the waveform output channel performs at least digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform and outputs the analog waveform. Since the waveform generation module changes from passively obtaining waveform data based on the control of the first processing unit to actively obtaining digital waveform data from the storage unit according to the preset address, it is not necessary to rely on the first processing unit to control the transmission of waveform data, so that the first processing unit can remove the intermediate device for reading waveform data to reduce the cost of the waveform generator. In addition, after removing the intermediate device for reading waveform data, the transfer of waveform data in the intermediate device can be reduced, thereby simplifying the transmission process of waveform data. Moreover, after the reading of waveform data no longer depends on the intermediate device, the waveform generation module actively obtains digital waveform data from the storage unit, so that the way of reading waveform data is no longer restricted by the intermediate device, so that the waveform can be output more flexibly. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the structure of a waveform generator according to an embodiment;

[0029] Figure 2 is a structural schematic diagram of a waveform generator of another embodiment;

[0030] Figure 3 A schematic structural diagram of a waveform generator according to another embodiment;

[0031] Figure 4 A waveform generation diagram according to an embodiment of the present invention is shown in FIG. DETAILED DESCRIPTION

[0032] The present application is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments use associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and the related operations can be fully understood according to the description in the specification and the general technical knowledge in the art.

[0033] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0034] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0035] In the current technical solution, when waveforms are generated based on independent CPUs and FPGAs, since the communication line delay between the CPU and FPGA is relatively high, the CPU and FPGA require their own corresponding memories to store waveform data, which results in high costs and a relatively complex waveform data transmission process.

[0036] When waveforms are generated based on SOC, since the CPU and FPGA are in the same system on chip, the CPU and FPGA can share a memory, thereby reducing the amount of memory and reducing costs. However, in the process of generating waveforms, the CPU generates waveform data and stores it in the memory. Then the CPU sends the storage address to DMA (Direct Memory Access), and then DMA obtains the waveform data from the memory according to the storage address and transmits it to FPGA. Finally, FPGA processes the waveform data and performs analog-to-digital conversion and low-pass filtering to obtain the output waveform.

[0037] However, in the above-mentioned waveform generation process, the control of waveform data transmission is based on the CPU. For example, the CPU needs to generate waveform data and store it, and also needs to control the reading of waveform data based on DMA and transmit it to FPGA. Since the waveform data is read by DMA and then transmitted to FPGA, the waveform data is transmitted multiple times, making the waveform data transmission process relatively complicated.

[0038] Moreover, DMA can only read sequentially from the storage address specified by the memory, so it can only generate one waveform. When a sequence waveform of multiple waveforms needs to be generated, the multiple waveforms need to be spliced ​​into one waveform first, and then stored in sequence and read by DMA and sent to FPGA. At this time, the memory must provide continuous storage space, and when a certain waveform needs to be played repeatedly, it needs to occupy multiple storage space, making it impossible to flexibly control the waveform output.

[0039] In some embodiments of the present application, when the waveform is generated, the first processing unit is used to generate waveform data and store it in the storage unit, while the second processing unit changes from passively acquiring waveform data to actively acquiring waveform data from the storage unit and processing the waveform data. For example, after the CPU generates waveform data, the waveform data is stored in the preset address of the memory, and the FPGA actively acquires the waveform data from the memory according to the preset address. Compared with the control of waveform data transmission by the CPU, the FPGA in the present application changes from passively acquiring waveform data to actively acquiring waveform data, so there is no need to perform data transmission control based on the CPU, firstly, the DMA corresponding to the CPU can be reduced, thereby reducing costs. Secondly, after canceling DMA, the waveform data does not need to be read through DMA but is directly transmitted to the FPGA, thereby reducing the number of transmissions of the waveform data and simplifying the transmission process of the waveform data. In addition, since the FPGA actively acquires waveform data without passing through DMA, it can acquire waveform data at any address in the memory, which is not limited by the DMA reading method, so that the waveform can be flexibly output, making the waveform generation process more flexible.

[0040] In some embodiments, a waveform generator is provided, which is used to generate and output a desired waveform. Figure 1 The waveform generator includes a storage unit 10, a waveform data generating system 20 and a waveform output channel 30, which are described in detail below.

[0041] The storage unit 10 is used to store data. In some embodiments, the storage unit 10 is used to store waveform data, and the storage unit 10 can select a corresponding number of memories and a corresponding type of memory according to requirements, for example, a DRAM (Dynamic Random Access Memory, DRAM) memory can be selected.

[0042] Please refer to Figure 2 and 3 The waveform data generating system 20 is an integrated system, which includes a first processing unit 22 and a second processing unit 24. The first processing unit 22 is used to generate digital waveform data and store the digital waveform data to a preset address of the storage unit 10. The second processing unit 24 includes a waveform generating module 242, which is used to obtain a preset address for storing waveform data, obtain digital waveform data from the storage unit 10 based on the preset address, and process the digital waveform data to obtain processed digital waveform data.

[0043] In some embodiments, the waveform data generation system 20 may be a SOC, wherein the first processing unit 22 may use a CPU, and the second processing unit 24 may use an FPGA. In some embodiments, the first processing unit 22 may generate corresponding digital waveform data based on the parameter configuration input by the user, which may include parameter configurations such as the type, frequency, and initial phase of the waveform. After the first processing unit 22 generates digital waveform data and stores it in a preset address of the storage unit 10, the first processing unit 22 may transmit the preset address to the waveform generation module 242, and the waveform generation module 242 then obtains the digital waveform data from the storage unit 10 based on the preset address. In some embodiments, the preset address may be the starting address and data length of the data storage, or the starting address and end address of the data storage, as long as the unique storage location of the data can be determined based on the preset address. In some embodiments, the waveform generation module 242 is used to perform filtering processing, calculation processing, and other processing on the digital waveform data.

[0044] In some embodiments, the digital waveform data generated by the first processing unit 22 includes at least one waveform segment data. When the digital waveform data includes multiple waveform segment data, the multiple waveform segment data can be stored in different preset addresses of the storage unit 10, or can be spliced ​​to obtain one waveform segment data and then stored. In some embodiments, when the digital waveform data includes repeated waveform segment data, the repeated waveform segment data can be stored in different preset addresses of the storage unit 10, or can be stored in the same preset address of the storage unit 10, that is, stored once.

[0045] In some embodiments, the waveform data generating system 20 further includes a storage control unit 26, which is used to control the storage unit 10 to store data and read data. In some embodiments, the first processing unit 22 outputs the digital waveform data to the storage control unit 26, and the storage control unit 26 controls the storage unit 10 to store the digital waveform data to a preset address. The waveform generating module 242 outputs the preset address to the storage control unit 26, and the storage control unit 26 reads the digital waveform data from the storage unit 10 according to the preset address and outputs it to the waveform generating module 242. In some embodiments, the storage control unit 26 may correspond to the storage unit 10, for example, when the storage unit 10 is a DRAM memory, the storage control unit 26 may be a DRAM controller. In this embodiment, based on the storage control unit 26, the first processing unit 22 and the second processing unit 24 can better share the same storage unit 10.

[0046] Please refer to Figure 3 In some embodiments, the second processing unit 24 further includes a bus interface 244, and the waveform generation module 242 outputs a preset address to the storage control unit 26 through the bus interface 244, and obtains digital waveform data from the storage control unit 26. In some embodiments, the bus interface 244 needs to be suitable for the communication bus of the waveform data generating system 20. For example, when the waveform data generating system 20 is a SOC, the bus interface 244 can be an AXI interconnect interface. In some embodiments, the first processing unit 22 can also transmit the digital waveform data generated by it to the storage control unit 26 through its corresponding bus interface 244. In this embodiment, the waveform data can be better transmitted based on the bus interface 244.

[0047] The waveform output channel 30 is used to perform at least digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform, and output the analog waveform.

[0048] In some embodiments, the waveform output channel 30 includes a digital-to-analog converter 32 and a low-pass filter 34, wherein the digital-to-analog converter 32 is used to perform digital-to-analog conversion on digital waveform data to obtain analog waveform data, and the low-pass filter 34 is used to filter the analog waveform data to obtain an analog waveform.

[0049] The above is some description of the waveform generator. The following is a specific description of the process of the waveform generator generating a waveform.

[0050] Please refer to Figure 4, the first processing unit 22 generates digital waveform data, and stores the digital waveform data to a preset address of the storage unit 10 based on the storage control unit 26, and then the first processing unit 22 sends the preset address to the waveform generation module 242 of the second processing unit 24. The waveform generation module 242 actively obtains the digital waveform data according to the preset address, and reads the digital waveform data from the storage unit 10 based on the storage control unit 26. After processing the digital waveform data, the waveform generation module 242 sends it to the waveform output channel 30. Finally, the waveform output channel 30 performs digital-to-analog conversion and low-pass filtering on the processed digital waveform data to obtain an analog waveform, and outputs the analog waveform.

[0051] In the above embodiment, after the first processing unit 22 generates waveform data and stores it, the waveform generating module 242 obtains the preset address for storing the waveform data, and actively obtains the waveform data from the storage unit 10 based on the preset address. Compared with the first processing unit 22 controlling the reading of the waveform data and transmitting it to the waveform generating module 242, the waveform generating module 242 changes from passively obtaining the waveform data to actively obtaining the waveform data. Firstly, the data processing amount of the first processing unit 22 can be reduced, and the data processing capability of the waveform generating module 242 can be utilized, so that the first processing unit 22 does not need to read the waveform data of the storage unit 10 based on DMA, thereby reducing the intermediate device DMA and reducing the cost of the waveform generator. Secondly, after the waveform generating module 242 actively obtains the waveform data from the storage unit 10, on the one hand, it will not be restricted by DMA in the reading method of the waveform data, so that the required waveform data can be read arbitrarily, so that the waveform output is flexible. On the other hand, the waveform data does not need to be transferred through the intermediate device DMA, thereby reducing the number of transmissions of the waveform data and simplifying the transmission process of the waveform data.

[0052] In some embodiments, when the digital waveform data includes multiple waveform segment data, the first processing unit 22 stores the multiple waveform segment data in different preset addresses of the storage unit 10, and the waveform generation module 242 obtains the corresponding waveform segment data from the storage unit 10 based on the different preset addresses. In this embodiment, the waveform generation module 242 can obtain the corresponding waveform segment data from the storage unit 10 according to each preset address, so that there is no need to splice the multiple waveform segment data and store them in the storage unit 10, and the storage unit 10 does not need to provide continuous storage space, so that the waveform generation process is also more flexible.

[0053] In some embodiments, when the digital waveform data includes repeated waveform segment data, the first processing unit 22 stores the repeated waveform segment data in the same preset address of the storage unit 10, and the waveform generation module 242 repeatedly obtains the repeated waveform segment data from the storage unit 10 based on the same preset address. In this embodiment, the waveform generation module 242 can repeatedly obtain the corresponding waveform segment data from the storage unit 10 based on the same preset address, so that the repeated waveform segment data does not need to be spliced ​​and stored in the storage unit 10, which saves the storage space of the storage unit 10 and makes the waveform generation process more flexible.

[0054] In the above embodiment, the waveform generation module 242 can output the waveform more flexibly after actively acquiring the waveform data from the storage unit 10. For example, multiple waveform segment data can be stored and read separately, for example, repeated waveform segment data only needs to be stored once, and the waveform segment data can be repeatedly read to output the repeated waveform segment data, thereby reducing the storage space requirement of the storage unit 10 and achieving flexible output waveform.

[0055] The above is some description of one process of a waveform generator generating a waveform. The following is a specific description of another process of a waveform generator generating a waveform.

[0056] The first processing unit 22 generates digital waveform data, which includes at least one waveform segment data, and stores at least one waveform segment data to the preset address corresponding to the storage unit 10 based on the storage control unit 26, and then the first processing unit 22 sends each preset address to the second processing unit 24. The second processing unit 24 actively obtains the digital waveform data according to the preset address, and reads the corresponding waveform segment data from the storage unit 10 based on the storage control unit 26. After processing the at least one waveform segment data, the second processing unit 24 sends it to the waveform output channel 30. Finally, the waveform output channel 30 performs digital-to-analog conversion and low-pass filtering on the processed digital waveform data to obtain an analog waveform, and outputs the analog waveform.

[0057] In some embodiments, when at least one waveform segment data includes repeated waveform segment data, the first processing unit 22 stores the repeated waveform segment data to the same preset address of the storage unit 10, and the second processing unit 24 repeatedly obtains the repeated waveform segment data from the storage unit 10 based on the same preset address.

[0058] In the above embodiment, the second processing unit 24 changes from passively acquiring waveform data to actively acquiring waveform data. First, the data processing amount of the first processing unit 22 can be reduced, and the data processing capability of the second processing unit 24 can be utilized, so that the first processing unit 22 no longer needs to read the waveform data of the storage unit 10 based on DMA, thereby reducing the intermediate device DMA and reducing the cost of the waveform generator. Secondly, after the second processing unit 24 actively acquires the waveform data from the storage unit 10, on the one hand, it will not be restricted by DMA in the reading method of the waveform data, so that it can acquire the corresponding waveform segment data from the storage unit 10 based on each preset address, so that the waveform output is flexible. On the other hand, the waveform data no longer needs to be transferred through the intermediate device DMA, thereby reducing the number of transmissions of the waveform data and simplifying the transmission process of the waveform data.

[0059] The above specific examples are used to illustrate the present application, which is only used to help understand the present application and is not intended to limit the present application. For technicians in the technical field to which the present application belongs, they can also make some simple deductions, deformations or substitutions based on the ideas of the present application.

Claims

1. A waveform generator, characterized in that: include: A storage unit for storing data; A waveform data generating system, comprising a first processing unit and a second processing unit, wherein the second processing unit comprises a waveform generating module; the first processing unit and the waveform generating module are respectively connected to the storage unit, and the first processing unit is also connected to the waveform generating module; the first processing unit is used to generate digital waveform data, store the digital waveform data in a preset address of the storage unit, and send the preset address to the waveform generating module; The waveform generation module obtains the preset address to obtain the digital waveform data from the storage unit based on the preset address, and processes the digital waveform data to obtain processed digital waveform data; A waveform output channel connected to the waveform generation module to obtain the processed digital waveform data; The waveform output channel is used to perform at least digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform, and output the analog waveform.

2. The waveform generator according to claim 1, characterized in that The waveform data generating system further comprises a storage control unit, wherein the first processing unit and the waveform generating module are respectively connected to the storage unit through the storage control unit, and the storage control unit is used to control the storage unit to store data and read data; The first processing unit outputs the digital waveform data to the storage control unit, and the storage control unit controls the storage unit to store the digital waveform data to the preset address; The waveform generation module outputs the preset address to the storage control unit, and the storage control unit reads the digital waveform data from the storage unit according to the preset address and outputs it to the waveform generation module.

3. The waveform generator according to claim 2, characterized in that The second processing unit also includes a bus interface, and the waveform generation module outputs the preset address to the storage control unit through the bus interface, and obtains the digital waveform data from the storage control unit.

4. The waveform generator according to any one of claims 1 to 3, characterized in that: The waveform data generating system is a system on a chip.

5. The waveform generator according to claim 4, characterized in that The first processing unit is a CPU, and the second processing unit is an FPGA.

6. The waveform generator according to claim 2, characterized in that The storage unit is a DRAM memory, and the storage control unit is a DRAM controller.

7. The waveform generator according to claim 1, characterized in that The waveform output channel includes a digital-to-analog converter and a low-pass filter connected in sequence; The digital-to-analog converter is connected to the waveform generating module to obtain the processed digital waveform data; the digital-to-analog converter performs digital-to-analog conversion on the processed digital waveform data to obtain analog waveform data, and outputs the analog waveform data to the low-pass filter; the low-pass filter performs low-pass filtering on the analog waveform data to obtain an analog waveform, and outputs the analog waveform.

8. A waveform generator, characterized in that: include: A storage unit for storing data; A waveform data generating system, comprising a first processing unit and a second processing unit; The first processing unit and the second processing unit are connected to the storage unit respectively, and the first processing unit is also connected to the second processing unit; the first processing unit is used to generate digital waveform data, the digital waveform data includes at least one waveform segment data, the first processing unit stores the at least one waveform segment data to the preset addresses corresponding to the storage unit respectively, and sends each of the preset addresses to the second processing unit; the second processing unit obtains each of the preset addresses, obtains the corresponding waveform segment data from the storage unit based on each of the preset addresses, and processes the at least one waveform segment data to obtain processed digital waveform data; A waveform output channel connected to the second processing unit to obtain the processed digital waveform data; The waveform output channel is used to perform at least digital-to-analog conversion on the processed digital waveform data to obtain an analog waveform, and output the analog waveform.

9. The waveform generator according to claim 8, characterized in that The waveform data generation system is a system on chip, the first processing unit is a CPU, and the second processing unit is an FPGA.

10. The waveform generator according to claim 8, characterized in that The waveform data generating system further comprises a storage control unit, wherein the first processing unit and the second processing unit are respectively connected to the storage unit through the storage control unit, and the storage control unit is used to control the storage unit to store data and read data; The first processing unit outputs the at least one waveform segment data to the storage control unit, and the storage control unit controls the storage unit to store the at least one waveform segment data to the corresponding preset address respectively; The second processing unit outputs each of the preset addresses to the storage control unit, and the storage control unit reads the corresponding waveform segment data from the storage unit according to each of the preset addresses and outputs the data to the second processing unit.

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