Junction field effect transistor

Abstract

The utility model provides a junction field effect transistor. The junction field effect transistor comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the field oxide layer is located in the deep trap of the second conduction type and the shallow trap of the first conduction type, and the polysilicon gate is located on the field oxide layer; the shallow well of the first conductive type is located in the deep well of the second conductive type and transversely extends into the semiconductor substrate; the drain electrode region and the source electrode region are located on the two sides of the polysilicon gate; and each shallow trap of the second conduction type longitudinally penetrates through the shallow trap of the first conduction type below the source region, and the ion concentration of the shallow trap of the second conduction type is greater than that of the deep trap of the second conduction type. The junction field effect transistor provided by the utility model can prevent the drain current from being affected when the pinch-off voltage of the junction field effect transistor is adjusted.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a junction field effect transistor. Background Art

[0002] A Junction Field-Effect Transistor (JFET) is a three-terminal active device with amplification capabilities, consisting of a pn junction gate (G), a source (S), and a drain (D). Its operating principle is to control the output current by changing the conductivity of the channel through voltage.

[0003] See Figure 1 and Figure 2 The JFET in a conventional UHV device (i.e., conventional JFET) includes: a P-type semiconductor substrate (P-sub) 01; an N-type deep well (DNW) 02 located in the P-type semiconductor substrate 01; a field oxide layer 07 and a polysilicon gate 08 sequentially stacked on the surface of the N-type deep well 02; an N-type drain region 054 and a P-type gate region 053 on the surface of the N-type deep well 02 on both sides of the field oxide layer 07 below the polysilicon gate 08; an N-type source region 052 located on the surface of the N-type deep well 02, and the field oxide layer 07 is also located between the source region 052 and the gate region 053; a spacer region 04 located below the field oxide layer 07 between the source region 052 and the gate region 053 and passing through the N-type deep well 02; and a P-type drain region 054 and a P-type gate region 053 located on the surface of the N-type deep well 02. A P-type substrate lead-out region 051 on the surface of the P-type semiconductor substrate 01 outside the well 02, and the field oxide layer 07 is also located between the substrate lead-out region 051 and the source region 052; a P-type shallow well 03 located below the gate region 053 and the substrate lead-out region 051; a high-voltage P-type well (HPW) 09 located in the N-type deep well 02 and laterally passing through the P-type shallow well 03 below the gate region 053 and the spacer region 04, the high-voltage P-type well 09 being located between the source region 052 and the drain region 054; a contact hole 06 connected to the substrate lead-out region 051, the source region 052, the gate region 053, the drain region 054 and the polysilicon gate 08, and the contact hole 06 connected to the polysilicon gate 08 is connected to the contact hole connected to the gate region 053. The substrate lead-out region 051 is connected to the substrate electrode (B) through the contact hole 06, the source region 052 is connected to the source (S) through the contact hole 06, the gate region 053 and the polysilicon gate 08 are connected to the gate (G) through the contact hole 06, and the drain region 054 is connected to the drain (D) through the contact hole 06. Figure 3 A circuit diagram showing a conventional JFET in the normally-on state, with no voltage applied to the gate and substrate electrodes. Figure 4This circuit diagram shows a conventional JFET operating state. Negative voltages are applied to the gate and substrate electrodes, creating a depletion region around the high-voltage P-type well 09 and the P-type semiconductor substrate 01. When these depletion regions overlap, the channel is vertically pinched off. Conventional JFETs used in UHV (ultra-high voltage) (≥500V) devices achieve current control by vertically pinching off the lateral channel between the high-voltage P-type well 09 and the P-type semiconductor substrate 01 at spacer region 04.

[0004] Traditional JFETs increase the breakdown voltage (BV) by creating a depletion region around the high-voltage P-type well 09, while also providing channel pinch-off. However, the MV (medium voltage) or LV (low voltage) devices that work with it do not use the high-voltage P-type well 09, so the high-voltage P-type well 09 is only present between the source region 052 and the drain region 054 of the JFET. In addition, traditional JFETs adjust the Vp (pinch-off voltage) by adjusting the size, position, and number of the spacer regions 04 to achieve quantitative control of the output current. However, this adjustment will affect the Id (drain current) of the JFET, as can be seen in the following example. Figure 5 .from Figure 5 As can be seen from the figure, if the pinch-off voltage of 500V JFET and 700V JFET is reduced, the drain current Id will also be significantly reduced. Therefore, the traditional JFET has the following problems:

[0005] First, the high-voltage P-type well only exists in JFETs, and its function is single and its cost is relatively high.

[0006] Second, adjusting the JFET pinch-off voltage (spacer size, location, and number) affects Id. For example, a lower pinch-off voltage requires a larger or more spacer, which results in a lower Id. Utility Model Content

[0007] The purpose of the utility model is to provide a junction field effect transistor to avoid affecting the drain current when adjusting the pinch-off voltage of the junction field effect transistor.

[0008] In order to achieve the above-mentioned and other related purposes, the present invention provides a junction field effect transistor, comprising:

[0009] a semiconductor substrate of a first conductivity type;

[0010] A deep well of a second conductivity type is located in the semiconductor substrate;

[0011] a shallow well of the first conductivity type, located in the deep well of the second conductivity type and extending laterally into the semiconductor substrate;

[0012] a field oxide layer and a polysilicon gate, wherein the field oxide layer is located in a deep well of the second conductivity type and a shallow well of the first conductivity type, and the polysilicon gate is located on the field oxide layer;

[0013] A drain region and a source region are located on both sides of the polysilicon gate, wherein the source region is located on the surface of the shallow well of the first conductivity type, and the drain region is located on the surface of the deep well of the second conductivity type;

[0014] A plurality of shallow wells of the second conductivity type, each shallow well of the second conductivity type longitudinally penetrates the shallow well of the first conductivity type below the source region, the ion concentration of the shallow well of the second conductivity type is greater than the ion concentration of the deep well of the second conductivity type, and the shallow well of the second conductivity type is used to adjust the pinch-off voltage of the junction field effect transistor.

[0015] Optionally, in the junction field effect transistor, a cross-sectional shape of each shallow well of the second conductivity type parallel to the surface of the semiconductor substrate is a polygon.

[0016] Optionally, in the junction field effect transistor, there are multiple shallow wells of the second conductivity type.

[0017] Optionally, in the junction field effect transistor, the ion concentration of the second conductivity type shallow well is one order of magnitude greater than the ion concentration of the second conductivity type deep well.

[0018] Optionally, in the junction field effect transistor, the polarity of the first conductivity type is opposite to the polarity of the second conductivity type.

[0019] Optionally, in the junction field effect transistor, the junction field effect transistor further includes a substrate lead-out region, the substrate lead-out region is spaced apart from the source region, and the substrate lead-out region is located on the surface of the shallow well of the first conductivity type.

[0020] Optionally, in the junction field effect transistor, the junction field effect transistor further includes a gate region, the gate region is located on the surface of the shallow well of the first conductivity type, the gate region is spaced apart from the source region, and the source region is located between the gate region and the substrate lead-out region.

[0021] Optionally, in the junction field effect transistor, the field oxide layer is located between the substrate lead-out region and the source region, between the source region and the gate region, and between the gate region and the drain region.

[0022] Optionally, in the junction field effect transistor, the source region and the drain region are of the second conductivity type, and the substrate lead-out region and the gate region are of the first conductivity type.

[0023] Optionally, in the junction field effect transistor, the junction field effect transistor also includes a contact hole, the substrate lead-out region is connected to the substrate electrode through the contact hole, the gate region and the polysilicon gate are connected to the gate through the contact hole, the source region is connected to the source through the contact hole, and the drain region is connected to the drain through the contact hole.

[0024] Compared with the prior art, the technical solution of the utility model has the following unexpected beneficial effects:

[0025] The junction field effect transistor of the present invention is provided with a plurality of shallow wells of the second conductivity type penetrating the shallow wells of the first conductivity type below the source region. When a negative voltage is applied to the gate and the substrate electrode, a depletion region is formed around the shallow wells of the first conductivity type on both sides of the shallow wells of the second conductivity type. When the depletion regions overlap, the channel of the junction field effect transistor will be laterally pinched off. Moreover, since the ion concentration of the shallow wells of the second conductivity type is greater than the ion concentration of the deep wells of the second conductivity type, the resistance at the shallow wells of the second conductivity type is very small. The shallow wells of the second conductivity type are equivalent to a very small resistor connected in series in the circuit, and their effect on the drain current is very small and can be ignored. The size of the drain current of the junction field effect transistor mainly depends on the deep wells of the second conductivity type. Therefore, the junction field effect transistor provided by the present invention can avoid affecting the drain current when adjusting the pinch-off voltage of the junction field effect transistor.

[0026] Secondly, the junction field effect transistor of the present invention forms a shallow well of the second conductivity type that can be shared with the LV device and the MV device, and does not form a HPW with a single function, which can save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of a traditional junction field effect transistor;

[0028] Figure 2 yes Figure 1 A top view of a conventional junction field effect transistor in FIG.

[0029] Figure 3 This is the circuit diagram of the traditional junction field effect transistor in the normally-on state;

[0030] Figure 4 This is a circuit diagram of a traditional junction field effect transistor in normal working condition;

[0031] Figure 5 This is a graph showing the relationship between drain current and pinch-off voltage for a conventional junction field-effect transistor.

[0032] Figure 6This is a schematic structural diagram of a junction field effect transistor according to an embodiment of the present invention;

[0033] Figure 7 1 is a top view of a shallow well of the second conductivity type according to an embodiment of the present invention;

[0034] Figures 1 to 5 middle:

[0035] 01-semiconductor substrate, 02-N-type deep well, 03-P-type shallow well, 04-spacer region, 051-substrate lead-out region, 052-source region, 053-gate region, 054-drain region, 06-contact hole, 07-field oxide layer, 08-polysilicon gate, 09-high-voltage P-type well;

[0036] Figure 6 middle:

[0037] 10 - semiconductor substrate, 20 - deep well of the second conductivity type, 30 - shallow well of the first conductivity type, 40 - shallow well of the second conductivity type, 501 - substrate lead-out region, 502 - source region, 503 - gate region, 504 - drain region, 60 - contact hole, 70 - field oxide layer, 80 - polysilicon gate. DETAILED DESCRIPTION

[0038] The following is a further detailed description of the junction field-effect transistor proposed in the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0039] See Figure 6 The present invention provides a junction field effect transistor, comprising:

[0040] A semiconductor substrate 10 of a first conductivity type;

[0041] A deep well 20 of a second conductivity type, located in the semiconductor substrate 10;

[0042] A shallow well 30 of the first conductivity type is located in the deep well 20 of the second conductivity type and extends laterally into the semiconductor substrate 10;

[0043] a field oxide layer 70 and a polysilicon gate 80 , wherein the field oxide layer 70 is located in the second conductivity type deep well 20 and the first conductivity type shallow well 30 , and the polysilicon gate 80 is located on the field oxide layer 70 ;

[0044] The drain region 504 and the source region 502 are located on both sides of the polysilicon gate 80 , and the source region 502 is located on the surface of the shallow well 30 of the first conductivity type, and the drain region 504 is located on the surface of the deep well 20 of the second conductivity type;

[0045] A plurality of shallow wells 40 of the second conductivity type are provided, each shallow well 40 of the second conductivity type longitudinally penetrating the shallow well 30 of the first conductivity type below the source region 502, the ion concentration of the shallow well 40 of the second conductivity type being greater than the ion concentration of the deep well 20 of the second conductivity type, and the shallow well 40 of the second conductivity type being used to adjust the pinch-off voltage of the junction field effect transistor.

[0046] In this embodiment, the polarity of the first conductivity type is opposite to that of the second conductivity type. For example, the first conductivity type is P-type and the second conductivity type is N-type, then the junction field effect transistor is an N-channel junction field effect transistor. It should be noted that in other embodiments, the first conductivity type may be N-type and the second conductivity type is P-type. In this embodiment, the device of this example is described by taking the junction field effect transistor as an N-channel junction field effect transistor as an example, that is, in this embodiment, the first conductivity type is P-type and the second conductivity type is N-type. Correspondingly, the semiconductor substrate 10 of the first conductivity type is a P-type substrate, the deep well 20 of the second conductivity type is an N-type deep well, the shallow well 30 of the first conductivity type is a P-type shallow well, and the shallow well 40 of the second conductivity type is an N-type shallow well.

[0047] The semiconductor substrate 10 can be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a germanium substrate, or a silicon carbide substrate, and the semiconductor substrate 10 is a P-type semiconductor substrate, and its P-type ion doping concentration can adopt the P-type ion doping concentration of the semiconductor substrate of a traditional junction field effect transistor, which will not be elaborated here.

[0048] The second conductive type deep well 20 is formed in the semiconductor substrate 10, and the second conductive type deep well 20 is an N-type deep well, and its N-type ion doping concentration can adopt the N-type ion doping concentration of the N-type deep well of the traditional junction field effect transistor, for example, 1E12cm -3 .

[0049] In this embodiment, the second conductivity type deep well 20 is formed in the semiconductor substrate 10 through an ion implantation process. After the ion implantation process, a high-temperature bake process is performed to diffuse the ions in the second conductivity type deep well 20 to a deeper region, thereby increasing the depth of the second conductivity type deep well 20 in the semiconductor substrate 10. The temperature of the high-temperature bake process is preferably greater than 1100° C., and the time is preferably 430 minutes to 500 minutes, for example, 450 minutes.

[0050] The field oxide layer 70 is formed in the second conductivity type deep well 20 and the first conductivity type shallow well 30. In this embodiment, the number of the field oxide layer 70 can be multiple. Specifically, the field oxide layer 70 is provided between the drain region 504 and the gate region 503, between the gate region 503 and the source region 502, and between the source region 502 and the substrate lead-out region 501. In addition, the field oxide layer 70 can also be located between other different device regions to provide isolation.

[0051] In this embodiment, after the step of forming the second conductivity type deep well 20 , the field oxide layer 70 is formed by performing a deposition process or a thermal oxidation process.

[0052] The shallow well 30 of the first conductivity type is lower in depth than the deep well 20 of the second conductivity type. It is located within the deep well 20 of the second conductivity type and extends laterally into the semiconductor substrate 10. Specifically, the shallow well 30 of the first conductivity type extends laterally from the deep well 20 of the second conductivity type on one side of the polysilicon gate 80 into the semiconductor substrate 10 in a direction away from the polysilicon gate 80. That is, the shallow well 30 of the first conductivity type extends from below the edge of the polysilicon gate 80 near the gate region 503 to below the edge of the substrate lead-out region 501 away from the polysilicon gate 80. The shallow well 30 of the first conductivity type is a P-type shallow well, and its P-type ion doping concentration can adopt the P-type ion doping concentration of a P-type shallow well of a conventional junction field-effect transistor, which will not be described in detail here.

[0053] In this embodiment, after forming the field oxide layer 70, an ion implantation process is performed to form the first conductivity type shallow well 30. Following the ion implantation process, a short high-temperature process is performed to activate the ions and remove impurities. The high-temperature process is preferably performed at a temperature of 800°C to 900°C and for a duration of 10 to 20 seconds. During the formation of the first conductivity type shallow well 30, a mask is used to mask the location of the second conductivity type shallow well 40, preventing the first conductivity type ion implantation from occurring in the second conductivity type shallow well 40.

[0054] The number of the second conductivity type shallow well 40 is at least one, preferably multiple. Each second conductivity type shallow well 40 vertically penetrates the first conductivity type shallow well 30 below the source region 502, that is, the second conductivity type shallow well 40 vertically connects the source region 502 and the second conductivity type deep well 20, and can act as a current channel for the junction field effect transistor, and the second conductivity type shallow well 40 can be used to adjust the pinch-off voltage of the junction field effect transistor. The second conductivity type shallow well 40 is an N-type shallow well, and the second conductivity type shallow well 40 is located directly below the source region 502. In this embodiment, the region where the second conductivity type shallow well 40 is located serves as the channel of the junction field effect transistor. When a negative voltage is applied to the gate and substrate electrodes, a depletion region is formed around the first conductivity type shallow well 30 on both sides of the second conductivity type shallow well 40. When the depletion regions overlap, the channel is laterally pinched off. In this embodiment, the ion concentration of the second conductivity type shallow well 40 is greater than the ion concentration of the second conductivity type deep well 20. Furthermore, the ion concentration of the shallow well 40 of the second conductivity type is one order of magnitude greater than the ion concentration of the deep well 20 of the second conductivity type. For example, the concentration of the deep well 20 of the second conductivity type is 1E12cm -3 The ion concentration of the second conductive type shallow well 40 is 1E13cm -3 . Since the ion concentration of the second conductive type shallow well 40 is relatively large, the resistance at the second conductive type shallow well 40 is very small, much smaller than the resistance of the second conductive type deep well 20. The setting of the second conductive type shallow well 40 is equivalent to a very small resistor in series in the circuit, and its effect on the drain current is very small and can be ignored. The greater the ion concentration of the second conductive type shallow well 40 in this embodiment, the narrower the depletion region formed around the first conductive type shallow well 30 will be, and the greater the pinch-off voltage will be; the more the number of the second conductive type shallow wells 40, the wider the channel of the junction field effect transistor will be, and the greater the pinch-off voltage will be; in the state of looking down at the semiconductor substrate 10, the larger the shape and size of the second conductive type shallow well 40, the wider the channel of the junction field effect transistor will be, and the greater the pinch-off voltage will be.

[0055] In a state of looking down at the semiconductor substrate 10, the shape of each shallow well 40 of the second conductivity type may be a polygon (ie, the cross-sectional shape of each shallow well 40 of the second conductivity type parallel to the surface of the semiconductor substrate 10 is a polygon), for example Figure 7In the hexagon. In the present embodiment, each shallow well 40 of the second conductivity type is covered by the shallow well 30 of the first conductivity type. The better the shallow well 40 of the second conductivity type is covered by the shallow well 30 of the first conductivity type (that is, the better the coverage of the shallow well 30 of the first conductivity type), the easier the channel is to be pinched off, and the lower the pinch-off voltage will be. In the state of looking down at the semiconductor substrate 10, the more the cross-sectional shape of the shallow well 40 of the second conductivity type tends to be circular, the better it is covered by the shallow well 30 of the first conductivity type, and the lower the pinch-off voltage. For example, in the state of looking down at the semiconductor substrate 10, the pinch-off voltage when the shape of the shallow well 40 of the second conductivity type is hexagonal is lower than the pinch-off voltage when the shape of the shallow well 40 of the second conductivity type is triangular. In the present embodiment, the cross-sectional shapes of each shallow well 40 of the second conductivity type parallel to the surface of the semiconductor substrate 10 may be the same or different, and are preferably the same. Moreover, when looking down at the semiconductor substrate 10 , the distribution of the second conductive type shallow wells 40 may be uniform or non-uniform, and the more regular and uniform the distribution of the second conductive type shallow wells 40 is, the lower the pinch-off voltage is.

[0056] This embodiment can adjust the pinch-off voltage of the junction field effect transistor by adjusting the shape, size, number, and ion concentration of the second conductive type shallow well 40, while also preventing the drain current from being affected (i.e., when the pinch-off voltage is reduced, the drain current is ensured to remain essentially unchanged). Therefore, without affecting the high current of the junction field effect transistor, the different pinch-off voltage requirements of customers can be met. Moreover, the junction field effect transistor of this embodiment forms a second conductive type shallow well 40 that can be shared with LV devices and MV devices, and does not form a single-function high-voltage P-type well, thereby saving costs.

[0057] In this embodiment, after forming the shallow well 30 of the first conductivity type, the shallow well 40 of the second conductivity type is formed through an ion implantation process. Following the ion implantation process, a short high-temperature process is performed to activate the ions and remove impurities. The temperature of the high-temperature process is preferably 800°C to 900°C, and the duration is preferably 10 to 20 seconds. During the formation of the shallow well 40 of the second conductivity type, the mask used will mask the location of the shallow well 30 of the first conductivity type, so that the second conductivity type ion implantation is not performed in the location of the shallow well 30 of the first conductivity type. In other embodiments, after forming the field oxide layer 70, the shallow well 40 of the second conductivity type may be formed first, and then the shallow well 30 of the first conductivity type may be formed.

[0058] The polysilicon gate 80 is preferably made of polysilicon. In this embodiment, the polysilicon gate 80 can be of P-type or N-type. The polysilicon gate 80 is located on the field oxide layer 70 between the drain region 504 and the gate region 503 .

[0059] In this embodiment, after the step of forming the shallow well 40 of the second conductivity type, the polysilicon gate 80 is formed through a deposition process and an etching process.

[0060] The source region 502 and the drain region 504 are located on both sides of the polysilicon gate 80, with the source region 502 located on the surface of the shallow well 30 of the first conductivity type, and the drain region 504 located on the surface of the deep well 20 of the second conductivity type on the side of the polysilicon gate 80 away from the source region 502. The junction field effect transistor may further include a substrate lead-out region 501 and a gate region 503. The substrate lead-out region 501, the gate region 503, and the source region 502 are spaced apart on the surface of the shallow well 30 of the first conductivity type, and the source region 502 is located between the substrate lead-out region 501 and the gate region 503. The source region 502 and the drain region 504 are of the second conductivity type, and the substrate lead-out region 501 and the gate region 503 are of the first conductivity type. In this embodiment, the substrate lead-out region 501 and the source region 502 , the source region 502 and the gate region 503 , and the gate region 503 and the drain region 504 are separated by the field oxide layer 70 .

[0061] In this embodiment, after the step of forming the polysilicon gate 80, the substrate lead-out region 501, the gate region 503, the source region 502, and the drain region 504 are formed by two ion implantation processes. After each ion implantation process, a short high-temperature process is performed to activate the ions and remove impurities. The temperature of the high-temperature process is preferably 800°C to 900°C, and the time is preferably 10 to 20 seconds. In this embodiment, the source region 502 and the drain region 504 can be formed by a single ion implantation process, and the substrate lead-out region 501 and the gate region 503 can be formed by a single ion implantation process.

[0062] The junction field-effect transistor of this embodiment further includes a contact hole 60. The substrate lead-out region 501 is connected to the substrate electrode via the contact hole 60. The gate region 503 and the polysilicon gate 80 are connected to the gate (G) via the contact hole 60. The source region 502 is connected to the source (S) via the contact hole 60. The drain region 504 is connected to the drain (D) via the contact hole 60. The contact hole 60 can be formed using a conventional junction field-effect transistor contact hole, and the formation process can also be formed using a conventional junction field-effect transistor contact hole formation process, which will not be described in detail here.

[0063] To sum up, the unexpected technical effect of the present application is that multiple shallow wells of the second conductivity type are arranged below the source region, penetrating the shallow well of the first conductivity type. When a negative voltage is applied to the gate and the substrate electrode, a depletion region will be formed around the shallow well of the first conductivity type on both sides of the shallow well of the second conductivity type. When the depletion regions overlap, the channel of the junction field effect transistor will be laterally pinched off. Moreover, since the ion concentration of the shallow well of the second conductivity type is greater than the ion concentration of the deep well of the second conductivity type, the resistance at the shallow well of the second conductivity type is very small. The shallow well of the second conductivity type is equivalent to a very small resistor connected in series in the circuit, and its effect on the drain current is very small and can be ignored. The size of the drain current of the junction field effect transistor mainly depends on the deep well of the second conductivity type. Therefore, the junction field effect transistor provided by the utility model can avoid affecting the drain current when adjusting the pinch-off voltage of the junction field effect transistor.

[0064] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. Any person skilled in the art will be able to utilize the above-disclosed technical content to make many possible changes and modifications to the present invention without departing from the scope of the present invention, or to modify the present invention into equivalent embodiments with equivalent variations. Therefore, any simple modifications, equivalent variations, and modifications to the above embodiments made in accordance with the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

[0065] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the present invention. It should be noted that the singular forms "a," "an," and "the," as used herein and in the appended claims, include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include subsequent steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or," not a logical "exclusive or," unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximating should be so interpreted unless the context clearly indicates otherwise.

Claims

1. A junction field effect transistor, characterized in that: include: a semiconductor substrate of a first conductivity type; A deep well of a second conductivity type, located in the semiconductor substrate; a shallow well of a first conductivity type, located in a deep well of the second conductivity type and extending laterally into the semiconductor substrate; A field oxide layer and a polysilicon gate, wherein the field oxide layer is located in a deep well of the second conductivity type and a shallow well of the first conductivity type, and the polysilicon gate is located on the field oxide layer; A drain region and a source region, located on both sides of the polysilicon gate, wherein the source region is located on the surface of the shallow well of the first conductivity type, and the drain region is located on the surface of the deep well of the second conductivity type; A plurality of shallow wells of the second conductivity type, each of which longitudinally penetrates the shallow well of the first conductivity type below the source region, the ion concentration of the shallow well of the second conductivity type is greater than the ion concentration of the deep well of the second conductivity type, and the shallow well of the second conductivity type is used to adjust the pinch-off voltage of the junction field effect transistor.

2. The junction field effect transistor according to claim 1, characterized in that The cross-sectional shape of each shallow well of the second conductivity type parallel to the surface of the semiconductor substrate is a polygon.

3. The junction field effect transistor according to claim 1, wherein: The number of the second conductive type shallow wells is plural.

4. The junction field effect transistor according to claim 1, characterized in that The ion concentration of the shallow well of the second conductivity type is one order of magnitude greater than the ion concentration of the deep well of the second conductivity type.

5. The junction field effect transistor according to claim 1, wherein: The polarity of the first conductivity type is opposite to the polarity of the second conductivity type.

6. The junction field effect transistor according to claim 1, wherein: The junction field effect transistor further includes a substrate lead-out region, the substrate lead-out region is spaced apart from the source region, and the substrate lead-out region is located on a surface of the shallow well of the first conductivity type.

7. The junction field effect transistor according to claim 6, characterized in that The junction field effect transistor further includes a gate region, the gate region is located on the surface of the shallow well of the first conductivity type, the gate region is spaced apart from the source region, and the source region is located between the gate region and the substrate lead-out region.

8. The junction field effect transistor according to claim 7, characterized in that The field oxide layer is located between the substrate lead-out region and the source region, between the source region and the gate region, and between the gate region and the drain region.

9. The junction field effect transistor according to claim 7, characterized in that: The source region and the drain region are of the second conductivity type, and the substrate lead-out region and the gate region are of the first conductivity type.

10. The junction field effect transistor according to claim 7, characterized in that: The junction field effect transistor also includes a contact hole, through which the substrate lead-out region is connected to the substrate electrode, through which the gate region and the polysilicon gate are connected to the gate, through which the source region is connected to the source, and through which the drain region is connected to the drain.

Images