Power device

Abstract

The utility model discloses a power device which comprises a gate structure, the gate structure is located on the side, away from a substrate, of a second epitaxial layer, the gate structure comprises a gate oxide layer, a gate and a Schottky diode structure, and the gate oxide layer is in contact with a second sub-epitaxial part, a part of the second sub-epitaxial part located between an injection region and a first sub-epitaxial part and a part of an injection region. The gate electrode and the Schottky diode structure are located on the side, away from the substrate, of the gate oxide layer, the Schottky diode structure comprises multiple doping layers arranged in a stacked mode in the second direction, any two adjacent doping layers have different doping types, the gate electrode is located on the side face, in the first direction, of the Schottky diode structure, and the gate electrode is located on the side face of the Schottky diode structure. The doped layer, in contact with the gate oxide layer, in the multiple doped layers is a first doped layer, the gate is in contact with the first doped layer, and the second direction is the direction from the substrate to the first epitaxial layer. The problem of poor electrostatic breakdown resistance of a grid electrode of a power device in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device. Background Art

[0002] Power MOSFET has become an important semiconductor device in power electronic applications due to its low forward voltage drop, high switching speed, and easy gate control. The gate antistatic capability of power MOSFET is directly related to the chip area and gate oxide thickness. Compared with Si MOS devices, SiC MOS devices are limited by material and process characteristics, with small chip area, thin gate oxide thickness, and poor gate antistatic breakdown capability. Utility Model Content

[0003] The present application provides a power device to solve the problem of poor anti-static breakdown capability of the gate of the power device in the related art.

[0004] According to one aspect of the present application, a power device is provided, comprising a substrate and a first epitaxial layer and a second epitaxial layer located on one side of the substrate, the first epitaxial layer having a first doping type, the second epitaxial layer being located on a side of the first epitaxial layer away from the substrate, the second epitaxial layer having a first sub-epitaxial portion and a second sub-epitaxial portion alternately arranged along a first direction, the first sub-epitaxial portion having the first doping type, the second sub-epitaxial portion having a second doping type, the second epitaxial layer having a first surface away from the substrate, the first direction being parallel to the first surface, the power device further comprising: at least one implantation region, the implantation region being located in the second sub-epitaxial portion, the surface of the implantation region away from the substrate being located in the first surface, the implantation region having the first doping type, and a portion of the second sub-epitaxial portion being between the implantation region and the first sub-epitaxial portion. An epitaxial portion; a gate structure, wherein the gate structure is located on a side of the second epitaxial layer away from the substrate, the gate structure includes a gate oxide layer, a gate and a Schottky diode structure, the gate oxide layer is respectively in contact with the first sub-epitaxial portion, a portion of the second sub-epitaxial portion located between the injection region and the first sub-epitaxial portion, and a portion of the injection region, the gate and the Schottky diode structure are respectively located on a side of the gate oxide layer away from the substrate, wherein the Schottky diode structure includes a plurality of doped layers stacked along a second direction, any two adjacent doped layers have different doping types, the gate is located on the side of the Schottky diode structure in the first direction, the doped layer in the plurality of doped layers that is in contact with the gate oxide layer is a first doped layer, the gate is in contact with the first doped layer, and the second direction is a direction from the substrate to the first epitaxial layer.

[0005] Optionally, the Schottky diode structure is located on a side of the first sub-epitaxial portion away from the substrate, and the gate is located on both sides of the Schottky diode structure in the second direction.

[0006] Optionally, the first doping layer and the gate have the same doping type.

[0007] Optionally, the doped layer in contact with the first doped layer in the multiple doped layers is a second doped layer, and in the second direction, the first doped layer has a first thickness, the second doped layer has a second thickness, the gate has a third thickness, and the sum of the first thickness and the second thickness is greater than the third thickness.

[0008] Optionally, the Schottky diode structure further includes a second doping layer and a third doping layer located on a side of the first doping layer away from the substrate and stacked along the second direction, the first doping layer and the third doping layer have N-type doping, and the second doping layer has P-type doping.

[0009] Optionally, the gate oxide layer includes a first region and a second region, the first region is located at least between the Schottky diode structure and the second epitaxial layer, and the rest of the gate oxide layer is the second region, the first region has a fourth thickness in the second direction, the second region has a fifth thickness in the second direction, and the fourth thickness is greater than the fifth thickness.

[0010] Optionally, a projection of the first region in the second direction is located in a surface of the second sub-epitaxial portion facing away from the substrate.

[0011] Optionally, the power device further includes: the first doped layer has a first thickness in the second direction, the gate has a third thickness in the second direction, and the first thickness is smaller than the third thickness.

[0012] Optionally, the first sub-epitaxial portion has a sixth thickness in the second direction, the second sub-epitaxial portion has a seventh thickness in the second direction, and the sixth thickness is greater than or equal to the seventh thickness.

[0013] Optionally, the power device further comprises: a plurality of conductive parts, the conductive parts are respectively in contact with the injection region, the Schottky diode structure and the gate, and the plurality of conductive parts are arranged at intervals.

[0014] By applying the technical solution of the present application, a planar gate power device is provided, in which the gate includes a Schottky diode structure, so that a Schottky barrier diode (SBD) is integrated in the gate, and the gate can be protected. Specifically, the Schottky diode structure includes multiple doping layers, and any two adjacent doping layers have different doping types, so that at least one PN junction is included in the Schottky diode structure, and the gate is in direct contact with the Schottky diode structure. After a voltage is applied to the gate, a conduction circuit can be formed in the Schottky diode structure. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will turn on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, thereby improving the anti-static ability of the planar gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a schematic cross-sectional structure diagram of a power device according to an embodiment of the present application;

[0017] Figure 2 is a schematic cross-sectional structure diagram of another power device according to an embodiment of the present application;

[0018] Figure 3 It is a schematic diagram of the cross-sectional structure of another power device according to an embodiment of the present application.

[0019] The above drawings include the following reference numerals:

[0020] 10. substrate; 21. first epitaxial layer; 22. second epitaxial layer; 221. first sub-epitaxial portion; 222. second sub-epitaxial portion; 30. injection region; 40. gate structure; 41. gate oxide layer; 411. first region; 412. second region; 42. gate; 43. Schottky diode structure; 431. first doped layer; 432. second doped layer; 433. third doped layer; 50. conductive portion; 51. first conductive portion; 52. second conductive portion; 53. third conductive portion; 54. conductive layer; 70. insulating portion. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these products or devices.

[0024] As described in the background art, in the prior art, SiC MOS devices have a poor gate anti-static breakdown capability due to a thin gate oxide layer. In order to solve the above problem, the present application provides a power device.

[0025] According to one aspect of the present application, a power device is provided, such as Figures 1 to 3As shown, it includes a substrate 10 and a first epitaxial layer 21 and a second epitaxial layer 22 located on one side of the substrate 10, the first epitaxial layer 21 has a first doping type; the second epitaxial layer 22 is located on the side of the first epitaxial layer 21 away from the substrate 10, the second epitaxial layer 22 has a first sub-epitaxial portion 221 and a second sub-epitaxial portion 222 alternately arranged along a first direction A, the first sub-epitaxial portion 221 has a first doping type, the second sub-epitaxial portion 222 has a second doping type, the second epitaxial layer 22 has a first surface away from the substrate 10, and the first direction A is parallel to the first surface; the power device also includes: at least one implantation region 30, the implantation region 30 is located in the second sub-epitaxial portion 222, the surface of the implantation region 30 away from the substrate 10 is located in the first surface, the implantation region 30 has the first doping type, and a portion of the second sub-epitaxial portion 222 is provided between the implantation region 30 and the first sub-epitaxial portion 221; the gate structure 4 0, the gate structure 40 is located on the side of the second epitaxial layer 22 away from the substrate 10, the gate structure 40 includes a gate oxide layer 41, a gate 42 and a Schottky diode structure 43, the gate oxide layer 41 is respectively in contact with the first sub-epitaxial portion 221, a portion of the second sub-epitaxial portion 222 located between the injection region 30 and the first sub-epitaxial portion 221, and a portion of the injection region 30, the gate 42 and the Schottky diode structure 43 are respectively located on the side of the gate oxide layer 41 away from the substrate 10, wherein the Schottky diode structure 43 includes a plurality of doped layers stacked along the second direction B, any two adjacent doped layers have different doping types, the gate 42 is located on the side of the Schottky diode structure 43 in the first direction A, the doped layer in the plurality of doped layers that is in contact with the gate oxide layer 41 is the first doped layer 431, the gate 42 is in contact with the first doped layer 431, and the second direction B is the direction from the substrate 10 to the first epitaxial layer 21.

[0026] In the above-mentioned power device, the gate includes a Schottky diode structure, and a Schottky barrier diode (SBD) is integrated in the gate to protect the gate. Specifically, the Schottky diode structure includes multiple doping layers, and any two adjacent doping layers have different doping types, so that at least one PN junction is included in the Schottky diode structure. In the case of multiple PN junctions, multiple PN junctions are connected in series, and the gate is in direct contact with the Schottky diode structure. After the gate is applied with a voltage, a conduction circuit can be formed in the Schottky diode structure. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will turn on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, thereby improving the anti-static ability of the planar gate.

[0027] The breakdown voltage of the Schottky diode structure is greater than the gate turn-on voltage, but less than the gate oxide breakdown voltage. Under normal working conditions, the on and off of the trench power device will not be affected by the Schottky diode structure; if the gate voltage exceeds the safety range, the integrated Schottky diode structure will turn on, and the current will be released through the PN junction in the Schottky diode structure, protecting the gate oxide layer from breakdown.

[0028] The device adopts a new structure to realize the integration of SiC MOS gate and polysilicon PN junction. The gate is connected in series to the source metal through the integrated PN junction, which can not only ensure the normal operation of the device, but also in the case of high static electricity, the PN junction is turned on and the current is released through the source level, and static electricity will not break down the gate oxide.

[0029] The implantation region and the first sub-epitaxial portion have the same doping type, the implantation depth of the implantation region is 0.3 μm to 0.6 μm, and the doping concentration of the implantation region is greater than 1.0×10 20 / cm 3 A portion of the second sub-epitaxial portion is provided between the injection region and the first sub-epitaxial portion, and the injection region and the second sub-epitaxial portion have different doping types, that is, the injection region, the first sub-epitaxial portion, the second sub-epitaxial portion and the gate oxide structure constitute a MOS structure, wherein a channel is formed in the portion of the second sub-epitaxial portion between the injection region and the first sub-epitaxial portion by controlling the magnitude of the gate voltage, thereby controlling the flow of electrons (or holes) to realize the conduction of the device.

[0030] In some optional embodiments, the materials of the gate and the doping layer are doped polysilicon materials.

[0031] Specifically, the present application adopts a novel structure to realize the integration of SiC MOS gate and polysilicon PN junction. The gate and the integrated PN junction are connected in series, which can not only ensure the normal operation of the device, but also, in the case of high static electricity, the PN junction is turned on, and the current can be released through the source level, and static electricity will not break down the gate oxide. Among them, the conductivity of the polysilicon material can be regulated by process means such as doping, so that the doping concentration of the polysilicon material can be adjusted according to its application environment, and the doping concentration can be adjusted to meet the conductive performance of the gate. At the same time, the doping concentration of the doping layer of the Schottky diode structure can be adjusted to meet the voltage requirement of the PN junction, so as to achieve the voltage requirement of the Schottky diode structure.

[0032] In addition, the gate and doping layer are made of doped polysilicon material. Since polysilicon material has good chemical stability and thermal stability, using polysilicon as the material of the gate and Schottky diode structure can bring out the reliability of the performance of its structural stability and ensure the long-term stable operation of the device. Polysilicon material has lower leakage current and higher breakdown voltage, which can enable the device to withstand a higher voltage under reverse bias and improve the stability of the device. Polysilicon has good mechanical strength and toughness, which is conducive to maintaining the integrity and stability of the device during the device processing.

[0033] In some optional embodiments, such as Figures 1 to 3 As shown, the Schottky diode structure 43 is located on a side of the first sub-epitaxial portion 221 facing away from the substrate 10 , and the gate 42 is located on both sides of the Schottky diode structure 43 in the second direction B.

[0034] Specifically, in the above embodiment structure, when the gate voltage works normally, the two Schottky diode structures will not be turned on, and the gate plays the role of providing the gate voltage. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on to protect the gate oxide layer from being broken down. The Schottky diode structure is located on the side of the second sub-epitaxial portion away from the substrate, and the gate is located on both sides of the Schottky diode structure in the second direction, that is, the gate structure is located on the part of the second sub-epitaxial portion between the injection region and the first sub-epitaxial portion and above the injection region, so that the gate voltage can be applied, and the current flowing through the channel can be accurately controlled by adjusting the gate voltage. Moreover, the Schottky diode structure is located on the side of the second sub-epitaxial portion away from the substrate, which will not affect the implementation of the gate voltage, so that the Schottky diode structure is integrated into the gate structure without sacrificing the working performance of the power device, and the gate oxide layer is protected.

[0035] In some optional embodiments, the doping concentration of the first sub-epitaxial portion is greater than the doping concentration of the first epitaxial layer, that is, a doping concentration gradient is formed at the contact surface of the first sub-epitaxial portion and the first epitaxial layer, which can reduce the on-resistance of the device and optimize the switching characteristics of the device. In addition, the doping concentration gradient can balance the internal electric field and temperature distribution of the power device, reduce thermal stress and current crowding effects, and improve the reliability and service life of the device.

[0036] In some optional embodiments, the first doping layer and the gate have the same doping type.

[0037] Specifically, the first doping layer has the same doping as the gate, which can reduce the conduction voltage between the gate and the Schottky diode structure, and help the gate voltage to be small when it exceeds the safety range, and the Schottky diode structure to be turned on. At the same time, the first doping layer is in contact with the gate. When the gate voltage is within the safety range, the PN junction in the Schottky diode structure will not be turned on, and the current can flow normally between the gate and the first doping layer. At this time, the first doping layer can also play the role of the gate, that is, the width of the gate in the first direction is increased, which helps to disperse the electric field strength, reduce the concentration of the electric field at the edge of the gate, and increase the breakdown voltage of the gate oxide layer. In addition, the gate width is increased, the channel width is increased, and the on-resistance is reduced, which is conducive to reducing the power consumption of the device. At the same time, the wide gate can better dissipate heat, reduce the device temperature, and maintain the stability and reliability of the device. When the gate voltage exceeds the safety range, the first doping layer and other doping layers provide the Schottky diode structure with a PN junction breakdown voltage to protect the gate oxide layer from breakdown.

[0038] In some optional implementations, such as Figure 2 As shown, the doped layer in the multi-layer doped layer that is in contact with the first doped layer 431 is the second doped layer 432. In the second direction B, the first doped layer 431 has a first thickness, the second doped layer 432 has a second thickness, the gate 42 has a third thickness, and the sum of the first thickness and the second thickness is greater than the third thickness.

[0039] Specifically, the thickness of the gate is less than the sum of the thicknesses of the first doping layer and the second doping layer, that is, the gate can contact the second doping layer, that is, the gate has a thicker thickness. A thicker gate can provide a stronger electric field, thereby more effectively controlling the carriers in the channel, reducing the channel resistance, and improving the current driving capability of the device. The stronger channel control capability helps to improve the switching speed and flat rate effect of the device. In addition, the thick gate can better shield the electric field interference from under the gate. At the same time, the thick gate can better withstand high temperature environments, reduce performance fluctuations caused by heat generated by current passing through, and improve the stability and reliability of the device. In addition, as the thickness of the gate increases, the gate leakage current will decrease, where gate leakage refers to the current passing through the gate oxide layer between the gate and the channel. The reduction of gate leakage improves the energy efficiency and long-term stability of the device.

[0040] In some optional implementations, such as Figures 1 to 3 As shown, the Schottky diode structure 43 also includes a second doping layer 432 and a third doping layer 433 located on the side of the first doping layer 431 away from the substrate 10 and stacked along the second direction B. The first doping layer 431 and the third doping layer 433 have N-type doping, and the second doping layer 432 has P-type doping.

[0041] Specifically, the first doping layer is N-type, the second doping layer is P-type, and the third doping layer is N-type. The Schottky diode structure constitutes an NPN-type doping structure. The NPN is less affected by temperature and has high temperature stability, so that it maintains good performance in high temperature environments. Since the mobility of electrons is much higher than the mobility of holes, the NPN structure can achieve rapid current changes during the PN junction switching process, so that when the gate voltage exceeds the safety range, the Schottky diode structure can be turned on in time to achieve better protection for the gate oxide layer. In addition, the NPN structure can withstand higher power density, so that it can maintain stable performance in high-power applications.

[0042] In the above embodiment, the doping concentration of the first doping layer is lower than the doping concentration of the remaining doping layers.

[0043] Specifically, the first doped layer contacts the gate oxide layer, and the doping concentration of the first doped layer is less than that of the remaining doped layers, which can prevent impurities in the first doped layer from diffusing into the gate oxide layer and affecting the performance of the gate oxide layer, thereby improving the stability and reliability of the device.

[0044] For example, the doping concentration of the first doping layer is 1.0×10 17 / cm 3 ~1.0×10 19 / cm 3 The doping concentration of the second doping layer and the third doping layer is 1.0×10 19 / cm 3 ~1.0×10 21 / cm 3 , this application does not make specific limitations.

[0045] In some optional embodiments, such as Figure 3 As shown, the gate oxide layer 41 includes a first region 411 and a second region 412. The first region 411 is at least located between the Schottky diode structure 43 and the second epitaxial layer 22, and the remaining gate oxide layer is the second region 412. The first region 411 has a fourth thickness in the second direction B, and the second region 412 has a fifth thickness in the second direction, and the fourth thickness is greater than the fifth thickness.

[0046] Specifically, a series PN junction structure is formed in the Schottky diode structure. During the device startup process, the Schottky diode structure will affect the performance of the device during the switching process. By thickening the gate oxide layer between the Schottky diode structure and the second epitaxial layer, the series PN junction structure is prevented from affecting the device dynamics.

[0047] The thickness of the first region is 50 nm to 300 nm, which is not specifically limited in this application.

[0048] In some optional embodiments, a projection of the first region in the second direction is located in a surface of the second sub-epitaxial portion facing away from the substrate.

[0049] Specifically, the first region of the gate oxide layer has a thicker thickness. Since the electric field strength will weaken as the thickness of the gate oxide layer increases, if the thickened first region covers the channel, the gate's control over the channel will be weakened. Moreover, if the thickness of the gate oxide layer increases, the electric field change will take longer to pass through the thicker gate oxide layer, so the thicker gate oxide will increase the switching time of the gate. Therefore, the projection of the first region in the second direction should be located on the surface of the second sub-epitaxial portion away from the substrate to avoid the thickened gate oxide layer covering the channel, thereby increasing the gate's control over the channel and improving the switching speed.

[0050] In the above embodiment, the first doped layer has a first thickness in the second direction, the gate has a third thickness in the second direction, and the first thickness is less than the third thickness.

[0051] Specifically, the Schottky diode structure integrated in the gate structure has a multi-layer structure, and at the same time, there is a thicker gate oxide layer between the Schottky diode structure and the second epitaxial layer, which will affect the overall thickness of the device. Therefore, reducing the thickness of the first doped layer can reduce the thickness of the chip. During the device integration process, the chip thickness is reduced, which improves the integration of the device.

[0052] In some optional embodiments, the first sub-epitaxial portion has a sixth thickness in the second direction, the second sub-epitaxial portion has a seventh thickness in the second direction, and the sixth thickness is greater than or equal to the seventh thickness.

[0053] Specifically, the thickness of the first sub-epitaxial portion is greater than or equal to the thickness of the second sub-epitaxial portion. Without affecting the breakdown voltage of the device, the thickness of the first epitaxial layer can be reduced, the on-resistance of the device can be reduced, and the speed of the device can be increased.

[0054] The seventh thickness of the second sub-epitaxial portion is less than 2 μm. The specific thickness of the second sub-epitaxial portion is not limited in this application. The doping concentration of the second sub-epitaxial portion is 1.0×10 17 / cm 3 ~1.0×10 19 / cm 3 , this application does not make specific limitations.

[0055] In some optional embodiments, such as Figures 1 to 3 As shown, the power device further includes: a plurality of conductive parts 50 , the conductive parts 50 are respectively in contact with the implantation region 30 , the Schottky diode structure 43 and the gate 42 , and the plurality of conductive parts 50 are arranged at intervals.

[0056] Specifically, the conductive part includes a first conductive part 51, a second conductive part 52 and a third conductive part 53, wherein the first conductive part 51 contacts the Schottky diode structure 43, the second conductive part 52 contacts the gate 42, and the third conductive part 53 contacts the injection region 30. When the gate voltage exceeds the safety range, the integrated Schottky diode structure 43 is turned on, and the current flows into the Schottky diode structure 43 through the gate 42 and the first doping layer 431, and flows out through the first conductive part 51, so that the current is released; the second conductive part 52 contacts the gate 42 to provide a gate voltage for the device; the third conductive part 53 contacts the injection region 30, and the third conductive part 53 acts as a source to provide current for the MOS structure.

[0057] In some optional embodiments, such as Figures 1 to 3 As shown, the power device further includes: a conductive layer 54, which is located on a side of the substrate 10 away from the first epitaxial layer 21 and can serve as a drain electrode of the power device.

[0058] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to any one of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals or alloy materials. The conductive part includes a layer of conductive material or multiple layers of conductive materials. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0059] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, wherein the thickness of each layer is 0.1μm~0.2μm / 0.1μm~0.2μm / 0.1μm~0.2μm / 3μm~6μm, respectively, the first conductive part contacts the first doped layer to form an ohmic contact, the second conductive part contacts the gate to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0060] In some optional embodiments, such as Figures 1 to 3 As shown, the power device further includes: an insulating portion 70, which is located between the conductive layers. The insulating portion 70 serves to isolate the plurality of conductive portions 50, thereby preventing the conductive portions 50 from being short-circuited, so as to form a protection circuit.

[0061] Specifically, the material of the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0062] The insulating part includes a layer of material or multiple layers of material, and the thickness of the insulating part is 0.3 μm to 2 μm, which is not specifically limited in this application.

[0063] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such product or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the product or device including the elements.

[0064] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A power device, comprising a substrate and a first epitaxial layer and a second epitaxial layer located on one side of the substrate, wherein the first epitaxial layer has a first doping type, the second epitaxial layer is located on a side of the first epitaxial layer away from the substrate, the second epitaxial layer has a first sub-epitaxial portion and a second sub-epitaxial portion alternately arranged along a first direction, the first sub-epitaxial portion has the first doping type, the second sub-epitaxial portion has a second doping type, the second epitaxial layer has a first surface away from the substrate, the first direction is parallel to the first surface, characterized in that: The power device further comprises: at least one implantation region, the implantation region being located in the second sub-epitaxial portion, the surface of the implantation region facing away from the substrate being located in the first surface, the implantation region having the first doping type, and a portion of the second sub-epitaxial portion being between the implantation region and the first sub-epitaxial portion; A gate structure, wherein the gate structure is located on a side of the second epitaxial layer away from the substrate, the gate structure includes a gate oxide layer, a gate and a Schottky diode structure, the gate oxide layer is respectively in contact with the first sub-epitaxial portion, a portion of the second sub-epitaxial portion located between the injection region and the first sub-epitaxial portion, and a portion of the injection region, the gate and the Schottky diode structure are respectively located on a side of the gate oxide layer away from the substrate, wherein the Schottky diode structure includes a plurality of doped layers stacked along a second direction, any two adjacent doped layers have different doping types, the gate is located on the side of the Schottky diode structure in the first direction, the doped layer in the plurality of doped layers that is in contact with the gate oxide layer is a first doped layer, the gate is in contact with the first doped layer, and the second direction is a direction from the substrate to the first epitaxial layer.

2. The power device according to claim 1, characterized in that: The Schottky diode structure is located on a side of the first sub-epitaxial portion away from the substrate, and the gate is located on both sides of the Schottky diode structure in the second direction.

3. The power device according to claim 2, characterized in that: The first doping layer has the same doping type as the gate.

4. The power device according to claim 3, characterized in that: The doped layer in the multiple doped layers that is in contact with the first doped layer is a second doped layer. In the second direction, the first doped layer has a first thickness, the second doped layer has a second thickness, the gate has a third thickness, and the sum of the first thickness and the second thickness is greater than the third thickness.

5. The power device according to claim 1, characterized in that: The Schottky diode structure also includes a second doping layer and a third doping layer located on a side of the first doping layer away from the substrate and stacked along the second direction, the first doping layer and the third doping layer have N-type doping, and the second doping layer has P-type doping.

6. The power device according to claim 1, characterized in that: The gate oxide layer includes a first region and a second region, the first region is at least located between the Schottky diode structure and the second epitaxial layer, and the rest of the gate oxide layer is the second region, the first region has a fourth thickness in the second direction, the second region has a fifth thickness in the second direction, and the fourth thickness is greater than the fifth thickness.

7. The power device according to claim 6, characterized in that: A projection of the first region in the second direction is located in a surface of the second sub-epitaxial portion facing away from the substrate.

8. The power device according to claim 6, characterized in that: Also includes: The first doping layer has a first thickness in the second direction, the gate has a third thickness in the second direction, and the first thickness is smaller than the third thickness.

9. The power device according to claim 1, characterized in that: The first sub-epitaxial portion has a sixth thickness in the second direction, the second sub-epitaxial portion has a seventh thickness in the second direction, and the sixth thickness is greater than or equal to the seventh thickness.

10. The power device according to claim 1, characterized in that: Also includes: A plurality of conductive parts are provided, wherein the conductive parts are respectively in contact with the injection region, the Schottky diode structure and the gate, and the plurality of conductive parts are arranged at intervals.

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