LDO (Low Dropout Regulator) integrated with novel buffer circuit

Abstract

The utility model discloses a low dropout regulator (LDO) integrated with a novel buffer circuit, which belongs to the technical field of low dropout regulators, and comprises a bias circuit, the bias circuit is connected with an error amplifier component and a switch tube component, the error amplifier component and the switch tube component are both connected with the novel buffer circuit, the novel buffer circuit is connected with a feedback resistor component, and the feedback resistor component is connected with the bias circuit. The error amplifier assembly is connected with the switching tube assembly. Compared with a traditional LDO circuit, the LDO circuit integrates a novel buffer circuit, and meanwhile low-current starting of the LDO and enhancement of the power supply rejection ratio are achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of low voltage dropout regulators, in particular to an LDO with an integrated novel buffer circuit. Background Art

[0002] Low-dropout linear regulator is a power supply analog circuit module in the chip; at the same time, it is also an important branch of power management. LDO is generally used as a lower-level module of a switching power supply or a charge pump, responsible for reducing the voltage, eliminating ripples, filtering noise, etc. in the switching power supply or charge pump. Finally, the output voltage processed by LDO is used as the ideal voltage source inside the chip. When the traditional LDO architecture is actually powered on, there is a startup current of several amperes, which is easy to break down the chip. Therefore, the traditional LDO architecture needs to design an additional slow-start module to achieve safe startup.

[0003] For example, Chinese patent CN209327893U discloses a low voltage dropout regulator with a soft start circuit, the low voltage dropout regulator comprising: a differential amplifier; a channel transistor, the channel transistor is coupled to the output portion of the differential amplifier, wherein the channel transistor is configured to provide the output voltage of the LDO regulator; and a soft start circuit, the soft start circuit is coupled to the differential amplifier.

[0004] However, the technology has the following problems: the slow start module occupies too much chip area and has a single function, and cannot achieve low current startup, high power supply rejection ratio, and slew rate enhancement.

[0005] Based on this, the utility model designs an LDO integrating a novel buffer circuit to solve the above problems. Utility Model Content

[0006] In view of the above-mentioned shortcomings of the prior art, the utility model provides an LDO integrating a novel buffer circuit.

[0007] In order to achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] A LDO with an integrated novel buffer circuit comprises a bias circuit, wherein the bias circuit is connected to an error amplifier component and a switch tube component, wherein the error amplifier component and the switch tube component are both connected to the novel buffer circuit, wherein the novel buffer circuit is connected to a feedback resistor component, and the error amplifier component and the switch tube component are connected.

[0009] Furthermore, the bias circuit includes P1, P2, P3, P4, P5, P6, P8, P9, N1, N2, N4, N5, N7, R0, R1 and IDC, the drain of P1 is electrically connected to the source of P2, the drain of P2 is electrically connected to the gates of R0 and P1, the gate of P1, the drain of P2, the gate of P3, the gate of P5 and the gate of P8 are short-circuited, R0 is electrically connected to the drain of N2, the gate of N2 is electrically connected to the gate of N1, the gate of N2, the gate of N1 and the drain of N1 are all connected to the switch tube component, the drain of N1, the gate of N1 and the gate of N2 are short-circuited, forming a first circuit. Current mirror circuit; the drain of P3 is electrically connected to the source of P4, the drain of P4 is electrically connected to the drain of N4 through R1, the source of N4 is electrically connected to the drain of N5, the gate of N5 is electrically connected to the drain of N4, the gate of N4 is connected to the switch tube component, the IDC is connected to the switch tube component, the drain of P5 is electrically connected to the source of P6, the drain of P6 is electrically connected to the drain of N7, the gate of N7 is connected to the switch tube component, the drain of P8 is electrically connected to the source of P9, the drain of P9 is connected to the error amplifier component, the gate of P2, the drain of N2, the gate of P4, the gate of P6, and the gate of P9 are short-circuited, and the IDC is a connector.

[0010] Furthermore, the error amplifier component includes P11, P12, P13, P15, P16, P17, N10, N11, N9 and N12, the source of P11 and the source of P12 are electrically connected to the drain of P9, the drain of P11 is electrically connected to the source of N11 and the drain of N12, the drain of N11 is connected to the novel buffer circuit, the drain of P12 is electrically connected to the source of N10 and the drain of N9, the drain of N10 is electrically connected to P The drain of N17, the gate of P13, and the gate of P15 are all electrically connected, the gate of P13 and the gate of P15 are all connected to the switch tube component, the drain of P15 is electrically connected to the source of P16, the drain of P16 is electrically connected to the drain of N11, the drain of N7, the gate of N7, the gate of N12, and the gate of N9 are short-circuited to form a second current mirror circuit, the gate of P16 is electrically connected to the gate of P17, and the gate of P11 is electrically connected to VREF.

[0011] Furthermore, the novel buffer circuit includes P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, N13, N14, N15, N16, N17, N18 and N19, the drain of P19 is electrically connected to the source of P20, the drain of P20, the source of P21, the gate of P22, the gate of P23 and the gate of P24 are short-circuited, and the drain of P22 is electrically connected to the source of P20. The drain of P25, the drain of P26, and the gate of P28 are all electrically connected to the source of P21, the drain of P23 is electrically connected to the source of P26, the drain of P21 is electrically connected to the drain of N13 and the gate of N19, the gate of P21 is electrically connected to the drain of P16 and the drain of N11, the gate of N13 is electrically connected to the gate of N14, the gate of N15, the drain of N15, and the drain of N17, and the source of N15 is electrically connected. The gate of N17 is electrically connected to the drain of N14, the source of N17 is electrically connected to the drain of N18, the drain of P28 is connected to the feedback resistance component, the drain of P28 is connected to the load capacitance equivalent parasitic resistance Resr, the load capacitance equivalent parasitic resistance Resr is connected to the load capacitance CL, VOUT, the drain of P25, the drain of P26, the drain of N15, and the drain of N17 are all connected to the switch tube component, the gate of N17 is electrically connected to the gate of N10, the gate of N11, the gate of N4, and the drain of N6, the gate of N18 is electrically connected to the gate of N5 and R1, the gate of P1, the drain of P2, the gate of P3, the gate of P5, the gate of P8, and the gate of P19 are short-circuited to form a third current mirror circuit, the gate of N1, the drain of P4, the gate of N10, the gate of N11, and the gate of N17 are short-circuited to form a fourth current mirror circuit.

[0012] Furthermore, the feedback resistor component includes R2 and R3, the drain of P28 is electrically connected to R2, R2 and R3 are electrically connected, VFB is electrically connected between R2 and R3, and the gate of P12 is electrically connected to VFB.

[0013] Furthermore, the switch tube assembly includes P0, P7, P10, P14, P18, P27, P29, N0, N3, N6, N8 and N16, the source of P0 is electrically connected to IDC, the drain of P0 is electrically connected to the drain of N1, the drain of NO is electrically connected to the gate of N1, the drain of N3 is electrically connected to the gate of N5, the drain of N6 is electrically connected to the gate of N4, the drain of N8, the drain of N7, the gate of N7, the gate of N9, and the gate of N12 are short-circuited, the drain of N16 is electrically connected to the gate of N13, the gate of N14, the gate of N15, the drain of N15, the drain of N17, and the drain of P27, and the source of P27 is electrically connected to the source of P21, The source of P22, the drain of P25, the drain of P26, and the gate of P28 are all electrically connected; the drain of P29, the gate of P24, the gate of P23, the gate of P22, the drain of P20, and the source of P21 are short-circuited; the drain of P18 is electrically connected to the gate of P21; the drain of P14 is electrically connected to the gate of P13 and the gate of P15; the drain of P10 is short-circuited to the gate of P3 and the gate of P7; the drain of P7 is electrically connected to the gate of P8; the gate of P0, the gate of N0, the gate of N3, the gate of N6, the gate of N8, the gate of N16, and the gate of P27 are all electrically connected; the gate of P7, the gate of P10, the gate of P14, and the gate of P29 are all electrically connected.

[0014] Furthermore, the gate of P2, the drain of N2, the gate of P4, the gate of P6, the gate of P9, the gate of P17, the gate of P18, and the gate of P20 are short-circuited to form a fifth current mirror circuit.

[0015] Furthermore, the gate of N5, the drain of N1, and the gate of N18 are short-circuited to form a sixth current mirror circuit.

[0016] Furthermore, the IDC, the source of P1, the source of P3, the source of P5, the source of P7, the source of P8, the source of P10, the source of P13, the source of P14, the source of P15, the source of P19, the source of P22, the source of P23, the source of P24, the source of P29, and the source of P28 are all electrically connected to VDD.

[0017] Furthermore, the source of N0, the source of N1, the source of N2, the source of N3, the source of N5, the source of N6, the source of N7, the source of N8, the source of N9, the source of N12, the source of N13, the source of N14, the source of N16, the source of N18, the source of N19, the source of N2, R3, and the load capacitor CL are all grounded.

[0018] The utility model has the following technical effects:

[0019] 1. When the utility model is in the initial state, when the power supply and the enable signal EN are at a low level, the gate of the switch tube P0 and the gate of P27 are at a high level; the gate of P7, the gate of P10, the gate of P14, the gate of P18, and the gate of P29 are all at a low level; the gate of N0, the gate of N3, the gate of N6, the gate of N8, and the gate of N16 are at a high level; the switch tube is working, and the LDO output terminal is at zero potential to the ground.

[0020] 2. When the utility model is in the on state, when the power supply and the enable signal jump from low level to high level, the gate of the switch tube P0 and the gate of P27 are low level; the gate of P7, the gate of P10, the gate of P14, the gate of P18, and the gate of P29 are all high level; the gate of N0, the gate of N3, the gate of N6, the gate of N8, and the gate of N16 are low level, the output end of LDO is zero potential to ground, and the output voltage rises slowly; at this time, the current in IDC is allowed to be transferred to LDO through the P0 and N1 branches, and the bias circuit enters the working point; the bias circuit gives voltage biases to the error amplifier VB0, VB1, etc., and the error amplifier enters the working point; the error amplifier and the bias circuit give voltage bias to the new buffer circuit, and the new buffer circuit enters the working point; the new buffer circuit starts to work and gives a voltage bias to the gate of the power tube P16, and the power tube enters the working point; the power tube starts to work and generates current flowing into the feedback resistors R2 and R3, and outputs a stable 4.6V voltage.

[0021] 3. Compared with the traditional LDO circuit, the utility model integrates a new buffer circuit, and at the same time, realizes the enhancement of the low current startup and power supply rejection ratio of the LDO. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a circuit connection diagram of an LDO with an integrated novel buffer circuit of the utility model;

[0024] Figure 2 This is a connection block diagram of an LDO integrated with a novel buffer circuit of the utility model;

[0025] Figure 3 A circuit connection diagram of the bias circuit of the utility model;

[0026] Figure 4It is a circuit connection diagram of the error amplifier component of the utility model;

[0027] Figure 5 It is a circuit connection diagram of the novel buffer circuit and feedback resistor assembly of the utility model;

[0028] Figure 6 This is a circuit connection diagram of the switch tube assembly of the utility model.

[0029] Figure 7 It is the response simulation curve diagram under slow start transient state;

[0030] Figure 8 It is a load modulation simulation curve diagram;

[0031] Fig. 9 It is the transient response simulation curve diagram;

[0032] Fig.10 It is the amplitude-frequency characteristic simulation curve diagram;

[0033] Fig.11 It is a simulation curve diagram of the input voltage range;

[0034] Fig.12 This is the load modulation simulation curve.

[0035] The numbers in the figure represent:

[0036] 1. Bias circuit; 2. Error amplifier component; 3. New buffer circuit; 4. Feedback resistor component; 5. Switch tube component. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0038] The utility model is further described below in conjunction with embodiments.

[0039] Example 1

[0040] Please refer to the instruction manual Figure 1-12, an LDO with an integrated novel buffer circuit, including a bias circuit 1, wherein the bias circuit 1 is connected to an error amplifier component 2 and a switch tube component 5, the error amplifier component 2 and the switch tube component 5 are both connected to a novel buffer circuit 3, the novel buffer circuit 3 is connected to a feedback resistor component 4, and the error amplifier component 2 and the switch tube component 5 are connected.

[0041] Compared with the traditional LDO circuit, the error amplifier component 2 and the bias circuit 1 of the utility model give a voltage bias to the new buffer circuit 3. When the new buffer circuit 3 starts to work, the power tube starts to work and generates current. The current flows into the feedback resistor component 4 and outputs a stable voltage. At the same time, the low current startup and power supply rejection ratio of the LDO are enhanced.

[0042] Example 2

[0043] like Figure 1-12 As shown, as a preferred embodiment of the utility model, the bias circuit 1 includes P1, P2, P3, P4, P5, P6, P8, P9, N1, N2, N4, N5, N7, R0, R1 and IDC, the drain of P1 is electrically connected to the source of P2, the drain of P2 is electrically connected to the gates of R0 and P1, the gate of P1, the drain of P2, the gate of P3, the gate of P5 and the gate of P8 are short-circuited, R0 is electrically connected to the drain of N2, the gate of N2 is electrically connected to the gate of N1, the gate of N2, the gate of N1 and the drain of N1 are all connected to the switch tube component 5, the drain of N1, the gate of N1 and the gate of N2 are short-circuited, A first current mirror circuit is formed; the drain of P3 is electrically connected to the source of P4, the drain of P4 is electrically connected to the drain of N4 through R1, the source of N4 is electrically connected to the drain of N5, the gate of N5 is electrically connected to the drain of N4, the gate of N4 is connected to the switch tube component 5, the IDC is connected to the switch tube component 5, the drain of P5 is electrically connected to the source of P6, the drain of P6 is electrically connected to the drain of N7, the gate of N7 is connected to the switch tube component 5, the drain of P8 is electrically connected to the source of P9, the drain of P9 is connected to the error amplifier component 2, the gate of P2, the drain of N2, the gate of P4, the gate of P6, and the gate of P9 are short-circuited, and the IDC is a connector.

[0044] The error amplifier component 2 includes P11, P12, P13, P15, P16, P17, N10, N11, N9 and N12. The source of P11 and the source of P12 are electrically connected to the drain of P9. The drain of P11 is electrically connected to the source of N11 and the drain of N12. The drain of N11 is connected to the novel buffer circuit 3. The drain of P12 is electrically connected to the source of N10 and the drain of N9. The drain of N10 is electrically connected to P17. The drain of P13, the gate of P15 are all electrically connected, the gate of P13 and the gate of P15 are all connected to the switch tube component 5, the drain of P15 is electrically connected to the source of P16, the drain of P16 is electrically connected to the drain of N11, the drain of N7, the gate of N7, the gate of N12, and the gate of N9 are short-circuited to form a second current mirror circuit, the gate of P16 is electrically connected to the gate of P17, and the gate of P11 is electrically connected to VREF.

[0045] The novel buffer circuit 3 includes P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, N13, N14, N15, N16, N17, N18 and N19, the drain of P19 is electrically connected to the source of P20, the drain of P20, the source of P21, the gate of P22, the gate of P23 and the gate of P24 are short-circuited, and the drain of P22, the source of P21, the gate of P22, the gate of P23 and the gate of P24 are short-circuited. The drain of P5, the drain of P26, and the gate of P28 are all electrically connected to the source of P21, the drain of P23 is electrically connected to the source of P26, the drain of P21 is electrically connected to the drain of N13 and the gate of N19, the gate of P21 is electrically connected to the drain of P16 and the drain of N11, the gate of N13 is electrically connected to the gate of N14, the gate of N15, the drain of N15, and the drain of N17, the source of N15 is electrically connected to the drain of N19, and the gate of N16 is electrically connected to the drain of N17. 4, the source of N17 is electrically connected to the drain of N18, the drain of P28 is connected to the feedback resistor component 4, the drain of P28 is connected to the load capacitor equivalent parasitic resistance Resr, the load capacitor equivalent parasitic resistance Resr is connected to the load capacitor CL, VOUT, the drain of P25, the drain of P26, the drain of N15, and the drain of N17 are all connected to the switch tube component 5, the gate of N17 is electrically connected to the gate of N10, the gate of N11, the gate of N4, and the drain of N6, the gate of N18 is electrically connected to the gate of N5 and R1, the gate of P1, the drain of P2, the gate of P3, the gate of P5, the gate of P8, and the gate of P19 are short-circuited to form a third current mirror circuit, and the gate of N1, the drain of P4, the gate of N10, the gate of N11, and the gate of N17 are short-circuited to form a fourth current mirror circuit.

[0046] The feedback resistor component 4 includes R2 and R3, the drain of P28 is electrically connected to R2, R2 and R3 are electrically connected, VFB is electrically connected between R2 and R3, and the gate of P12 is electrically connected to VFB.

[0047] The switch tube assembly 5 includes P0, P7, P10, P14, P18, P27, P29, N0, N3, N6, N8 and N16, the source of P0 is electrically connected to IDC, the drain of P0 is electrically connected to the drain of N1, the drain of N0 is electrically connected to the gate of N1, the drain of N3 is electrically connected to the gate of N5, the drain of N6 is electrically connected to the gate of N4, the drain of N8, the drain of N7, the gate of N7, the gate of N9 and the gate of N12 are short-circuited, the drain of N16 is electrically connected to the gate of N13, the gate of N14, the gate of N15, the drain of N15, the drain of N17 and the drain of P27, the source of P27 is electrically connected to the source of P21, the gate of P22 The source of P25, the drain of P26, and the gate of P28 are all electrically connected, the drain of P29, the gate of P24, the gate of P23, the gate of P22, the drain of P20, and the source of P21 are short-circuited, the drain of P18 is electrically connected to the gate of P21, the drain of P14 is electrically connected to the gate of P13 and the gate of P15, the drain of P10 is short-circuited to the gate of P3 and the gate of P7, the drain of P7 is electrically connected to the gate of P8, the gate of P0, the gate of N0, the gate of N3, the gate of N6, the gate of N8, the gate of N16, and the gate of P27 are all electrically connected, and the gate of P7, the gate of P10, the gate of P14, and the gate of P29 are all electrically connected.

[0048] When in the initial state, when the power supply and enable signal are at a low level, the gate of the switch tube P0 and the gate of P27 are at a high level; the gate of P7, the gate of P10, the gate of P14, the gate of P18, and the gate of P29 are all at a low level; the gate of N0, the gate of N3, the gate of N6, the gate of N8, and the gate of N16 are at a high level; the switch tube is working, and the LDO output terminal is at zero potential to the ground.

[0049] When in the on state, when the power supply and enable signal jump from low level to high level, the gate of the switch tube P0 and the gate of P27 are low level; the gate of P7, the gate of P10, the gate of P14, the gate of P18, and the gate of P29 are all high level; the gate of N0, the gate of N3, the gate of N6, the gate of N8, and the gate of N16 are low level; the output end of LDO is at zero potential to ground, and the output voltage rises slowly; at this time, the current in IDC is allowed to be transferred to LDO through the P0 and N1 branches, and the bias circuit enters the working point; the bias circuit gives voltage biases to the error amplifier VB0, VB1, etc., and the error amplifier enters the working point; the error amplifier and the bias circuit give voltage bias to the new buffer circuit, and the new buffer circuit enters the working point; the new buffer circuit starts to work and gives the gate voltage bias of the power tube P16, and the power tube enters the working point; the power tube starts to work and generates current flowing into the feedback resistors R2 and R3, and outputs a stable 4.6V voltage.

[0050] When low current starts, when the power supply and enable signal jump from low level to high level, N17 and N18 obtain VB0 and VB1 voltage bias given by the bias circuit; the gate of P27 is low level; the gate of P22 and the drain of P22 are short-circuited to form an equivalent diode; the gate of N14, the gate of N15, and the drain of N15 are short-circuited to form an equivalent diode; finally, the VDD, P22, P27, N14, N15, N17, N18, and GND branches are turned on, so the power tube The gate voltage of P28 is locked by the VDD, P22, P27, N14, N15, N17, N18, and GND branches; finally, when the LDO is just powered on, the initial gate voltage of the power tube P28 is given through the VDD, P22, P27, N14, N15, N17, N18, and GND branches in the new buffer circuit; secondly, the slow start time can be selected by turning on or off P25 and P26 in the new buffer circuit, thereby realizing low-current startup of the LDO.

[0051] When improving the power supply rejection ratio, assuming that the power supply voltage has positive phase noise causing the power supply voltage to climb upward, then the gate voltage of P28, the gate voltage of P28, the gate voltage of N14, the gate voltage of N15, and the drain voltage of N15 all rise; the gate voltage of N14, the gate voltage of N15, and the drain of N15 rise, causing the gate voltage of N13 to rise; the N13, P19, P20, and P21 branches can be approximated as a common source amplifier with N13 as the input tube, then the source voltage of P21 decreases; the source voltage of P21 serves as the gate voltage of the power tube P28; finally, the positive phase noise of the power supply voltage is offset by the negative feedback formed by N13, N14, N15, P19, P20, P21, and P27 in the new buffer, thereby enhancing the LDO power supply rejection ratio.

[0052] When the slew rate is enhanced, when the output current of the LDO switches from light load to heavy load, due to the large size of the power tube and the presence of pF-level parasitic capacitance, the gate bias of the power tube cannot respond to the change of the output current in time, so an undershoot voltage will appear at the output of the LDO; when the undershoot voltage occurs, VFB also undershoots and is transmitted to the gate of the positive input terminal P12 of the error amplifier, so the error amplifier output is reduced and serves as the gate voltage bias of P21 in the buffer circuit. At this time, the P21, N13, and GND branches are approximately P21 is The common-source amplifier circuit of the input tube, so the drain voltage of P21 is raised; the drain voltage of P21 is used as the gate voltage bias of N19, so N19 generates output current to lower the gate voltage of power tube P28; the gate voltage of power tube P28 is pulled down, so that power tube P28 generates more output current to adapt to heavy load; finally, when the LDO has an undershoot voltage, P19, P20, P21, N13, and N19 in the buffer circuit provide additional slew rate enhancement for the gate voltage of power tube P28, thereby weakening the undershoot voltage of LDO.

[0053] Example 3

[0054] like Figure 1-12 As shown, as a preferred embodiment of the utility model, the gate of P2, the drain of N2, the gate of P4, the gate of P6, the gate of P9, the gate of P17, the gate of P18, and the gate of P20 are short-circuited to form a fifth current mirror circuit.

[0055] The gate of N5, the drain of N1, and the gate of N18 are short-circuited to form a sixth current mirror circuit.

[0056] The IDC, the source of P1, the source of P3, the source of P5, the source of P7, the source of P8, the source of P10, the source of P13, the source of P14, the source of P15, the source of P19, the source of P22, the source of P23, the source of P24, the source of P29, and the source of P28 are all electrically connected to VDD.

[0057] The source of N0, the source of N1, the source of N2, the source of N3, the source of N5, the source of N6, the source of N7, the source of N8, the source of N9, the source of N12, the source of N13, the source of N14, the source of N16, the source of N18, the source of N19, the source of N2, R3, and the load capacitor CL are all grounded.

[0058] like Figure 7The figure shows the simulation curve of the slow start transient response of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. The solid line 1 is the output voltage VOUT0 of LDO, the dotted line 2 is the output voltage VOUT1 of LDO, and the dotted horizontal line 3 is the output voltage VOUT2 of LDO. According to the simulation waveform, when the soft start time is 139uS, LDO successfully outputs an output voltage VOUT0 of 4.6V, the startup current IOUT0 is up to 396mA, and the compensation current I C0 is 987uA; when the soft start time is 112uS, LDO successfully outputs an output voltage VOUT1 of 4.6V, the startup current IOUT1 is up to 495mA, and the compensation current I C1 is 1.27mA; when the soft start time is 87uS, LDO successfully outputs an output voltage VOUT2 of 4.6V, the startup current IOUT2 ​​is up to 641mA, and the compensation current I C2 is 1.68mA.

[0059] like Figure 8 The figure shows the load modulation simulation curve of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. The curve in the figure is the output voltage waveform of the low-dropout linear regulator. According to the simulation waveform, when the output current is 0mA, the output voltage is 4.604677V; when the output current is 450mA, the output voltage is 4.597709V. Therefore, when the output current of the low-dropout linear regulator is within 450mA, the output voltage fluctuation range is only 6.96mV.

[0060] like Fig. 9 The figure shows the transient response simulation curve of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. The solid line 4 is the output voltage waveform of the low-voltage difference linear regulator, the dotted line 5 is the output current change waveform of the low-voltage difference linear regulator, and the dotted horizontal line 6 is the N19 output current ICC change waveform. According to the simulation waveform, when the output current jumps from 0mA to 200mA within 1us, the lowest undershoot voltage of the output voltage is 4.595191V; when the output current jumps from 200mA to 0mA within 1us, the lowest overshoot voltage of the output voltage is 4.607681V; when the LDO overshoots, the N19 output current ICC is 22.98uA; during the output current jump process, the lowest output voltage of the LDO is 4.595191V, the highest output voltage is 4.607681V, and the standard output voltage is 4.601V.

[0061] like Fig.10The figure shows the simulation curve of the amplitude-frequency characteristic of LDO. The simulation settings are tt process angle, 25°C, power supply voltage of 5V, and output current range of 0mA. The solid line 7 in the figure above is the loop gain, and the dotted line 8 is the phase margin. According to the simulation waveform, the low-frequency loop gain of the bandgap reference is 78.67dB, the unit gain bandwidth is 10.51KHz, and the phase margin is 87°.

[0062] like Fig.11 Shown is a simulation curve of the power supply rejection ratio of LDO. The simulation settings are tt process angle, 25℃, power supply voltage of 5V, and output current range of 0mA. The solid line in the figure above is the power supply rejection ratio of LDO. According to the simulation waveform, when the frequencies are 100Hz, 1KHz, 10KHz, 100KHz, 1.0mHz, and 10mHz, the power supply rejection ratios of LDO are 77.7dB, 77.7dB, 80.2dB, 84.9dB, 79.6dB, and 82.1dB respectively.

[0063] like Fig.12 The figure shows the simulation curve of the adjustable input voltage range of the LDO. The simulation settings are tt process angle, 25°C, power supply voltage range of 0-5.5V, and output current of 0mA. The solid line in the figure is the output voltage of the LDO. According to the simulation curve, when the power supply voltage is 4.62V, the output voltage of the LDO is 4.60456V; when the power supply voltage is 5.50V, the output voltage of the LDO is 4.60442V. Therefore, the adjustable input voltage range of the LDO is 4.62-5.50V, and the output voltage error is 132.07uV.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A LDO integrated with a novel buffer circuit, comprising a bias circuit (1), characterized in that: The bias circuit (1) is connected to an error amplifier component (2) and a switch tube component (5), the error amplifier component (2) and the switch tube component (5) are both connected to a novel buffer circuit (3), the novel buffer circuit (3) is connected to a feedback resistor component (4), and the error amplifier component (2) and the switch tube component (5) are connected.

2. The LDO integrated with the novel buffer circuit according to claim 1, characterized in that: The bias circuit (1) comprises P1, P2, P3, P4, P5, P6, P8, P9, N1, N2, N4, N5, N7, R0, R1 and IDC, the drain of P1 is electrically connected to the source of P2, the drain of P2 is electrically connected to the gates of R0 and P1, the gate of P1, the drain of P2, the gate of P3, the gate of P5 and the gate of P8 are all short-circuited, R0 is electrically connected to the drain of N2, the gate of N2 is electrically connected to the gate of N1, the gate of N2, the gate of N1 and the drain of N1 are all connected to the switch tube component (5), the drain of N1, the gate of N1 and the gate of N2 are short-circuited, and a first current mirror circuit is formed; P The drain of P3 is electrically connected to the source of P4, the drain of P4 is electrically connected to the drain of N4 through R1, the source of N4 is electrically connected to the drain of N5, the gate of N5 is electrically connected to the drain of N4, the gate of N4 is connected to the switch tube component (5), the IDC is connected to the switch tube component (5), the drain of P5 is electrically connected to the source of P6, the drain of P6 is electrically connected to the drain of N7, the gate of N7 is connected to the switch tube component (5), the drain of P8 is electrically connected to the source of P9, the drain of P9 is connected to the error amplifier component (2), the gate of P2, the drain of N2, the gate of P4, the gate of P6, and the gate of P9 are short-circuited, and the IDC is a connector.

3. The LDO with integrated novel buffer circuit according to claim 2, characterized in that: The error amplifier component (2) includes P11, P12, P13, P15, P16, P17, N10, N11, N9 and N12, the source of P11 and the source of P12 are both electrically connected to the drain of P9, the drain of P11 is electrically connected to the source of N11 and the drain of N12, the drain of N11 is connected to the novel buffer circuit (3), the drain of P12 is electrically connected to the source of N10 and the drain of N9, the drain of N10 is electrically connected to P1 The drain of N7, the gate of P13 and the gate of P15 are all electrically connected, the gate of P13 and the gate of P15 are all connected to the switch tube component (5), the drain of P15 is electrically connected to the source of P16, the drain of P16 is electrically connected to the drain of N11, the drain of N7, the gate of N7, the gate of N12 and the gate of N9 are short-circuited to form a second current mirror circuit, the gate of P16 is electrically connected to the gate of P17, and the gate of P11 is electrically connected to VREF.

4. The LDO integrated with the novel buffer circuit according to claim 3, characterized in that: The novel buffer circuit (3) comprises P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, N13, N14, N15, N16, N17, N18 and N19, wherein the drain of P19 is electrically connected to the source of P20, the drain of P20, the source of P21, the gate of P22, the gate of P23 and the gate of P24 are short-circuited, The drain of P22, the drain of P25, the drain of P26, and the gate of P28 are all electrically connected to the source of P21, the drain of P23 is electrically connected to the source of P26, the drain of P21 is electrically connected to the drain of N13 and the gate of N19, the gate of P21 is electrically connected to the drain of P16 and the drain of N11, the gate of N13 is electrically connected to the gate of N14, the gate of N15, the drain of N15, and the drain of N17. The gates of N17 are electrically connected to the gates of N5 and R1, the gates of P1, P2, P3, P5, P8 and P19 are short-circuited to form a third current mirror circuit, and the gates of N1, P4, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N30, N31, N32, N40, N41, N60, N42, N50, N60, N7, N8, N9, N10, N11, N22, N33, N41, N60, N7, N8, N9, N10, N11, N23, N41, N60, N8, N9, N10, N11, N24, N41, N60, N7, N8, N8, N9, N10, N11, N24, N41, N60 ... 10 The gate of N 11 The gate of N 17 The gates of are short-circuited to form a fourth current mirror circuit.

5. The LDO integrated with the novel buffer circuit according to claim 4, characterized in that: The feedback resistor component (4) comprises R2 and R3, the drain of P28 is electrically connected to R2, R2 and R3 are electrically connected, VFB is electrically connected between R2 and R3, and the gate of P12 is electrically connected to VFB.

6. The LDO integrated with the novel buffer circuit according to claim 5, characterized in that: The switch tube assembly (5) comprises P0, P7, P10, P14, P18, P27, P29, N0, N3, N6, N8 and N16, wherein the source of P0 is electrically connected to the IDC, the drain of P0 is electrically connected to the drain of N1, the drain of N0 is electrically connected to the gate of N1, the drain of N3 is electrically connected to the gate of N5, the drain of N6 is electrically connected to the gate of N4, the drain of N8, the drain of N7, the gate of N7, the gate of N9 and the gate of N12 are short-circuited, the drain of N16 is electrically connected to the gate of N13, the gate of N14, the gate of N15, the drain of N15, the drain of N17 and the drain of P27, the source of P27 is electrically connected to the source of P21, the gate of P2 The source of P2, the drain of P25, the drain of P26, and the gate of P28 are all electrically connected, the drain of P29, the gate of P24, the gate of P23, the gate of P22, the drain of P20, and the source of P21 are short-circuited, the drain of P18 is electrically connected to the gate of P21, the drain of P14 is electrically connected to the gate of P13 and the gate of P15, the drain of P10 is short-circuited to the gate of P3 and the gate of P7, the drain of P7 is electrically connected to the gate of P8, the gate of P0, the gate of N0, the gate of N3, the gate of N6, the gate of N8, the gate of N16, and the gate of P27 are all electrically connected, and the gate of P7, the gate of P10, the gate of P14, and the gate of P29 are all electrically connected.

7. The LDO integrated with the novel buffer circuit according to claim 6, characterized in that: The gate of P2, the drain of N2, the gate of P4, the gate of P6, the gate of P9, P 17 The gate, P 18 The gate, P 20 The gates of are short-circuited to form a fifth current mirror circuit.

8. The LDO integrated with the novel buffer circuit according to claim 7, characterized in that: The gate of N5, the drain of N1, and the gate of N18 are short-circuited to form a sixth current mirror circuit.

9. The LDO integrated with a novel buffer circuit according to claim 8, characterized in that: The IDC, the source of P1, the source of P3, the source of P5, the source of P7, the source of P8, the source of P10, the source of P13, the source of P14, the source of P15, the source of P19, the source of P22, the source of P23, the source of P24, the source of P29, and the source of P28 are all electrically connected to VDD.

10. The LDO integrated with a novel buffer circuit according to claim 9, characterized in that: The source of N0, the source of N1, the source of N2, the source of N3, the source of N5, the source of N6, the source of N7, the source of N8, the source of N9, the source of N12, the source of N13, the source of N14, the source of N16, the source of N18, the source of N19, the source of N2, R3, and the load capacitor CL are all grounded.

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