Flip chip packaging structure and electronic equipment
By setting holes on the carrier board to accommodate the second chip and realizing physical and electrical connections between the chips through dielectric material and wire bonding, the problem of excessively long chip interconnection distance in the prior art is solved, and a smaller Package thickness and better electrical performance.
Patent Information
- Application Number
- CN202421147866.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-23
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-05-23
AI Technical Summary
The existing flip chip packaging structures have increased the interconnection distance between chips due to limited trace space, which affects signal integrity.
By providing holes on the carrier plate, accommodating and installing a second chip, physical bonding is achieved using dielectric materials, and electrical connection is achieved through wire bonding, the first chip is electrically connected to the carrier plate through bumps, reducing the package thickness and size.
It realizes that the interconnection path between chips is shortened, which saves wiring space, reduces the packaging thickness and size, and improves the performance of chip products.
Smart Images
Figure CN222462894U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of packaging technology, and in particular to a flip chip packaging structure and an electronic device. Background Art
[0002] Compared with upright chips, flip chips have better heat dissipation function, low voltage, high brightness, high reliability, high saturation current density and other advantages. Therefore, flip chips are widely used in high-power devices.
[0003] In the existing flip-chip packaging, the flip chip can only be interconnected with other chips through substrate routing. When using substrate interconnection routing, the routing space is limited by the packaging process and substrate process, and the routing length is usually around 1mm. Therefore, this packaging form due to substrate interconnection routing will increase the interconnection distance between the two chips, which has a greater impact on signal integrity. Utility Model Content
[0004] The purpose of the embodiment of the present application is to provide a flip chip packaging structure and electronic device, by providing a hole on the carrier, the hole is used to accommodate and install the second chip, and the packaging area occupied by the second chip on the surface of the carrier is reduced. The second chip is physically bonded to the first chip through a dielectric material, the second chip is electrically connected to the first chip through wire bonding, and the first chip is electrically connected to the carrier through bumps, so that the thickness and size of the package are reduced, and the electrical performance of the packaged chip is better.
[0005] In a first aspect, the present application provides a flip chip packaging structure, comprising: a carrier, a first chip and a second chip, wherein the carrier is provided with a hole, the second chip is at least partially or entirely located in the hole, the second chip is connected to the first chip through a dielectric material, and the second chip is interconnected with the first chip through wire bonding, and the first chip is interconnected with the carrier through bumps.
[0006] In one embodiment, the carrier has a first surface and a second surface, the first surface forms the hole extending toward the second surface, and the first chip is interconnected with the first surface of the carrier through bumps.
[0007] In one embodiment, the flip chip packaging structure further includes: a dielectric layer; the lower surface of the dielectric layer is flush with the lower surface of the carrier, or the dielectric layer completely or partially wraps the carrier.
[0008] In one embodiment, the side surface of the hole is perpendicular or nearly perpendicular to the bottom surface.
[0009] In one embodiment, there is at least one second chip, each of the second chips is stacked in sequence in the direction of the bottom surface of the hole, and each of the second chips is interconnected with the first chip through wire bonding.
[0010] In one embodiment, there is at least one second chip, at least one hole, and adjacent holes are arranged at intervals, and the second chip at a corresponding position in each hole is interconnected with the first chip through wire bonding.
[0011] In one embodiment, there is at least one second chip, all of the second chips are at least partially or completely located in the hole, the second chip is interconnected with the first chip through wire bonding, and adjacent second chips are interconnected through wire bonding.
[0012] In one embodiment, the upper surface of the first chip is flush with the dielectric layer, and the lower surface of the carrier is flush with the dielectric layer.
[0013] In one embodiment, the carrier is a frame having frame pins; an area on the surface of the frame except the holes is interconnected with the first chip, and / or the frame pin area is interconnected with the first chip.
[0014] In a second aspect, the present application provides an electronic device comprising at least one flip chip packaging structure as described in any one of the first aspect of the present application.
[0015] Compared with the prior art, the technical solution of the present application has at least the following advantages:
[0016] In the present application, a hole is provided on the carrier board, and the hole is used to accommodate and install the second chip, thereby reducing the package area occupied by the second chip on the carrier board surface. The second chip is physically bonded to the first chip through a dielectric material, the second chip is electrically connected to the first chip through wire bonding, and the first chip is electrically connected to the carrier board through bumps.
[0017] The flip chip packaging structure of the present application can shorten the interconnection path between the first chip and the second chip, save wiring space, reduce the packaging thickness of the entire chip packaging structure, reduce the packaging size, and improve the performance of the packaged chip product. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0019] FIG. 1( a ) is a schematic diagram 1 of a flip chip packaging structure provided in the first embodiment of the present application;
[0020] FIG1( b ) is a second schematic diagram of a flip chip packaging structure provided in the first embodiment of the present application;
[0021] FIG1( c ) is a third schematic diagram of a flip chip packaging structure provided in the first embodiment of the present application;
[0022] FIG. 2( a ) is a schematic diagram 1 of a flip chip packaging structure provided in accordance with a second embodiment of the present application;
[0023] FIG2( b ) is a second schematic diagram of a flip chip packaging structure provided in accordance with the second embodiment of the present application;
[0024] FIG3( a ) is a schematic diagram 1 of a flip chip packaging structure provided in the third embodiment of the present application;
[0025] FIG3( b ) is a second schematic diagram of a flip chip packaging structure provided in the third embodiment of the present application;
[0026] FIG4( a ) is a schematic diagram 1 of a flip chip packaging structure provided in a fourth embodiment of the present application;
[0027] FIG4( b ) is a second schematic diagram of a flip chip packaging structure provided in the fourth embodiment of the present application;
[0028] Figure 5 Schematic diagram 1 of the flip chip packaging structure provided in the fifth embodiment of the present application.
[0029] Reference numerals:
[0030] 1-flip chip packaging structure; 100-carrier; 110-hole; 120-first surface; 130-second surface; 200-first chip; 300-second chip; 400-dielectric material; 500-bump; 600-dielectric layer; 700-frame; 710-frame pin. DETAILED DESCRIPTION
[0031] The terms “first”, “second”, “third”, etc. are only used for distinguishing descriptions and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.
[0032] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0033] In the description of the present application, it should be noted that the terms "inside", "outside", "left", "right", "up", "down", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the products of the present application are usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.
[0034] In the description of this application, unless otherwise clearly specified and limited, the terms "set", "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements.
[0035] The technical solution of the present application will be described below in conjunction with the accompanying drawings.
[0036] Please refer to FIG. 1( a ), which is a schematic diagram 1 of a flip chip packaging structure provided in the first embodiment of the present application. The flip chip packaging structure 1 comprises: a carrier 100, a first chip 200 and a second chip 300, the carrier 100 is provided with a hole 110, the second chip 300 is at least partially or entirely located in the hole 110, the second chip 300 is connected to the first chip 200 through a dielectric material 400, and the second chip 300 is interconnected with the first chip 200 through wire bonding, and the first chip 200 is interconnected with the carrier 100 through bumps 500.
[0037] In this embodiment, the carrier 100 can protect, support and fix the chip, and enhance the thermal conductivity and heat dissipation performance of the chip. The upper layer of the carrier 100 is connected to the chip, and the lower layer of the carrier 100 can be connected to a printed circuit board (PCB board) to achieve electrical and physical connection, signal distribution, and communication between the internal and external circuits of the chip.
[0038] By using a mature etching process, a hollowed-out hole 110 is precisely etched on the carrier 100, and the second chip 300 is accommodated and installed in the hole 110, which can reduce the package area occupied by the second chip 300 on the surface of the carrier 100. The second chip 300 is physically bonded to the first chip 200 through the dielectric material 400, the second chip 300 is electrically connected to the first chip 200 through wire bonding, and the first chip 200 is electrically connected to the carrier 100 through bumps. The flip chip packaging structure 1 in this embodiment shortens the interconnection path between the first chip 200 and the second chip 300, saves wiring space, reduces the packaging thickness of the entire flip chip packaging structure 1, reduces the packaging size, and improves the performance of the packaged chip product.
[0039] As an example, the dielectric material 400 may be a DAF film (Die Attach Film). Physical bonding between the second chip 300 and the first chip 200 is achieved through the DAF film, which can simplify the packaging process.
[0040] As an example, the bump 500 may be a microbump or a conventional bump. The material of the bump may be a solder bump, a copper pillar bump or a gold bump, which may be selected according to design requirements.
[0041] Furthermore, as shown in FIG. 1( a ), the carrier 100 has a first surface 120 and a second surface 130 , the first surface 120 forms a hole 110 extending toward the second surface 130 , and the first chip 200 is interconnected with the first surface 120 of the carrier 100 through bumps 500 .
[0042] In this embodiment, the first surface 120 is opposite to the second surface 130 . The first surface 120 forms a hole 110 structure extending toward the second surface 130 . The second chip 300 may be partially or completely placed in the hole 110 .
[0043] In order to further improve the installation stability and product reliability between the second chip 300 and the hole 110 , in some embodiments, the flip chip packaging structure 1 further includes: a dielectric layer 600 , the lower surface of the dielectric layer 600 is flush with the lower surface of the carrier 100 .
[0044] In this embodiment, when the hole 110 is etched from the first surface 120 of the carrier 100 to the second surface 130, the size of the hole 110 is slightly larger than the size of the second chip 300, so that a certain gap is left between the hole 110 and the second chip 300, so that the second chip 300 can be installed in the hole 110. The lower surface of the dielectric layer 600 is flush with the lower surface of the carrier 100. By providing the dielectric layer 600, the second chip 300 can be prevented from being offset and reliability failure. As an example, the dielectric layer 600 can be made of a material such as a plastic packaging material.
[0045] In some embodiments, the side and bottom of the hole 110 are perpendicular or nearly perpendicular. The hole 110 is preferably a straight groove, or an inclined groove with a certain inclination angle between the side and bottom, and the inclination angle between the side and bottom can be close to 90°, such as 80° to 100°.
[0046] Please refer to FIG. 1( b ), which is a second schematic diagram of the flip chip packaging structure 1 provided in the first embodiment of the present application. The flip chip packaging structure 1 in the embodiment of the present application is different from the flip chip packaging structure 1 in FIG. 1( a ) in that the dielectric layer 600 completely or partially wraps the carrier 100. By wrapping the carrier 100 completely or partially with the dielectric layer 600 , the product reliability of the flip chip packaging structure 1 can be improved.
[0047] In order to further improve the heat dissipation performance and light transmission performance of the packaging structure, in some embodiments, please refer to FIG. 1(c), which is a schematic diagram of the flip chip packaging structure provided in the first embodiment of the present application. The difference between the flip chip packaging structure 1 in the embodiment of the present application and the flip chip packaging structure 1 in FIG. 1(a) is that the upper surface of the first chip 200 is flush with the dielectric layer 600, and the lower surface of the carrier 100 is flush with the dielectric layer. Among them, the second chip 300 is physically bonded to the surface of the first chip 200 through the dielectric material 400, and is electrically connected to the first chip 200 through wire bonding. The upper surface of the first chip 200 is exposed, and the chip silicon wafer can be exposed, thereby improving the heat dissipation capacity and light transmission capacity of the chip.
[0048] In some embodiments, please refer to FIG. 2( a ), which is a schematic diagram 1 of a flip chip package structure 1 provided in a second embodiment of the present application. In the flip chip package structure 1 shown in FIG. 2( a ), there is at least one second chip 300 , each second chip 300 is stacked in sequence in the direction of the bottom surface of the hole 110 , and each second chip 300 is interconnected with the first chip 200 by wire bonding.
[0049] In this embodiment, two second chips 300 are used as an example, and the two second chips 300 are stacked in the direction of the bottom surface of the hole 110 in sequence. The adjacent second chips 300 are physically bonded by the dielectric material 400, and each second chip 300 is electrically connected to the surface of the first chip 200 by wire bonding. The lower surface of the dielectric layer 600 is flush with the lower surface of the carrier 100. The first chip 200 is interconnected with the first surface 120 of the carrier 100 through the bump 500. The flip chip packaging structure 1 in this embodiment can realize direct bonding between multiple flip chips along the thickness direction.
[0050] Please refer to FIG. 2( b ), which is a second schematic diagram of the flip chip packaging structure 1 provided in the second embodiment of the present application. The flip chip packaging structure 1 in the embodiment of the present application is different from the flip chip packaging structure 1 in FIG. 2( a ) in that the dielectric layer 600 completely or partially wraps the carrier 100. By wrapping the carrier 100 completely or partially with the dielectric layer 600 , the product reliability of the flip chip packaging structure 1 can be improved.
[0051] In some embodiments, please refer to FIG. 3( a ), which is a schematic diagram 1 of a flip chip package structure 1 provided in the third embodiment of the present application. In the flip chip package structure 1 shown in FIG. 3( a ), the second chip 300 is provided as at least one, the hole 110 is provided as at least one, and adjacent holes 110 are arranged at intervals, and the second chip 300 at the corresponding position in each hole 110 is interconnected with the first chip 200 through wire bonding.
[0052] In this embodiment, two second chips 300 are used as an example. The difference from the packaging structure shown in FIG. 2(a) is that the second chip 300 is bonded to the surface of the first chip 200 through the dielectric material 400. At the same time, holes 110 corresponding to the number of the second chips 300 are etched on the carrier 100, so that the second chips 300 are installed in the holes of the carrier 100, and each second chip 300 is electrically connected to the surface of the first chip 200 through wire bonding. The lower surface of the dielectric layer 600 is flush with the lower surface of the carrier 100. The first chip 200 is interconnected with the first surface 120 of the carrier 100 through the bumps 500. In this embodiment, the flip chip packaging structure 1 can realize multiple flip chip flat packaging.
[0053] Please refer to FIG3(b), which is a second schematic diagram of the flip chip packaging structure 1 provided in the third embodiment of the present application. The difference between the flip chip packaging structure 1 in the embodiment of the present application and the flip chip packaging structure 1 in FIG3(a) is that the dielectric layer 600 completely or partially wraps the carrier 100. By wrapping the carrier 100 completely or partially with the dielectric layer 600, the product reliability of the flip chip packaging structure 1 can be improved.
[0054] In some embodiments, please refer to FIG. 4( a ), which is a schematic diagram 1 of a flip chip package structure 1 provided in the fourth embodiment of the present application. In the flip chip package structure 1 shown in FIG. 4( a ), there is at least one second chip 300 , and all second chips 300 are at least partially or completely located in the hole 110 , and the second chip 300 is interconnected with the first chip 200 through wire bonding, and adjacent second chips 300 are interconnected through wire bonding.
[0055] In this embodiment, a hole 110 is etched on the carrier 100, and two second chips 300 are used as an example. The two second chips 300 are placed in one hole 110, and the adjacent second chips 300 are electrically connected by wire bonding. Each second chip 300 is bonded to the surface of the first chip 200 through a dielectric material 400, and the lower surface of the dielectric layer 600 is flush with the lower surface of the carrier 100. The first chip 200 is interconnected with the first surface 120 of the carrier 100 through bumps 500. In this embodiment, the flip chip packaging structure 1 can realize flip chip flat packaging, and multiple second chips 300 are directly interconnected by wire bonding.
[0056] Please refer to FIG4(b), which is a second schematic diagram of the flip chip packaging structure 1 provided in the fourth embodiment of the present application. The difference between the flip chip packaging structure 1 in the embodiment of the present application and the flip chip packaging structure 1 in FIG4(a) is that the dielectric layer 600 completely or partially wraps the carrier 100. By wrapping the carrier 100 completely or partially with the dielectric layer 600, the product reliability of the flip chip packaging structure 1 can be improved.
[0057] In some embodiments, in the flip chip package structure 1 shown in FIG. 1(a), FIG. 1(b), FIG. 1(c), FIG. 2(a), FIG. 2(b), FIG. 3(a), FIG. 3(b), FIG. 4(a), and FIG. 4(b), a solder pad or solder ball is further connected to the end of the carrier 100 away from the first chip 200. The flip chip package structure 1 is electrically connected to other electronic devices through the solder pad or solder ball.
[0058] In order to further reduce the cost and package thickness of the flip chip package structure 1, in some embodiments, please refer to Figure 5 , which is a schematic diagram of a flip chip packaging structure 1 provided in the fifth embodiment of the present application. Figure 5 In the flip chip packaging structure 1 shown, the carrier 100 is a frame 700 having frame pins 710 ; the area on the surface of the frame 700 except the holes 110 is interconnected with the first chip 200 , and / or the area of the frame pins 710 is interconnected with the first chip 200 .
[0059] The frame 700 is designed to support the chip, and it is usually made of metal material or ceramic material. The function of the frame is mainly to provide support and fixation to ensure that the electronic product will not be physically damaged during operation. In the packaging process of electronic products, the frame is often used to carry chips and other components. In this embodiment, the carrier 100 is replaced by the frame 700, and the frame 700 is bored to form a hole 110, and the second chip 300 is placed in the hole 110, and the second chip 300 and the first chip 200 are physically bonded through the dielectric material 400, and the second chip 300 and the first chip 200 are electrically connected through wire bonding. The lower surface of the dielectric layer 600 is flush with the lower surface of the frame 700. The first chip 200, except for the area where the first chip 200 and the second chip 300 are interconnected, is also electrically connected to the surface of the frame 700 through a bump, or is electrically connected to the surface of the frame pin 710 through a bump.
[0060] The flip chip packaging structure 1 shown in this embodiment can realize the vertical stacking packaging of multiple second chips 300, and can also realize the flat packaging of multiple second chips 300 or wire-bonded chips.
[0061] In summary, in the flip chip packaging structure 1 of the present application, by setting a hole 110 on the carrier 100, the hole 110 is used to accommodate and install the second chip 300, thereby reducing the packaging area occupied by the second chip 300 on the surface of the carrier 100. The second chip 300 is physically bonded to the first chip 200 through the dielectric material 400, the second chip 300 is electrically connected to the first chip 200 through wire bonding, and the first chip 200 is electrically connected to the carrier 100 through bumps. The flip chip packaging structure 1 can shorten the interconnection path between the first chip 200 and the second chip 300, save wiring space, reduce the packaging thickness of the entire flip chip packaging structure 1, reduce the packaging size, and improve the performance of the packaged chip product.
[0062] The present application also provides an electronic device, comprising at least one of the above-mentioned flip chip packaging structures 1. The electronic device may include a terminal device such as a smart phone, or a tablet computer, a smart wearable device, a smart door lock, or other types of electronic devices using the flip chip packaging structure 1.
[0063] It should be noted that, in the absence of conflict, the features in the embodiments of this application may be combined with each other.
[0064] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A flip chip packaging structure, characterized in that: include: A carrier board, a first chip and a second chip, wherein the carrier board is provided with a hole, the second chip is at least partially or completely located in the hole, the second chip is connected to the first chip through a dielectric material, and the second chip is interconnected with the first chip through wire bonding, and the first chip is interconnected with the carrier board through bumps.
2. The flip chip packaging structure according to claim 1, characterized in that: The carrier has a first surface and a second surface. The first surface forms the hole extending toward the second surface. The first chip is interconnected with the first surface of the carrier through bumps.
3. The flip chip packaging structure according to claim 1, characterized in that: The flip chip packaging structure further includes: a dielectric layer; the lower surface of the dielectric layer is flush with the lower surface of the carrier, or the dielectric layer completely or partially wraps the carrier.
4. The flip chip packaging structure according to claim 1 or 2, characterized in that: The side surface of the hole is perpendicular or nearly perpendicular to the bottom surface.
5. The flip chip packaging structure according to claim 4, characterized in that: There is at least one second chip, each of which is stacked in sequence in the direction of the bottom surface of the hole, and each of the second chips is interconnected with the first chip through wire bonding.
6. The flip chip packaging structure according to claim 1, characterized in that: There is at least one second chip, at least one hole, and adjacent holes are arranged at intervals. The second chip at a corresponding position in each hole is interconnected with the first chip through wire bonding.
7. The flip chip packaging structure according to claim 1, characterized in that: There is at least one second chip, all of the second chips are at least partially or completely located in the hole, the second chip is interconnected with the first chip through wire bonding, and adjacent second chips are interconnected through wire bonding.
8. The flip chip packaging structure according to claim 3, characterized in that: The upper surface of the first chip is flush with the dielectric layer, and the lower surface of the carrier is flush with the dielectric layer.
9. The flip chip packaging structure according to claim 1, characterized in that: The carrier board is a frame having frame pins; an area on the surface of the frame except the holes is interconnected with the first chip, and / or the frame pin area is interconnected with the first chip.
10. An electronic device, characterized in that: The invention comprises at least one flip chip packaging structure according to any one of claims 1 to 9.