Non-cds quantitative readout image sensor

Abstract

The utility model provides a non-cds quantization readout image sensor, comprising a pixel unit which is connected with a current source unit through a column line, converts an optical signal into a pixel voltage and outputs the pixel voltage through the column line; a ramp unit providing a ramp voltage; the positive input end of the comparison unit receives the pixel voltage and the slope voltage, the negative input end of the comparison unit receives the reference voltage, the sum of the pixel voltage and the slope voltage is compared with the reference voltage, and a comparison result is output; the first compensation unit is connected with the slope unit and is used for introducing the first power disturbance to the output end of the slope unit so as to suppress low-frequency-band and medium-frequency-band power disturbance in the pixel voltage; and the second compensation unit is connected with the comparison unit and introduces the second power supply disturbance to the negative input end of the comparison unit so as to suppress the full-band power supply disturbance in the pixel voltage. According to the utility model, the problem that the existing image sensor has a low power supply rejection ratio in a non-cds quantization mode is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to a non-cds quantitative readout image sensor. Background Art

[0002] Figure 1 It is the traditional cds (correlated double sampling) quantization mode. The ramp voltage Vramp is connected to the positive input terminal of the comparator through a DC blocking capacitor, and the column line is connected to the negative input terminal of the comparator through a DC blocking capacitor. The quantization timing is as follows: Figure 2 As shown, the reset signal is quantized first, then the corresponding transfer transistor is turned on, the charge is transferred to the floating diffusion node, the voltage on the column line drops, and then the image signal is quantized to achieve correlated double sampling, and the difference between the image signal and the reset signal is obtained. Since the voltage signal output by the pixel array will be affected by power supply disturbances, a positive power supply disturbance is introduced at the negative input of the comparator; the usual practice is to compensate for the positive power supply disturbance of the same amplitude at the positive input of the comparator, thereby improving the power supply rejection ratio.

[0003] Figure 3 It is a non-cds (non-true correlated double sampling) quantization mode. The ramp voltage Vramp and the column line are connected to the positive input of the comparator through a DC-blocking capacitor, and the negative input of the comparator is connected to the reference voltage Vref through a DC-blocking capacitor. The quantization timing is as follows: Figure 4 As shown, the corresponding transfer transistor is turned on, the charge is transferred to the floating diffusion node, the voltage on the column line drops, the comparator performs self-zeroing (AZ) based on the image signal, and then quantizes the image signal, then the corresponding reset transistor is turned on for reset, the voltage on the column line rises to the reset level, and then the reset signal is quantized, and finally the difference between the image signal and the reset signal is obtained. Since the voltage signal output by the pixel array will be affected by the power supply disturbance, a positive power supply disturbance is introduced at the positive input of the comparator. If the traditional method is used to compensate for the positive power supply disturbance of the same amplitude at the positive input of the comparator, the power supply disturbance at the positive input of the comparator will be larger, which will reduce the power supply rejection ratio.

[0004] In view of this, how to improve the power supply rejection ratio in the non-cds quantization mode is a technical problem that technical personnel in this field are eager to solve. Utility Model Content

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a non-cds quantization readout image sensor, so as to solve the problem of low power supply rejection ratio of the prior image sensor in the non-cds quantization mode.

[0006] In order to achieve the above-mentioned object and other related objects, the utility model provides a non-cds quantitative readout image sensor, the image sensor comprising:

[0007] A pixel unit, a current source unit, a slope unit, a comparison unit, a first compensation unit and a second compensation unit;

[0008] The pixel unit is connected to the current source unit through a column line, and is used to convert the optical signal into a pixel voltage and output it through the column line;

[0009] The ramp unit is used to provide a ramp voltage;

[0010] The comparison unit has a positive input terminal receiving the pixel voltage and the ramp voltage, and a negative input terminal receiving a reference voltage, for comparing the sum of the pixel voltage and the ramp voltage with the reference voltage and outputting a comparison result;

[0011] The first compensation unit is connected to the ramp unit and is used to introduce a first power supply disturbance into an output end of the ramp unit to suppress low- and medium-frequency power supply disturbances in the pixel voltage;

[0012] The second compensation unit is connected to the comparison unit, and is used to introduce a second power supply disturbance into the negative input terminal of the comparison unit to suppress the full-band power supply disturbance in the pixel voltage.

[0013] Optionally, the ramp unit includes a first transistor, a second transistor, a third transistor and a first switch;

[0014] The gate of the first transistor is connected to the first bias voltage through the first switch, the source is connected to the power supply voltage, and the drain is connected to the source of the second transistor and the first compensation unit;

[0015] The gate of the second transistor is connected to the second bias voltage, the drain is connected to the source of the third transistor and outputs the ramp voltage;

[0016] The gate of the third transistor is connected to the ramp input voltage, and the drain is grounded.

[0017] Optionally, the first compensation unit includes a fourth transistor, a fifth transistor, a second switch and a plurality of first compensation modules;

[0018] The gate of the fourth transistor is connected to the third bias voltage, the drain is connected to the ramp unit, and the source is connected to the drain of the fifth transistor;

[0019] The gate of the fifth transistor is connected to the fourth bias voltage through the second switch, and the source is grounded;

[0020] The first compensation module includes a first capacitor, a third switch and a fourth switch. The lower plate of the first capacitor is connected to the gate of the fifth transistor, and the upper plate is connected to the power supply voltage through the third switch and is grounded through the fourth switch.

[0021] Optionally, the second compensation unit includes a fifth switch and a plurality of second compensation modules;

[0022] The fifth switch is connected between the negative input terminal of the comparison unit and the reference voltage. The second compensation module includes a second capacitor, a sixth switch and a seventh switch. The lower plate of the second capacitor is connected to the negative input terminal of the comparison unit, and the upper plate is connected to the power supply voltage through the sixth switch and is grounded through the seventh switch.

[0023] Optionally, the current source unit includes a sixth transistor, whose gate is connected to the fifth bias, whose drain is connected to the column line, and whose source is grounded; or, the current source unit also includes a seventh transistor, wherein the sixth transistor is connected to the column line through the seventh transistor, wherein the gate of the seventh transistor is connected to the sixth bias, whose drain is connected to the column line, and whose source is connected to the drain of the sixth transistor.

[0024] Optionally, the image sensor further comprises a third compensation unit connected to the current source unit and configured to introduce a third power supply disturbance into the column line to suppress a low-frequency power supply disturbance in the pixel voltage.

[0025] Optionally, the third compensation unit includes an eighth switch and a plurality of third compensation modules;

[0026] The eighth switch is connected between the gate of the sixth transistor and the fifth bias voltage, the third compensation module includes a third capacitor, a ninth switch and a tenth switch, the lower plate of the third capacitor is connected to the gate of the sixth transistor, and the upper plate is connected to the power supply voltage through the ninth switch and is grounded through the tenth switch.

[0027] Optionally, when the first compensation module exists, the capacitance ratio of the first capacitor in each of the first compensation modules satisfies 2 0 :2 1 :…:2 a-1 , wherein a is the number of the first compensation modules and a is an integer greater than or equal to 1;

[0028] When the second compensation module exists, the capacitance ratio of the second capacitor in each second compensation module satisfies 2 0 :2 1 :…:2 b-1 , wherein b is the number of the second compensation modules and b is an integer greater than or equal to 1;

[0029] When the third compensation module exists, the capacitance ratio of the third capacitor in each of the third compensation modules satisfies 2 0 :2 1 :…:2 c-1 , wherein c is the number of the third compensation modules and c is an integer greater than or equal to 1.

[0030] Optionally, the image sensor further includes a fourth capacitor and a fifth capacitor, the fourth capacitor is connected between the column line and the positive input terminal of the comparison unit, and the fifth capacitor is connected between the output terminal of the ramp unit and the positive input terminal of the comparison unit.

[0031] Optionally, the image sensor further includes a counting unit and a storage unit;

[0032] The counting unit is connected to the comparing unit, and is used to quantize the pixel voltage according to the comparison result and output the quantization result;

[0033] The storage unit is connected to the counting unit and is used to store the quantization result.

[0034] Optionally, the image sensor includes a pixel array, the pixel array includes M pixel columns, the pixel units come from the pixel columns, wherein one pixel column corresponds to one current source unit and one comparison unit, X pixel columns share one ramp unit and one first compensation unit connected to the ramp unit, Y pixel columns share one second compensation unit, and when the image sensor includes a third compensation unit, Z pixel columns share one third compensation unit; M is an integer greater than 1, and X, Y, and Z are integers greater than or equal to 1 and less than or equal to M.

[0035] As described above, the non-CDS quantization readout image sensor of the present invention introduces a negative power disturbance at the positive input end of the comparison unit through the design of the first compensation unit, thereby suppressing the low and medium frequency power disturbances in the pixel voltage; introduces a positive power disturbance at the negative input end of the comparison unit through the design of the second compensation unit, thereby suppressing the low, medium and high frequency power disturbances in the pixel voltage; introduces a negative power disturbance on the column line through the design of the third compensation unit, thereby suppressing the low frequency power disturbance in the pixel voltage. The present invention utilizes each compensation unit to suppress the power disturbance of the column-level comparison unit, ensure the stable output of the comparison unit, avoid affecting the signal quantization result, and improve the power supply rejection ratio of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Shown is a schematic diagram of an image sensor in cds quantization mode.

[0037] Figure 2 Display as Figure 1 Quantization timing diagram of the image sensor shown.

[0038] Figure 3 Shown is a schematic diagram of an image sensor in non-cds quantization mode.

[0039] Figure 4 Display as Figure 3 Quantization timing diagram of the image sensor shown.

[0040] Figure 5 Shown is a schematic diagram of an image sensor in Embodiment 1 of the present invention.

[0041] Figure 6 Shown is a schematic diagram of a pixel unit in the first embodiment of the present invention.

[0042] Figure 7 Shown is a schematic diagram of an image sensor in the second embodiment of the present utility model.

[0043] Figure 8 Shown is a schematic diagram of an image sensor in Embodiment 3 of the present utility model.

[0044] Fig. 9 Shown is another schematic diagram of the image sensor in the third embodiment of the present utility model.

[0045] Component number description

[0046] 110 pixel unit

[0047] 120 Current source unit

[0048] 130 Slope Unit

[0049] 140 Comparison unit

[0050] 150 First compensation unit

[0051] 151 First compensation module

[0052] 160 Second compensation unit

[0053] 161 Second compensation module

[0054] 170 Third compensation unit

[0055] 171 Third compensation module

[0056] 180 counting units

[0057] 190 storage units DETAILED DESCRIPTION

[0058] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] See also Figures 5 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0060] Embodiment 1

[0061] like Figure 5 As shown, this embodiment provides a non-CDS quantization readout image sensor, including a pixel unit 110 , a current source unit 120 , a slope unit 130 , a comparison unit 140 , a first compensation unit 150 and a second compensation unit 160 .

[0062] The pixel unit 110 is connected to the current source unit 120 through the column line, and is used to convert the optical signal into a pixel voltage Vpix and output it through the column line.

[0063] As an example, Figure 6 As shown, the pixel unit 110 includes a photosensitive element PD, a transfer transistor MT, a reset transistor MR, a source follower transistor MF and a selection transistor MS. The gate of the transfer transistor MT receives a transfer control signal TX, the drain is connected to the floating diffusion node FD, and the source is grounded through the photosensitive element PD; the gate of the reset transistor MR receives a reset control signal RST, the drain is connected to the power supply voltage AVDD, and the source is connected to the floating diffusion node FD; the gate of the source follower transistor MF is connected to the floating diffusion node FD, the drain is connected to the power supply voltage AVDD, and the source is connected to the drain of the selection transistor MS; the gate of the selection transistor MS receives a selection control signal SEL, and the source is connected to the current source unit 120 through a column line.

[0064] Furthermore, the pixel unit 110 also includes a gain transistor (not shown in the figure), which is connected in series between the source of the reset transistor MR and the floating diffusion node FD, such that the gate of the gain transistor receives a gain control signal, the drain is connected to the source of the reset transistor MR, and the source is connected to the floating diffusion node FD.

[0065] Among them, Cfd is the total capacitance of the floating diffusion node FD, and Cp is the parasitic coupling capacitance between the power supply voltage AVDD and the floating diffusion node FD. It is precisely because of the existence of the parasitic coupling capacitance Cp that the disturbance on the power supply voltage AVDD will be introduced into the floating diffusion node FD and introduced into the column line through the source follower transistor MF and the selection transistor MS, thereby affecting the signal quantization result and resulting in a smaller power supply rejection ratio (PSRR).

[0066] In practical applications, the image sensor of this embodiment includes a pixel array, the pixel array includes M pixel columns, and the pixel units 110 are from the pixel columns; wherein one pixel column corresponds to one current source unit 120 and one comparison unit 140, X pixel columns share one slope unit 130 and one first compensation unit 150 to reduce area and power consumption, and Y pixel columns share one second compensation unit 160 to reduce area; M is an integer greater than 1, and X and Y are integers greater than or equal to 1 and less than or equal to M. As an optional solution, X=Y>1, so that several pixel columns that share one slope unit 130 and one first compensation unit 150 can also share one second compensation unit 160 at the same time.

[0067] The current source unit 120 is connected to the pixel unit 110 through the column line, and is used to provide output drive for the column line, so that the pixel voltage Vpix output by the pixel unit 110 can be output through the column line.

[0068] As an example, the current source unit 120 includes a sixth transistor M6 , a gate of which is connected to a fifth bias voltage VB5 , a drain of which is connected to a column line, and a source of which is grounded.

[0069] Furthermore, the current source unit 120 further includes a seventh transistor M7. At this time, the sixth transistor M6 is connected to the column line through the seventh transistor M7; wherein the gate of the seventh transistor M7 is connected to the sixth bias voltage VB6, the drain is connected to the column line, and the source is connected to the drain of the sixth transistor M6.

[0070] It should be noted that when the image sensor of this embodiment includes two or more pixel columns, the current source units 120 corresponding to the pixel columns usually have the same structure to facilitate circuit design, such as only including the sixth transistor M6, or including both the sixth transistor M6 and the seventh transistor M7.

[0071] The ramp unit 130 is used to provide a ramp voltage Vramp.

[0072] As an example, the ramp unit 130 includes a first transistor M1, a second transistor M2, a third transistor M3 and a first switch S1. The gate of the first transistor M1 is connected to the first bias voltage VB1 through the first switch S1, the source is connected to the power supply voltage AVDD, and the drain is connected to the source of the second transistor M2 and the first compensation unit 150; the gate of the second transistor M2 is connected to the second bias voltage VB2, the drain is connected to the source of the third transistor M3 and outputs the ramp voltage Vramp; the gate of the third transistor M3 is connected to the ramp input voltage Vin, and the drain is grounded.

[0073] In the ramp unit 130 of this example, the third transistor M3 is a source follower, and the first transistor M1 and the second transistor M2 form a common source and common gate structure as the load of the source follower. The ramp unit 130 is turned on and off by controlling the closing and opening of the first switch S1; wherein, when the first switch S1 is closed to turn on the ramp unit 130, the source voltage of the third transistor M3 changes with the gate voltage, that is, the ramp voltage Vramp changes with the ramp input voltage Vin.

[0074] The comparison unit 140 receives the pixel voltage Vpix and the ramp voltage Vramp at its positive input terminal and the reference voltage Vref at its negative input terminal, and is used to compare the sum of the pixel voltage Vpix and the ramp voltage Vramp with the reference voltage Vref and output a comparison result.

[0075] As an example, the comparison unit 140 includes a comparator CMP, wherein a positive input terminal of the comparator CMP receives the pixel voltage Vpix and the ramp voltage Vramp, a negative input terminal receives the reference voltage Vref, and an output terminal outputs a comparison result.

[0076] In practical applications, the pixel voltage Vpix and the ramp voltage Vramp are respectively input to the positive input terminal of the comparison unit 140 through the DC blocking capacitor. At this time, the image sensor of this embodiment further includes a fourth capacitor C4 and a fifth capacitor C5. The fourth capacitor C4 is connected between the column line and the positive input terminal of the comparison unit 140, and the fifth capacitor C5 is connected between the output terminal of the ramp unit 130 and the positive input terminal of the comparison unit 140. It should be noted that the capacitance ratio between the fourth capacitor C4 and the fifth capacitor C5 can be designed according to the gain requirement of the quantitative readout circuit in this application, and is not limited here.

[0077] The first compensation unit 150 is connected to the ramp unit 130 and is used to introduce the first power disturbance to the output end of the ramp unit 130, that is, the positive input end of the comparison unit 140, so as to suppress the low and medium frequency power disturbance in the pixel voltage Vpix.

[0078] The first compensation unit 150 of the present embodiment introduces the first power supply disturbance to the positive input terminal of the comparison unit 140 through the ramp unit 130, and the ramp unit 130 is usually shared by two or more pixel columns, which results in a relatively large parasitic coupling capacitance from the ramp unit 130 to each comparison unit 140, thereby introducing a low- and medium-frequency negative power supply disturbance at the positive input terminal of the comparison unit 140 to suppress the low- and medium-frequency positive power supply disturbance in the pixel voltage Vpix.

[0079] As an example, the first compensation unit 150 includes a fourth transistor M4, a fifth transistor M5, a second switch S2 and a plurality of first compensation modules 151. The gate of the fourth transistor M4 is connected to the third bias voltage VB3, and the drain is connected to the ramp unit 130, such as being connected to the source of the second transistor M2 in the ramp unit 130, and the source is connected to the drain of the fifth transistor M5; the gate of the fifth transistor M5 is connected to the fourth bias voltage VB4 through the second switch S2, and the source is grounded; the first compensation module 151 includes a first capacitor C1, a third switch S3 and a fourth switch S4, the lower plate of the first capacitor C1 is connected to the gate of the fifth transistor M5, and the upper plate is connected to the power supply voltage AVDD through the third switch S3 and is grounded through the fourth switch S4.

[0080] As an optional solution, the capacitance ratio of the first capacitor C1 in each first compensation module 151 satisfies 2 0 :2 1 :…:2 a -1 , wherein a is the number of the first compensation modules 151 and a is an integer greater than or equal to 1. It should be noted that the number of the first compensation modules 151 should be designed according to actual needs, and this embodiment does not limit this.

[0081] In the first compensation module 151 of this example, the third switch S3 and the fourth switch S4 are controlled by a group of control signals that are inverse to each other, so that the fourth switch S4 is opened when the third switch S3 is closed, and the fourth switch S4 is closed when the third switch S3 is opened; in addition, each first compensation module 151 can be controlled by the same or different control signals. For example, taking the first compensation unit 150 including four first compensation modules 151 as an example, the first two first compensation modules 151 are controlled by the first group of control signals so that the third switch S3 is opened and the fourth switch S4 is closed, and the last two first compensation modules 151 are controlled by the second group of control signals so that the third switch S3 is closed and the fourth switch S4 is opened. Of course, other combinations are also feasible, which has no effect on this embodiment.

[0082] In the first compensation unit 150 of this example, the fourth transistor M4 and the fifth transistor M5 form a common source and common gate structure, and the gate of the fifth transistor M5 becomes a high-resistance node by controlling the second switch S2 to be closed first and then opened; the connection node of each first compensation module 151 at the gate of the fifth transistor M5 is recorded as a first node, and the capacitance of the first node to the power supply voltage AVDD and the capacitance of the first node to the ground can be adjusted by controlling the switch of each first compensation module 151, so as to introduce the first power supply disturbance in a controllable manner.

[0083] The second compensation unit 160 is connected to the comparison unit 140 and is used to introduce the second power disturbance into the negative input terminal of the comparison unit 140 to suppress the full-band power disturbance (including low, medium and high-band power disturbance) in the pixel voltage Vpix.

[0084] The second compensation unit 160 of the present embodiment directly introduces the second power supply disturbance into the negative input terminal of the comparison unit 140, so the parasitic coupling capacitance between the two is relatively small, thereby realizing the introduction of low, medium and high frequency band positive power supply disturbance into the negative input terminal of the comparison unit 140 to suppress the low, medium and high frequency band positive power supply disturbance in the pixel voltage Vpix.

[0085] As an example, the second compensation unit 160 includes a fifth switch S5 and a plurality of second compensation modules 161. The fifth switch S5 is connected between the negative input terminal of the comparison unit 140 and the reference voltage Vref, the second compensation module 161 includes a second capacitor C2, a sixth switch S6 and a seventh switch S7, the lower plate of the second capacitor C2 is connected to the negative input terminal of the comparison unit 140, and the upper plate is connected to the power supply voltage AVDD through the sixth switch S6 and is grounded through the seventh switch S7.

[0086] As an optional solution, the capacitance ratio of the second capacitor C2 in each second compensation module 161 satisfies 2 0 :2 1 :…:2 b -1 , wherein b is the number of the second compensation modules 161 and b is an integer greater than or equal to 1. It should be noted that the number of the second compensation modules 161 should be designed according to actual needs, and this embodiment does not limit this.

[0087] In the second compensation module 161 of this example, the control method of the sixth switch S6 and the seventh switch S7 is the same as the control method of the third switch S3 and the fourth switch S4 in the first compensation module 151, but the control signals and their timing may be slightly different, which will not be repeated here.

[0088] In the second compensation unit 160 of this example, the negative input terminal of the comparison unit 140 is turned into a high-impedance node by controlling the fifth switch S5 to be closed first and then opened; the connection node of each second compensation module 161 at the negative input terminal of the comparison unit 140 is recorded as a second node, and the capacitance of the second node to the power supply voltage AVDD and the capacitance of the second node to the ground can be adjusted by controlling the switch of each second compensation module 161, so as to introduce the second power supply disturbance in a controllable manner.

[0089] Correspondingly, this embodiment also provides a method for suppressing power supply disturbance of a non-cds quantized readout image sensor, comprising the following steps; wherein the image sensor is implemented using the image sensor structure as described above.

[0090] The method includes: quantizing and reading out the pixel voltage Vpix output by the pixel unit 110; the first compensation unit 150 introduces a first power supply disturbance to the output end of the ramp unit 130 to suppress low- and medium-frequency power supply disturbances in the pixel voltage Vpix; and the second compensation unit 160 introduces a second power supply disturbance to the negative input end of the comparison unit 140 to suppress full-band power supply disturbances in the pixel voltage Vpix.

[0091] Among them, the method of introducing the first power supply disturbance to the output end of the ramp unit 130 includes: controlling the second switch S2 in the first compensation unit 150 to be closed first and then opened, so that the gate of the fifth transistor M5 in the first compensation unit 150 becomes a high-resistance node, and then introducing the first power supply disturbance to the output end of the ramp unit 130 through each first compensation module 151.

[0092] The common source and common gate structure composed of the fourth transistor M4 and the fifth transistor M5 extracts the bias current of the first transistor M1. After the sampling is stable, Idc=I0+I1 is satisfied; wherein, Idc is the current flowing through the first transistor M1, I0 is the current flowing through the second transistor M2 and the third transistor M3, and I1 is the current flowing through the fourth transistor M4 and the fifth transistor M5.

[0093] Assuming that the power supply voltage AVDD jitters upward by ΔV, the voltage coupled to the gate of the fifth transistor M5 through each first compensation module 151 will be raised upward by ΔV×Kc1. Since the source of the fifth transistor M5 is grounded, at this time, the gate-source voltage Vgs of the fifth transistor M5 increases, and the current I1 flowing through the fifth transistor M5 increases. Since Idc remains unchanged, the current I0 flowing through the third transistor M3 decreases, and the output ramp voltage Vramp will jitter downward. Conversely, assuming that the power supply voltage AVDD jitters downward by ΔV, the fifth transistor M5 The voltage of the gate coupled through each first compensation module 151 will decrease downward by ΔV×Kc1. Since the source of the fifth transistor M5 is grounded, at this time, the gate-source voltage Vgs of the fifth transistor M5 decreases, and the current I1 flowing through the fifth transistor M5 decreases. Since Idc remains unchanged, the current I0 flowing through the third transistor M3 increases, and the output ramp voltage Vramp will jitter upward; in this way, low- and medium-frequency negative power jitter is introduced at the ramp voltage Vramp to suppress the low- and medium-frequency positive power disturbance in the pixel voltage Vpix. Kc1 is the ratio of the sum of the capacitors connected to the power supply voltage AVDD in each first compensation module 151 to the total capacitance (i.e., the sum of all first capacitors C1).

[0094] Among them, the method of introducing the second power supply disturbance to the negative input terminal of the comparison unit 140 includes: controlling the fifth switch S5 in the second compensation unit 160 to be closed first and then opened, so that the negative input terminal of the comparison unit 140 becomes a high-impedance node, and then introducing the second power supply disturbance to the negative input terminal of the comparison unit 140 through each second compensation module 161.

[0095] Assuming that the power supply voltage AVDD jitters upward by ΔV, the voltage coupled to the negative input terminal of the comparison unit 140 through each second compensation module 161 will be raised by ΔV×Kc2, thereby introducing low, medium and high frequency positive power supply disturbances at the negative input terminal of the comparison unit 140 to suppress the low, medium and high frequency positive power supply disturbances in the pixel voltage Vpix. Kc2 is the ratio of the sum of the capacitors connected to the power supply voltage AVDD in each second compensation module 161 to the total capacitance (i.e., the sum of all second capacitors C2).

[0096] Embodiment 2

[0097] like Figure 7 As shown, the difference between this embodiment and the first embodiment is that the image sensor of this embodiment further includes a third compensation unit 170, which is connected to the current source unit 120 and is used to introduce a third power supply disturbance into the column line to suppress the low-frequency power supply disturbance in the pixel voltage Vpix.

[0098] In practical applications, usually Z pixel columns share one third compensation unit 170 to reduce the area, where Z is an integer greater than or equal to 1 and less than or equal to M. As an optional solution, X=Y=Z>1, so that a number of pixel columns that share one slope unit 130 and one first compensation unit 150 can also share one second compensation unit 160 and one third compensation unit 170 at the same time.

[0099] The third compensation unit 170 of this embodiment introduces the third power disturbance into the column line through the current source unit 120. The parasitic capacitance of the column line is large, thereby introducing a low-frequency negative power disturbance to suppress the low-frequency positive power disturbance in the pixel voltage Vpix.

[0100] As an example, the third compensation unit 170 includes an eighth switch S8 and a plurality of third compensation modules 171. The eighth switch S8 is connected between the gate of the sixth transistor M6 and the fifth bias voltage VB5, and the third compensation module 171 includes a third capacitor C3, a ninth switch S9 and a tenth switch S10, wherein the lower plate of the third capacitor C3 is connected to the gate of the sixth transistor M6, and the upper plate is connected to the power supply voltage AVDD through the ninth switch S9 and is grounded through the tenth switch S10.

[0101] As an optional solution, the capacitance ratio of the third capacitor C3 in each third compensation module 171 satisfies 2 0 :2 1 :…:2 c -1 , wherein c is the number of the third compensation modules 171 and c is an integer greater than or equal to 1. It should be noted that the number of the third compensation modules 171 should be designed according to actual needs, and this embodiment does not limit this.

[0102] In the third compensation module 171 of this example, the control method of the ninth switch S9 and the tenth switch S10 is the same as the control method of the third switch S3 and the fourth switch S4 of the first compensation module 151 in Example 1, but the control signals and their timing may be slightly different, which will not be repeated here.

[0103] In the third compensation unit 170 of this example, the eighth switch S8 is controlled to be closed first and then opened, so that the gate of the sixth transistor M6 becomes a high-resistance node; the connection node of each third compensation module 171 at the gate of the sixth transistor M6 is recorded as the third node, and by controlling the switch of each third compensation module 171, the capacitance of the third node to the power supply voltage AVDD and the capacitance of the third node to the ground can be adjusted to facilitate the controllable introduction of the third power supply disturbance.

[0104] Correspondingly, this embodiment also provides a method for suppressing power supply disturbance of a non-cds quantitative readout image sensor. Compared with the first embodiment, the method also includes: the third compensation unit 170 introduces the third power supply disturbance into the column line to suppress the low-frequency power supply disturbance in the pixel voltage Vpix.

[0105] Among them, the method of introducing the third power disturbance into the column line includes: controlling the eighth switch S8 in the third compensation unit 170 to be closed first and then opened, so that the gate of the sixth transistor M6 in the current source unit 120 becomes a high-resistance node, and then introducing the third power disturbance into the column line through each third compensation module 171.

[0106] Assuming that the power supply voltage AVDD jitters upward by ΔV, the voltage coupled to the gate of the sixth transistor M6 through each third compensation module 171 will be raised upward by ΔV×Kc3, and after common source amplification, a low-frequency negative power supply disturbance is introduced at the drain of the sixth transistor M6 to suppress the low-frequency positive power supply disturbance in the pixel voltage Vpix; wherein, the low-frequency negative power supply disturbance ΔVd=-g m r o ×ΔV×Kc3,-g m r o is the gain of the current source unit 120 , and Kc3 is the ratio of the sum of the capacitors connected to the power voltage AVDD in each third compensation module 171 to the total capacitance (ie, the sum of all third capacitors C3 ).

[0107] Embodiment 3

[0108] like Figure 8 and Fig. 9 As shown, the difference between this embodiment and the first and second embodiments is that the image sensor of this embodiment further includes a counting unit 180 and a storage unit 190 .

[0109] The counting unit 180 is connected to the comparing unit 140 and is used to quantize the pixel voltage Vpix according to the comparison result and output the quantization result, thereby completing the conversion of the pixel voltage Vpix from an analog signal to a digital signal.

[0110] The storage unit 190 is connected to the counting unit 180 and is used to store the quantization result to save the quantization result.

[0111] It should be noted that the addition of the counting unit 180 and the storage unit 190 has no effect on the power supply disturbance suppression method of the image sensor of this embodiment. For the related methods, please refer to the first and second embodiments, which will not be described in detail here.

[0112] In summary, the utility model is a non-CDS quantization readout image sensor, which introduces a negative power disturbance at the positive input end of the comparison unit through the design of the first compensation unit, so as to suppress the low and medium frequency power disturbance in the pixel voltage; introduces a positive power disturbance at the negative input end of the comparison unit through the design of the second compensation unit, so as to suppress the low, medium and high frequency power disturbance in the pixel voltage; introduces a negative power disturbance on the column line through the design of the third compensation unit, so as to suppress the low frequency power disturbance in the pixel voltage. The utility model utilizes each compensation unit to suppress the power disturbance of the column-level comparison unit, ensures the stable output of the comparison unit, avoids affecting the signal quantization result, and improves the power supply suppression ratio of the image sensor. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A non-cds quantitative readout image sensor, characterized in that: The image sensor comprises: A pixel unit, a current source unit, a slope unit, a comparison unit, a first compensation unit and a second compensation unit; The pixel unit is connected to the current source unit through a column line, and is used to convert the optical signal into a pixel voltage and output it through the column line; The ramp unit is used to provide a ramp voltage; The comparison unit has a positive input terminal receiving the pixel voltage and the ramp voltage, and a negative input terminal receiving a reference voltage, for comparing the sum of the pixel voltage and the ramp voltage with the reference voltage and outputting a comparison result; The first compensation unit is connected to the ramp unit and is used to introduce a first power supply disturbance into an output end of the ramp unit to suppress low- and medium-frequency power supply disturbances in the pixel voltage; The second compensation unit is connected to the comparison unit, and is used to introduce a second power supply disturbance into the negative input terminal of the comparison unit to suppress the full-band power supply disturbance in the pixel voltage.

2. The non-cds quantitative readout image sensor according to claim 1, characterized in that: The ramp unit includes a first transistor, a second transistor, a third transistor and a first switch; The gate of the first transistor is connected to the first bias voltage through the first switch, the source is connected to the power supply voltage, and the drain is connected to the source of the second transistor and the first compensation unit; The gate of the second transistor is connected to the second bias voltage, the drain is connected to the source of the third transistor and outputs the ramp voltage; The gate of the third transistor is connected to the ramp input voltage, and the drain is grounded.

3. The non-cds quantitative readout image sensor according to claim 1, characterized in that: The first compensation unit includes a fourth transistor, a fifth transistor, a second switch and a plurality of first compensation modules; The gate of the fourth transistor is connected to the third bias voltage, the drain is connected to the ramp unit, and the source is connected to the drain of the fifth transistor; The gate of the fifth transistor is connected to the fourth bias voltage through the second switch, and the source is grounded; The first compensation module includes a first capacitor, a third switch and a fourth switch. The lower plate of the first capacitor is connected to the gate of the fifth transistor, and the upper plate is connected to the power supply voltage through the third switch and is grounded through the fourth switch.

4. The non-cds quantitative readout image sensor according to claim 1, characterized in that: The second compensation unit includes a fifth switch and a plurality of second compensation modules; The fifth switch is connected between the negative input terminal of the comparison unit and the reference voltage. The second compensation module includes a second capacitor, a sixth switch and a seventh switch. The lower plate of the second capacitor is connected to the negative input terminal of the comparison unit, and the upper plate is connected to the power supply voltage through the sixth switch and is grounded through the seventh switch.

5. The non-cds quantitative readout image sensor according to claim 1, characterized in that: The current source unit includes a sixth transistor, whose gate is connected to the fifth bias voltage, whose drain is connected to the column line, and whose source is grounded; or, the current source unit also includes a seventh transistor, wherein the sixth transistor is connected to the column line through the seventh transistor, wherein the gate of the seventh transistor is connected to the sixth bias voltage, whose drain is connected to the column line, and whose source is connected to the drain of the sixth transistor.

6. The non-cds quantitative readout image sensor according to claim 5, characterized in that: The image sensor further includes a third compensation unit connected to the current source unit and configured to introduce a third power supply disturbance into the column line to suppress a low-frequency power supply disturbance in the pixel voltage.

7. The non-cds quantitative readout image sensor according to claim 6, characterized in that: The third compensation unit includes an eighth switch and a plurality of third compensation modules; The eighth switch is connected between the gate of the sixth transistor and the fifth bias voltage, the third compensation module includes a third capacitor, a ninth switch and a tenth switch, the lower plate of the third capacitor is connected to the gate of the sixth transistor, and the upper plate is connected to the power supply voltage through the ninth switch and is grounded through the tenth switch.

8. The non-cds quantitative readout image sensor according to claim 3, 4 or 7, characterized in that: When the first compensation module exists, the capacitance ratio of the first capacitor in each of the first compensation modules satisfies 2 0 :2 1 :…:2 a-1 , wherein a is the number of the first compensation modules and a is an integer greater than or equal to 1; When there is a second compensation module, the capacitance ratio of the second capacitor in each of the second compensation modules satisfies 2 0 :2 1 :…:2 b-1 , wherein b is the number of the second compensation modules and b is an integer greater than or equal to 1; When there is a third compensation module, the capacitance ratio of the third capacitor in each of the third compensation modules satisfies 2 0 :2 1 :…:2 c-1 , wherein c is the number of the third compensation modules and c is an integer greater than or equal to 1.

9. The non-cds quantitative readout image sensor according to claim 1, characterized in that: The image sensor further includes a fourth capacitor and a fifth capacitor. The fourth capacitor is connected between the column line and the positive input terminal of the comparison unit. The fifth capacitor is connected between the output terminal of the ramp unit and the positive input terminal of the comparison unit.

10. The non-cds quantitative readout image sensor according to claim 1, characterized in that: The image sensor also includes a counting unit and a storage unit; The counting unit is connected to the comparing unit, and is used to quantize the pixel voltage according to the comparison result and output the quantization result; The storage unit is connected to the counting unit and is used to store the quantization result.

11. The non-cds quantitative readout image sensor according to any one of claims 1 to 7, 9 and 10, characterized in that: The image sensor includes a pixel array, the pixel array includes M pixel columns, the pixel units come from the pixel columns, wherein one pixel column corresponds to one current source unit and one comparison unit, X pixel columns share one slope unit and one first compensation unit connected to the slope unit, Y pixel columns share one second compensation unit, and when the image sensor includes a third compensation unit, Z pixel columns share one third compensation unit; M is an integer greater than 1, and X, Y, and Z are integers greater than or equal to 1 and less than or equal to M.

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