PCB structure for improving DDR signal impedance change
By setting a specific signal via structure on the PCB board, the problem of impedance change of DDR signal trace after punching is solved, the impedance stability of DDR signal trace and the signal quality improvement is achieved, and the processing of DDR chips is simplified. process.
Patent Information
- Application Number
- CN202420761832.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-12
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-04-12
AI Technical Summary
The line width of the DDR signal trace will change between the hole discs after being punched, resulting in impedance changes, affecting the signal quality, and being difficult to process, affecting the yield rate of the DDR chip.
By providing a specific signal via structure on the PCB board, including a first signal via, a second signal via and a third signal via, the hole wall spacing between the signal vias is expanded, so that the DDR signal wiring can be achieved Consistently maintained 50Ω impedance is connected to the DDR chip.
The impedance stability of the DDR signal trace is achieved, impedance changes are avoided, signal quality is improved, and the processing process of the DDR chip is simplified and the yield rate is improved.
Smart Images
Figure CN222464898U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuit boards, and in particular to a PCB structure for improving impedance variation of DDR signals. Background Art
[0002] Printed Circuit Board (PCB), also known as printed circuit board, is an important part of the physical support and signal transmission of electronic products. DDR is an important part of electronic products. DDR (Double Data Rate) chips are widely used in PCB boards. DDR (Double Data Rate SDRAM) is called double data rate synchronous dynamic random access memory.
[0003] As the performance of electronic products continues to improve, the routing speed within the PCB board is also getting higher and higher, which puts higher requirements on the impedance control of DDR signal routing. In high-speed data transmission, routing impedance matching is crucial to the stability of signal transmission. Therefore, DDR signal routing usually requires precise 50Ω impedance processing to ensure accurate and reliable data transmission.
[0004] In conventional designs, DDR signal traces are connected to DDR chips. Because the DDR chip device disk-to-disk spacing is only 0.8mm, the usual practice is to punch holes between the disks of the DDR chip to connect to the inner layer traces. After punching, the hole disk-to-hole disk spacing in the inner layer can only pass a trace width of 0.1mm. Therefore, the DDR signal traces will change their line width here, and the impedance will change when the line width is changed. In this way, the line width of the DDR signal trace cannot be fully controlled as a 50Ω trace, causing impedance changes, which has a great impact on the DDR signal trace. In addition, in the processing of DDR chips, because the hole wall spacing between the two holes is very small, and the two holes need to pass a 0.1mm line width trace. This is difficult in processing, and the difficulty in processing will affect the processing yield of DDR chips.
[0005] The above shortcomings need to be improved. Utility Model Content
[0006] In order to overcome the problems in the prior art that the line width of DDR signal lines changes between the punched holes, causing impedance changes, and great processing difficulty, the utility model provides a PCB structure that improves the impedance change of DDR signals.
[0007] The technical solution of the utility model is as follows:
[0008] A PCB structure for improving DDR signal impedance variation comprises a PCB board, a DDR chip end is arranged on the surface of the PCB board, a plurality of groups of DDR pads for connecting to the DDR chip are arranged on the DDR chip end, each group of the DDR pads comprises three rows of DDR pads, a first signal via hole is arranged on the outside of the DDR pads in the first row of the PCB board, a second signal via hole is arranged on the outside of the DDR pads in the third row of the PCB board, and a third signal via hole is arranged in an up-and-down staggered manner between two adjacent pads in the second row of the DDR pads of the PCB board.
[0009] As a preferred solution of the present invention, the hole wall spacing between two adjacent DDR pads is 0.8 mm.
[0010] As a preferred solution of the present invention, the diameters of the first signal via hole, the second signal via hole and the third signal via hole are all 2 mm.
[0011] As a preferred solution of the present invention, the hole wall spacing between two adjacent first signal via holes is greater than 0.8 mm.
[0012] As a preferred solution of the present invention, the hole wall spacing between two adjacent second signal via holes is greater than 0.8 mm.
[0013] As a preferred solution of the present invention, the hole wall spacing between two adjacent second signal via holes is greater than 1.1 mm.
[0014] As a preferred solution of the present invention, the hole wall spacing between two adjacent third signal vias is greater than 0.8 mm.
[0015] As a preferred solution of the present invention, the hole wall spacing between adjacent first signal via holes and second signal via holes is greater than 0.8 mm.
[0016] As a preferred solution of the present invention, the hole wall spacing between adjacent second signal via holes and third signal via holes is greater than 0.8 mm.
[0017] As a preferred solution of the utility model, the inner layer of the PCB board is provided with a DDR signal line, and the distance from the DDR signal line to the hole wall of the first signal via, the second signal via and the third signal via that are not connected to it is greater than 0.25 mm.
[0018] As a preferred solution of the present invention, the impedance of the DDR signal line is 50Ω.
[0019] Compared with the prior art, the beneficial effects of the utility model are:
[0020] The utility model provides a PCB structure for improving the impedance variation of DDR signals. By changing the method of drilling signal via holes, the hole wall spacing between the signal via holes is enlarged. After the spacing is enlarged, the DDR signal wiring between two adjacent signal via holes can maintain a consistent 50Ω impedance to connect to the DDR chip. Since the impedance of the DDR signal wiring can be completely controlled to 50Ω, there is no need to change the 0.1mm line width, and therefore the impedance variation of the DDR signal will not be introduced, thereby ensuring the integrity of the DDR signal, optimizing the signal quality of the DDR signal wiring, and facilitating factory processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0022] Figure 1 This is a partial structural diagram of the surface layer of the PCB board in one embodiment of the utility model;
[0023] Figure 2 This is a schematic diagram of the partial structure of the inner layer of the PCB board in one embodiment of the utility model.
[0024] In the figure,
[0025] 1. PCB board; 2. DDR chip end; 3. DDR pad; 4. First signal via; 5. Second signal via; 6. Third signal via; 7. DDR signal routing. DETAILED DESCRIPTION
[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the utility model more clearly understood, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, it is stated that the embodiments described below are only used to explain the utility model and are not used to limit the utility model.
[0027] It should be noted that the terms "install", "set", "connect", "fix" and the like should be understood in a broad sense, for example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected, or indirectly connected through an intermediate medium, or they can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. The indication of orientation or position relationship is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the application product is usually placed when in use, or the orientation or position relationship commonly understood by those skilled in the art, or the orientation or position relationship in which the application product is usually placed when in use, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first", "second" and "third" are only used for the purpose of convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0028] In conventional designs, DDR signal traces are connected to DDR chips. Because the DDR chip device disk-to-disk spacing is only 0.8mm, the usual practice is to punch holes between the disks of the DDR chip to connect to the inner layer traces. After punching, the hole disk-to-hole disk spacing in the inner layer can only pass a trace width of 0.1mm. Therefore, the DDR signal traces will change their line width here, and the impedance will change when the line width is changed. In this way, the line width of the DDR signal trace cannot be fully controlled as a 50Ω trace, causing impedance changes, which has a great impact on the DDR signal trace. In addition, in the processing of DDR chips, because the hole wall spacing between the two holes is very small, and the two holes need to pass a 0.1mm line width trace. This is difficult in processing, and the difficulty in processing will affect the processing yield of DDR chips.
[0029] In order to solve the above problem, this embodiment provides a PCB structure for improving the impedance variation of DDR signals.
[0030] See also Figure 1 , Figure 2The PCB structure for improving DDR signal impedance variation includes a PCB board 1, a DDR chip terminal 2 is arranged on the surface of the PCB board 1, and a plurality of groups of DDR pads 3 for connecting to the DDR chip are arranged on the DDR chip terminal 2, each group of DDR pads 3 includes three rows of DDR pads 3, a first signal via hole 4 is arranged on the outer side of the first row of DDR pads 3 of the PCB board 1, a second signal via hole 5 is arranged on the outer side of the third row of DDR pads 3 of the PCB board 1, and a third signal via hole 6 is arranged between two adjacent pads of the second row of DDR pads 3 of the PCB board 1 in an up-and-down staggered manner, and a DDR signal trace 7 is arranged on the inner layer of the PCB board 1, and the DDR signal trace 7 is connected to the DDR chip through the first signal via hole 4, the second signal via hole 5 or the third signal via hole 6.
[0031] The above-mentioned PCB structure for improving the impedance variation of DDR signals increases the hole wall spacing between the signal vias by changing the method of drilling signal vias. After the spacing is increased, the DDR signal trace 7 between two adjacent signal vias can maintain a consistent 50Ω impedance to connect to the DDR chip; since the impedance of the DDR signal trace 7 can be completely controlled to 50Ω, there is no need to change the 0.1mm line width, and therefore the impedance variation of the DDR signal will not be introduced, thereby ensuring the integrity of the DDR signal, making the signal quality of the DDR signal trace 7 optimal, and facilitating factory processing.
[0032] See also Figure 1 In some specific embodiments, the DDR chip end 2 is provided with two groups of DDR pads 3 spaced apart from each other.
[0033] In one embodiment, the hole wall spacing between two adjacent DDR pads 3 is 0.8 mm. The diameters of the first signal via 4, the second signal via 5 and the third signal via 6 are all 2 mm. Since the PCB board 1 is provided with the first signal via 4 outside the first row of DDR pads 3, the PCB board 1 is provided with the second signal via 5 outside the third row of DDR pads 3, and the PCB board 1 is provided with the third signal via 6 staggered up and down between two adjacent pads of the second row of DDR pads 3, the hole wall spacing between two adjacent first signal vias 4 can be made to be greater than 0.8 mm, the hole wall spacing between two adjacent second signal vias 5 can be made to be greater than 0.8 mm, the hole wall spacing between two adjacent second signal vias 5 can be made to be greater than 0.8 mm or 1.1 mm, the hole wall spacing between the adjacent first signal vias 4 and the second signal vias 5 can be made to be greater than 0.8 mm, and the hole wall spacing between the adjacent second signal vias 5 and the third signal vias 6 can be made to be greater than 0.8 mm. In this way, the signal line width of the DDR signal routing 7 on the inner layer of the PCB board 1 can completely control the 50Ω impedance without changing the 0.1mm line width, so there is no impedance change of the DDR signal, thereby ensuring the integrity of the DDR signal and making the signal quality of the DDR signal routing 7 optimal.
[0034] In one embodiment, considering the ease of factory processing, the distance between the DDR signal trace 7 and the hole walls of the first signal via 4, the second signal via 5 and the third signal via 6 not connected thereto is at least 0.25 mm.
[0035] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.
[0036] The above is an exemplary description of the utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the utility model patent is not limited to the above-mentioned method. As long as various improvements are made by adopting the method concept and technical solution of the utility model patent, or the concept and technical solution of the utility model patent are directly applied to other occasions without improvement, they are all within the protection scope of the utility model.
Claims
1. A PCB structure for improving DDR signal impedance variation, comprising a PCB board, a DDR chip terminal is disposed on the surface of the PCB board, and the DDR chip terminal is disposed with a plurality of groups of DDR pads for connecting to the DDR chip, each group of the DDR pads comprises three rows of DDR pads, characterized in that: The PCB board is provided with first signal vias on the outside of the first row of DDR pads, the PCB board is provided with second signal vias on the outside of the third row of DDR pads, and the PCB board is provided with third signal vias staggered up and down between two adjacent pads of the second row of DDR pads.
2. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The hole wall spacing between two adjacent DDR pads is 0.8 mm.
3. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The diameters of the first signal via hole, the second signal via hole, and the third signal via hole are all 2 mm.
4. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The hole wall spacing between two adjacent first signal via holes is greater than 0.8 mm.
5. The PCB structure for improving DDR signal impedance variation according to claim 1 or 4, characterized in that: The hole wall spacing between two adjacent second signal via holes is greater than 0.8 mm.
6. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The hole wall spacing between two adjacent second signal via holes is greater than 1.1 mm.
7. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The hole wall spacing between two adjacent third signal via holes is greater than 0.8 mm.
8. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The hole wall spacing between adjacent first signal via holes and second signal via holes is greater than 0.8 mm.
9. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The hole wall spacing between adjacent second signal via holes and third signal via holes is greater than 0.8 mm.
10. The PCB structure for improving DDR signal impedance variation according to claim 1, characterized in that: The inner layer of the PCB board is provided with a DDR signal line, and the distances from the DDR signal line to the hole walls of the first signal via hole, the second signal via hole, and the third signal via hole not connected thereto are all greater than 0.25 mm.