Display panel, display device and mask

Abstract

The embodiment of the utility model provides a display panel, and belongs to the technical field of display. A display backboard in the display panel is provided with a first area, a splicing area and a second area which are sequentially connected in the first direction, and the distribution density of light-emitting units in all the areas is the same. A first signal line in the display backboard is located in the splicing area, and a second signal line is located in the first area or the second area and controls the brightness of the first light-emitting unit and the second light-emitting unit respectively. The line widths of the first signal line and the second signal line are different, and / or the areas of the first electrodes of the first light-emitting unit and the second light-emitting unit are different, and the driving conditions of the first light-emitting unit and the second light-emitting unit are the same; or the first and second signal lines are spaced from each other and extend in the second direction, the signal lines are different in line width, the areas of the first electrodes of the first and second light-emitting units are different, and the voltages provided by the first and second signal lines are different. The brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%. According to the embodiment of the invention, the problem of uneven display can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel, a display device, and a mask. Background Art

[0002] Display devices have a wide range of application scenarios in life, such as mobile phones, tablet computers and other electronic devices. Display panels are an important component of display devices.

[0003] In the related art, the display panel includes a stacked display backplane and a light-emitting functional layer. In the process of manufacturing the display panel, a mask needs to be used to expose and develop on the display backplane. However, due to the small area of ​​the mask and the technical difficulty of developing a large-size mask, the display backplane needs to be divided into a connected first area, a splicing area, and a second area. Through splicing, the production of a large-size display panel is achieved. For example, one mask is used to expose in the first area and the splicing area, and another mask is used to expose in the second area and the splicing area, that is, the splicing area is exposed twice.

[0004] Since the splicing area has been exposed twice, in the same film layer, the pattern of part of the film layer in the splicing area is different from the pattern of part of the film layer in the non-splicing area (i.e., the first area and the second area). As a result, the luminous brightness of the multiple light-emitting units located in the splicing area is greatly different from that of the multiple light-emitting units located in the non-splicing area, resulting in an uneven display problem in the display panel. Utility Model Content

[0005] The embodiments of the present disclosure provide a display panel, a display device and a mask, which can improve the problem of uneven display of the display panel. The technical solution is as follows:

[0006] In a first aspect, a display panel is provided, the display panel comprising a stacked display backplane and a light-emitting functional layer, the display backplane having a first area, a splicing area, and a second area connected in sequence in a first direction; the light-emitting functional layer comprises a plurality of light-emitting units distributed in an array, each of the light-emitting units comprising a first electrode, wherein the distribution density of the light-emitting units in the first area, the distribution density of the light-emitting units in the splicing area, and the distribution density of the light-emitting units in the second area are the same; the display backplane comprises a first signal line and a second signal line of the same layer, the first signal line is located in the splicing area, the second signal line is located in the first area or the second area, the first signal line is used to control the brightness of the first light-emitting unit, the first light-emitting unit is a light-emitting unit located in the splicing area among the plurality of light-emitting units, the second signal line is used to control the brightness of the second light-emitting unit, the second light-emitting unit is a light-emitting unit located in the first area or the second area among the plurality of light-emitting units; the line width of the first signal line is different from the line width of the second signal line, and / or the area of ​​the first electrode of the first light-emitting unit is different from the area of ​​the first electrode of the second light-emitting unit; the difference between the brightness of the first light-emitting unit and the brightness of the second light-emitting unit under the same driving conditions is within 15%.

[0007] Optionally, the first signal line and the second signal line are connected and extend along the first direction, or the first signal line and the second signal line are spaced from each other and extend in a second direction, and the second direction intersects with the first direction; the line width of the first signal line is different from the line width of the second signal line, and the area of ​​the first electrode located in the stitching area is the same as the area of ​​the first electrode located in the first area or the second area.

[0008] In a second aspect, a display panel is also provided, the display panel comprising a stacked display backplane and a light-emitting functional layer, the display backplane having a first area, a splicing area, and a second area sequentially connected in a first direction; the light-emitting functional layer comprises a plurality of light-emitting units distributed in an array, each of the light-emitting units comprises a first electrode, wherein the distribution density of the light-emitting units in the first area, the distribution density of the light-emitting units in the splicing area, and the distribution density of the light-emitting units in the second area are the same; the display backplane comprises a first signal line and a second signal line in the same layer, the first signal line is located in the splicing area, the second signal line is located in the first area or the second area, the first signal line and the second signal line are spaced apart from each other and extend in the second direction, and the second direction intersects with the first direction; A signal line is used to control the brightness of a first light-emitting unit, the first light-emitting unit is a light-emitting unit located in the stitching area among the multiple light-emitting units, and the second signal line is used to control the brightness of a second light-emitting unit, the second light-emitting unit is a light-emitting unit located in the first area or the second area among the multiple light-emitting units; the line width of the first signal line is different from the line width of the second signal line, and the area of ​​the first electrode of the first light-emitting unit is different from the area of ​​the first electrode of the second light-emitting unit; the first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit, and the first voltage and the second voltage are different in magnitude, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%.

[0009] Optionally, the line width of the first signal line is smaller than the line width of the second signal line, and the area of ​​the first electrode located in the stitching area is larger than the area of ​​the first electrode located in the first area and the second area, and the first voltage is smaller than the second voltage; or, the line width of the first signal line is larger than the line width of the second signal line, and the area of ​​the first electrode located in the stitching area is smaller than the area of ​​the first electrode located in the first area and the second area, and the first voltage is larger than the second voltage.

[0010] Optionally, the display panel also includes a plurality of microlenses and a filling layer, wherein the plurality of microlenses and the filling layer are sequentially located on a side of the light-emitting functional layer away from the display backplane, a refractive index of the plurality of microlenses is greater than a refractive index of the filling layer, the plurality of microlenses correspond one-to-one to the plurality of light-emitting units, and an orthographic projection of the plurality of microlenses on the display backplane at least partially overlaps with an orthographic projection of the plurality of light-emitting units on the display backplane.

[0011] Optionally, a refractive index of the plurality of microlenses is 0.15 to 0.8 greater than a refractive index of the filling layer.

[0012] Optionally, the display backplane is a silicon-based driving backplane.

[0013] Optionally, the display backplane also includes multiple pixel driving circuits, and the multiple pixel driving circuits are connected one-to-one with the multiple light-emitting units; the multiple pixel driving circuits include a first pixel driving circuit connected to the first light-emitting unit and a second pixel driving circuit connected to the second light-emitting unit, the first signal line is electrically connected to the first pixel driving circuit, and the second signal line is electrically connected to the second pixel driving circuit.

[0014] According to a third aspect, a display device is provided, comprising a power supply circuit and any one of the aforementioned display panels, wherein the power supply circuit supplies power to the display panel.

[0015] Optionally, the display device further includes a control circuit, which is used to be electrically connected to any one of the display panels in the second aspect and is configured to provide the first voltage to the first signal line and provide the second voltage to the second signal line.

[0016] In a fourth aspect, a mask plate is also provided for making a film layer of a display panel, wherein the display panel is any one of the aforementioned display panels; the mask plate comprises a first part and a second part connected to each other, the first part being used for making a film layer of the first area or the second area, and the second part being used for making a film layer of the splicing area; the sizes of the graphics in the graphic area of ​​the first part and the graphic area of ​​the second part are different.

[0017] The beneficial effects brought about by the technical solution provided by the present disclosure include at least: by changing the film layer pattern in the splicing area to reduce the difference in the film layer pattern between the splicing area and the first area (or the second area), thereby reducing the brightness difference between the splicing area and the first area (or the second area) of the display panel, so that the brightness difference between the first light-emitting unit and the second light-emitting unit under the same driving conditions is within 15%, thereby improving display unevenness; or, by providing voltages of different sizes to the first light-emitting unit and the second light-emitting unit respectively through the first signal line and the second signal line, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%, thereby improving display unevenness. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a schematic diagram of the relationship between the display panel size and the field of view angle provided by an embodiment of the present disclosure;

[0020] Figure 2 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 3 is a schematic diagram of a planar structure of a display backplane provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of a planar structure of another display panel provided by an embodiment of the present disclosure;

[0023] Figure 5 is a schematic diagram of a planar structure of another display panel provided by an embodiment of the present disclosure;

[0024] Figure 6 is a schematic diagram of a cross-sectional structure of a silicon-based driving backplane provided in an embodiment of the present disclosure;

[0025] Figure 7 is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0026] Figure 8 It is a structural schematic diagram of a first mask and a second mask for manufacturing a plurality of signal lines located on the same layer provided by an embodiment of the present disclosure;

[0027] Fig. 9 It is a schematic structural diagram of a third mask and a fourth mask for manufacturing a first electrode layer provided in an embodiment of the present disclosure.

[0028] Legend:

[0029] x, first direction y, second direction A, first area B, splicing area C, second area D, display area E, non-display area

[0030] 10, display backplane 11a, first signal line 11b, second signal line 12, planarization layer 12a, via 101, substrate 102, source and drain layer 1021, source 1022, drain 103, gate insulation layer 104, gate layer 1040, gate 105, first insulation layer 106, first wiring layer 107, second insulation layer 108, second wiring layer 109, isolation groove 110, protection layer 111, sidewall structure 112, metal protection layer

[0031] 20, light-emitting functional layer 21, first electrode 22, light-emitting layer 23, second electrode

[0032] 30, color filter layer 31, first color block 32, second color block 33, third color block

[0033] 40. Micro lens 41. Filling layer

[0034] 51. Encapsulation layer 52. Pixel definition layer 53. Protection layer

[0035] 601, strip structure 602, block structure

[0036] 61, first mask 61a, first part 61b, second part

[0037] 62, second mask 62a, third part 62b, fourth part

[0038] 63, third mask 63a, fifth part 63b, sixth part

[0039] 64, fourth mask 64a, seventh part 64b, eighth part DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0041] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate quantitative restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. The directional terms mentioned in the present disclosure, such as "top", "bottom", "up", "down", "left" or "right", etc., are only referenced to the directions of the drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present disclosure, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure.

[0042] Figure 1 Schematic diagram of the relationship between the display panel size and the viewing angle provided by the embodiment of the present disclosure. Figure 1As shown, the size (length or width) of the display panel is c, the distance between the display panel and the eyeball is b, and the field of view (FOV) is ω. Figure 1 It can be obtained that b, c, and ω satisfy the relationship: c = 2*b*tan(ω / 2), from which ω = 2*tan -1 [c / (2b)]. The larger ω is, the larger the FOV is, and the greater the sense of immersion the user can obtain. Under the premise that the distance b between the display panel and the eyeball remains unchanged, in order to make the FOV larger, the size c of the display panel needs to be as large as possible. However, the mask currently used to make display panels is small, and its effective exposure area is small. If the mask is used to expose a certain layer structure in the display panel at one time, the size of the display panel produced is small and cannot meet market demand.

[0043] For example, when producing silicon-based OLED (Organic Light Emitting Diode) display panels for VR (Virtual Reality) display devices, the effective exposure size of the mask is generally about 26mm*33mm. Even if the peripheral drive is not considered (that is, only the display area of ​​the display panel is considered without considering the peripheral area), the maximum display size supported by the mask is only about 1.65 inches, which cannot meet the market demand for display sizes greater than 1.7 inches.

[0044] One way to solve this problem is to develop a larger mask, but this approach will increase production costs, and the technical difficulty of developing a mask with a large effective exposure area is relatively high, and it cannot be broken through in a short time. Another way to solve this problem is to divide a larger display panel into a connected first area, a splicing area, and a second area, use a mask to expose the first area and the splicing area, and use another mask to expose the second area and the splicing area, that is, the splicing area has been exposed twice, thereby realizing the production of a large-size display panel. However, since the splicing area has been exposed twice, in the same film layer, the pattern of part of the film layer in the splicing area is different from the pattern of part of the film layer in the non-splicing area (that is, the first area and the second area). Therefore, the brightness difference between the splicing area of ​​the display panel and the first area and the second area is large (for example, the brightness difference is about 15% to 30%), resulting in uneven display.

[0045] The following describes in detail the situation where the pattern of the splicing area is different from the pattern of the non-splicing area in the same film layer due to the splicing area being exposed twice.

[0046] A mask is used to make the film layer pattern located in the first area A and the joint area B, and the size of the pattern corresponding to the first area A in the mask is the same as the size of the pattern corresponding to the joint area B; another mask is used to make the film layer pattern located in the joint area B and the second area C, and the size of the pattern corresponding to the joint area B in the mask is the same as the size of the pattern corresponding to the second area C. Since the joint area B has been exposed for many times, affected by factors such as the alignment accuracy of repeated exposure and the diffraction phenomenon during exposure, the size of the film layer in the joint area B and the first area A and the second area B in the manufactured display panel is quite different.

[0047] Since the width of the stitching area B is smaller than the width of the display panel, for example, the width of the stitching area B is about 20μm to 50μm, and the width of the display panel is about 10cm to 20cm; if the difference between the luminous brightness of the multiple light-emitting units located in the stitching area B and the luminous brightness of the multiple light-emitting units located in the first area A and the second area C is large, there will be an obvious stitching line (bright line or dark line) in the stitching area.

[0048] To this end, the embodiment of the present disclosure provides a display panel, which reduces the difference between the film layer pattern in the splicing area and the first area (or the second area) by changing the film layer pattern in the splicing area, thereby reducing the brightness difference between the splicing area and the first area (or the second area) of the display panel, so that the difference between the two is within 15%, thereby improving the display unevenness. The embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0049] Figure 2 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure. Figure 2 As shown, the display panel includes a stacked display backplane 10 and a light-emitting functional layer 20 .

[0050] Figure 3 is a schematic diagram of a planar structure of a display backplane provided by an embodiment of the present disclosure, and Figure 2 include Figure 3 Schematic diagram of the cross-sectional structure along the FF section line. Figure 3 As shown, the display backplane has a first area A, a splicing area B, and a second area C connected in sequence in a first direction x. The light-emitting functional layer 20 includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode 21. Among them, the distribution density of the light-emitting units in the first area A, the distribution density of the light-emitting units in the splicing area B, and the distribution density of the light-emitting units in the second area C are the same. Here, the distribution density refers to the number of light-emitting units per unit area. The area of ​​the first electrode 21 located in the splicing area B is the same as the area of ​​the first electrode 21 located in the first area A and the second area B.

[0051] The display backplane 10 includes a first signal line 11a and a second signal line 11b in the same layer, the first signal line is located in the splicing area B, and the second signal line 11b is located in the first area A or the second area B. The first signal line 11a is used to control the brightness of the first light-emitting unit, which is one of the multiple light-emitting units located in the splicing area B, and the second signal line 11b is used to control the brightness of the second light-emitting unit, which is one of the multiple light-emitting units located in the first area A or the second area B. The line width of the first signal line 11a is different from the line width of the second signal line 11b. The area of ​​the first electrode 21 located in the splicing area B is the same as the area of ​​the first electrode 21 located in the first area A or the second area C. The difference between the brightness of the first light-emitting unit and the brightness of the second light-emitting unit under the same driving conditions is within 15%.

[0052] Optionally, the difference between the luminous brightness of the plurality of light-emitting units located in the joint area B and the luminous brightness of the plurality of light-emitting units located in the first area A and the second area C is within 5%. Optionally, the difference between the luminous brightness of the plurality of light-emitting units located in the joint area B and the luminous brightness of the plurality of light-emitting units located in the first area A and the second area C is within 3%.

[0053] In the embodiments of the present disclosure, the same layer means formed by the same patterning process, or in contact with the same surface of the same film layer, or located on the same side of the same film layer, etc. Different layers mean formed by different patterning processes, or in contact with surfaces of different film layers, or located on different sides of the same film layer, etc.

[0054] Alternatively, if Figure 3 As shown, the first signal line 11a is connected to the second signal line 11b, and the extending direction is the first direction x.

[0055] Alternatively, if Figure 2 As shown, each light-emitting unit further includes a light-emitting layer 22 and a second electrode 23 , and the light-emitting layer 22 and the second electrode 23 are sequentially stacked on a side of the first electrode 21 away from the display backplane 10 .

[0056] Optionally, the first electrode 21 is an anode layer, and the second electrode 23 is a cathode layer.

[0057] Alternatively, if Figure 2 As shown, the light emitting layer 22 is a whole layer structure. Optionally, the light emitted by the light emitting layer 22 is white light.

[0058] Alternatively, if Figure 2 As shown, the light-emitting functional layer 20 further includes a pixel definition layer 52 . The pixel definition layer is located between the first electrode 21 and the light-emitting layer 22 . The pixel definition layer 52 is used to separate the plurality of first electrodes 21 .

[0059] For example, Figure 2 In the embodiment, the shape of the first electrode 21 is a square. Optionally, the shape of the orthographic projection of the first electrode 21 on the first surface D may also be a hexagon, a triangle, a circle, etc. The shape of the orthographic projection of the light-emitting unit 20 on the first surface D may be the shape of the first electrode 21 or the opening shape of the pixel definition layer 52 where the light-emitting unit 20 is located.

[0060] Alternatively, if Figure 2 As shown, the display panel further includes an encapsulation layer 51 , which is located on a side of the light-emitting functional layer 20 away from the display backplane 10 and is used to protect the light-emitting functional layer 20 and the film layer under the light-emitting functional layer 20 .

[0061] Alternatively, if Figure 2 As shown, the display panel further includes a color filter layer 30, which is located on the side of the encapsulation layer 40 away from the display backplane 10. The color filter layer 30 includes a plurality of color blocks distributed in an array and a black matrix located between any two adjacent color blocks, and the plurality of color blocks correspond to the plurality of light-emitting units one by one.

[0062] Optionally, the plurality of color blocks 30 include a first color block 31, a second color block 32, and a third color block 33. The colors corresponding to the first color block 31, the second color block 32, and the third color block 33 are red, green, and blue, respectively, so that the white light emitted by the light-emitting layer 22 is converted into red light, green light, and blue light to achieve color display.

[0063] Optionally, the display panel may not include the color filter layer 30. The light-emitting layer 22 includes a plurality of light-emitting blocks distributed in an array, and the plurality of light-emitting blocks emit different colors, such as red, green and blue. In this case, the pixel definition layer 52 is also used to separate the plurality of light-emitting blocks.

[0064] Alternatively, if Figure 2 As shown, the display backplane also includes a planarization layer 12, which is located between the first signal line 11a and the first electrode 21 and is used to fill the unevenness caused by the first signal line 11a and other structures, so as to facilitate the manufacture of the first electrode 21 and other structures located above the first signal line 11a.

[0065] In the embodiment of the present disclosure, the routing layer where the first signal line 11a is located is the routing layer in the display backplane that is closest to the first electrode layer where the first electrode 21 is located, that is, there is no other conductive layer between the routing layer where the first signal line 11a is located and the first electrode layer where the first electrode 21 is located.

[0066] Alternatively, if Figure 2As shown, the orthographic projection of the first signal line 11a on the display backplane 10 at least partially overlaps with the orthographic projection of the first electrode 21 of the first light-emitting unit on the display backplane 10. The orthographic projection of the second signal line 11b on the display backplane 10 at least partially overlaps with the orthographic projection of the first electrode 21 of the second light-emitting unit on the display backplane 10. The planarization layer 12 has a plurality of vias 12a, which facilitates the electrical connection of the first signal line 11a with the first electrode 21 through the vias 12a.

[0067] In the related art, different widths of the signal lines (the first signal line 11a and the second signal line 11b) may result in different areas of the first electrode 21 located in the stitching area B and the first electrode 21 located in the first area A and the second area C. This will be described in detail below.

[0068] Assuming that the width of the signal line in the splicing area B is smaller than the width of the signal line in the first area A and the second area C, the distance between two adjacent signal lines in the splicing area B is greater than the distance between two adjacent signal lines in the first area A. Therefore, when the planarization layer on the signal line is subsequently manufactured, the upper surface of the planarization layer 12 between two adjacent signal lines in the splicing area B has a concave curvature (such as Figure 2 As shown), the concave curvature of the upper surface of the planarization layer 12 between two adjacent signal lines in the first area A and the second area C is larger.

[0069] When manufacturing the first electrode 21, a whole first electrode material layer is first formed on the planarization layer 12, and then the first electrode material layer is formed into a plurality of first electrodes 21 by, for example, developing, exposing, and etching. Since the concave curvature of the upper surface of the planarization layer 12 between two adjacent signal lines in the splicing area B is greater than the concave curvature of the upper surface of the planarization layer 12 between two adjacent signal lines in the first area A and the second area C, the maximum thickness of the first electrode material layer in the splicing area B is greater than the maximum thickness of the first electrode material layer in the first area A and the second area C. When forming a plurality of first electrodes 21, the etching time required to separate the plurality of first electrodes 21 in the splicing area B is longer than the etching time required to separate the plurality of first electrodes 21 in the first area A and the second area C. In order to ensure that all the first electrodes 21 in the display panel are separated, after the etching process is completed, the first electrodes 21 in the first area A and the second area C are in an over-etched state. When etching is performed with the same photoresist pattern in the stitching area B, the first region A and the second region C, the area of ​​the first electrode 21 located in the stitching area B will be larger than the area of ​​the first electrode 21 located in the first region A and the second region C.

[0070] In some examples, the line width D1 of the first signal line 11a is 0.2μm to 0.4μm smaller than the line width D2 of the second signal line 11b, and causes the dimension D3 of the first electrode 21 of the first light-emitting unit in the second direction y to be approximately 0.1μm to 0.3μm larger than the dimension D4 of the first electrode 21 of the second light-emitting unit in the second direction y. When the dimension of the first electrode 21 in the first direction x is constant, the area of ​​the light-emitting layer 22 in contact with the first electrode 21 in the light-emitting unit located in the first area A or the second area C is larger than the area of ​​the light-emitting layer 22 in contact with the first electrode 21 in the light-emitting unit located in the stitching area B, which in turn causes the brightness of the light-emitting unit in the stitching area B to be greater than the brightness of the light-emitting unit located in the first area A or the second area C, resulting in more obvious display unevenness.

[0071] In the related art, the first mask is used to make the signal lines (the first signal line 11a and the second signal line 11b) of the first area A and the splicing area B, and the second mask is used to make the signal lines of the splicing area B and the second area B. If the width of the first photoresist pattern formed by the first mask is the same as the width of the second photoresist pattern formed by the second mask, the width of the first signal line 11a located in the splicing area B will be different from the width of the second signal line 11b located in the first area A or the second area C. This is explained below:

[0072] If the photoresist used to make the signal line is a positive photoresist, the graphic size of the first signal line 11a corresponding to the first area A in the first mask is the same as the graphic size of the second signal line 11b corresponding to the second area C in the second mask, the graphic size of the first signal line 11a corresponding to the splicing area B in the first mask is the same as the graphic size of the second signal line 11b corresponding to the splicing area B in the second mask, and the graphic size of the first signal line 11a corresponding to the first area A in the first mask is larger than the graphic size of the second signal line 11b corresponding to the splicing area B in the second mask. After exposure and development, the splicing area B is affected by repeated exposure, and the size of the photoresist structure retained in the splicing area B is smaller than the photoresist structure retained in the first area A and the second area B, which will cause the width of the first signal line 11a located in the splicing area B to be smaller than the width of the second signal line 11b located in the first area A or the second area C. If the photoresist used to make the signal line is a negative photoresist, the width of the first signal line 11a located in the stitching area B will be greater than the width of the second signal line 11b located in the first area A or the second area C. The specific process will not be repeated here.

[0073] In the embodiment of the present disclosure, the line width D1 of the first signal line 11a is different from the line width D2 of the second signal line 11b. Figure 3In the illustrated embodiment, the line width D1 of the first signal line 11a is smaller than the line width D2 of the second signal line 11b, but the area of ​​the first electrode 21 located in the stitching area B is the same as the area of ​​the first electrode 21 located in the first area A or the second area C.

[0074] By making the area of ​​the first electrode 21 located in the stitching area B the same as the area of ​​the first electrode 21 located in the first region A or the second region C, the area of ​​the light-emitting layer 22 in contact with the first electrode 21 in the light-emitting unit located in the stitching area B is made the same as the area of ​​the light-emitting layer 22 in contact with the first electrode 21 in the light-emitting unit located in the first region A or the second region C. Therefore, under the same driving conditions, the light-emitting brightness of the light-emitting unit in the stitching area B is substantially the same as that of the light-emitting unit in the first region A or the second region C. That is, the embodiment of the present disclosure reduces the difference in brightness between the light-emitting unit in the stitching area B and the light-emitting unit in the first region A or the second region C by reducing the difference in area between the first electrode in the stitching area B and the first electrode in the first region A or the second region C. Here, the same driving conditions refer to the voltage on the first signal line 11a being the same as the voltage on the second signal line 11b.

[0075] The area of ​​the first electrode 21 located in the stitching area B can be made the same as the area of ​​the first electrode 21 located in the first area A or the second area C in the following manner. After a plurality of signal lines with different line widths are manufactured, the signal lines include a thinner first signal line 11a and a thicker second signal line 11b, and then the planarization layer 12 and the plurality of first electrodes 21 are manufactured. When manufacturing the first electrode 21, a whole first electrode material layer can be formed on the planarization layer 12, and the maximum thickness of the first electrode material layer located in the stitching area B is greater than the maximum thickness of the first electrode material layer located in the first area A and the second area C.

[0076] If the photoresist used to make the first electrode is a positive photoresist, and the third mask and the fourth mask are used to make multiple first electrodes 21 respectively, the graphic size of the first electrode 21 corresponding to the first area A in the third mask can be made the same as the graphic size of the first electrode 21 corresponding to the second area C in the fourth mask, the graphic size of the first electrode 21 corresponding to the stitching area B in the third mask can be made the same as the graphic size of the first electrode 21 corresponding to the stitching area B in the fourth mask, and the graphic size of the first electrode 21 corresponding to the first area A in the third mask is larger than the graphic size of the first electrode 21 corresponding to the stitching area B in the third mask, so that after exposure and development, the size of the photoresist structure retained in the stitching area B is smaller than the photoresist structure retained in the first area A and the second area B.

[0077] When the first electrode material layer is etched to form a plurality of first electrodes 21, due to the difference in thickness of the first electrode material layer in the splicing area B, the first region A, and the second region B, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is longer than the etching time required to separate the plurality of first electrodes 21 located in the first region A and the second region C. In order to ensure that all first electrodes 21 in the display panel are separated, after the etching process is completed, the first electrodes 21 located in the first region A and the second region C are in an over-etched state, that is, the size of the first electrode 21 actually formed in the first region A and the second region C is smaller than the size of the photoresist structure retained in the first region A and the second region B, and the size of the first electrode 21 actually formed in the splicing area B is equal to the size of the photoresist structure retained in the splicing area B, so that the area of ​​the first electrode 21 located in the splicing area B is the same as the area of ​​the first electrode 21 located in the first region A or the second region C.

[0078] In another possible embodiment, the line width D1 of the first signal line 11a is larger than the line width D2 of the second signal line 11b, and the area of ​​the first electrode 21 located in the stitching area B is the same as the area of ​​the first electrode 21 located in the first area A or the second area C. Since the width of the signal line located in the stitching area B is larger than the width of the signal line located in the first area A and the second area C, the distance between two adjacent signal lines located in the stitching area B is smaller than the distance between two adjacent signal lines located in the first area A. Therefore, when the planarization layer located on the signal line is subsequently manufactured, the upper surface of the planarization layer 12 located between two adjacent signal lines in the stitching area B has a concave curvature that is smaller than the concave curvature of the upper surface of the planarization layer 12 located between two adjacent signal lines in the first area A and the second area C. When manufacturing the first electrode 21, a whole layer of the first electrode material layer can be first formed on the planarization layer 12, and the maximum thickness of the first electrode material layer located in the stitching area B is smaller than the maximum thickness of the first electrode material layer located in the first area A and the second area C. If the photoresist used to make the first electrode is a negative photoresist, and the third mask and the fourth mask are used to make multiple first electrodes 21 respectively, the graphic size of the first electrode 21 corresponding to the first area A in the third mask can be made the same as the graphic size of the first electrode 21 corresponding to the second area C in the fourth mask, the graphic size of the first electrode 21 corresponding to the stitching area B in the third mask can be made the same as the graphic size of the first electrode 21 corresponding to the stitching area B in the fourth mask, and the graphic size of the first electrode 21 corresponding to the first area A in the third mask is smaller than the graphic size of the first electrode 21 corresponding to the stitching area B in the third mask, so that after exposure and development, the size of the photoresist structure retained in the stitching area B is larger than the photoresist structure retained in the first area A and the second area B.

[0079] When the first electrode material layer is etched to form a plurality of first electrodes 21, due to the difference in thickness of the first electrode material layer in the splicing area B, the first region A, and the second region B, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is shorter than the etching time required to separate the plurality of first electrodes 21 located in the first region A and the second region C. In order to ensure that all the first electrodes 21 in the display panel are separated, after the etching process is completed, the first electrodes 21 located in the splicing area B are in an over-etched state, that is, the size of the first electrode 21 actually formed in the splicing area B is smaller than the size of the photoresist structure retained in the splicing area B. Because the size of the photoresist structure retained in the splicing area B is larger than the photoresist structure retained in the first region A and the second region B, the area of ​​the first electrode 21 located in the splicing area B can be made the same as the area of ​​the first electrode 21 located in the first region A or the second region C.

[0080] By, for example, reducing the difference between the area of ​​the first electrode 21 located in the stitching area B and the area of ​​the first electrode 21 located in the first area A or the second area C, reducing the difference between the area of ​​the first electrode 21 located in the stitching area B and the area of ​​the first electrode 21 located in the first area A or the second area C, reducing the difference between the luminous brightness of multiple light-emitting units located in the stitching area B and the luminous brightness of multiple light-emitting units located in the first area A and the second area C, the display unevenness is improved.

[0081] In other possible embodiments, the difference between the line width D1 of the first signal line 11a and the line width D2 of the second signal line 11b can also be reduced. For example, the difference between the line width of the second signal line 11b and the first signal line 11a in the embodiment of the present disclosure is smaller than the difference between the line width of the second signal line 11b and the first signal line 11a in the related art. Therefore, after the planarization layer is formed, the concave curvature of the upper surface of the planarization layer in the splicing area is smaller than the concave curvature of the upper surface of the planarization layer in the related art. This reduces the difference between the area of ​​the first electrode 21 located in the splicing area B and the area of ​​the first electrode 21 located in the first area A or the second area B. This reduces the difference between the luminous brightness of the multiple light-emitting units located in the splicing area B and the luminous brightness of the multiple light-emitting units located in the first area A and the second area C, thereby improving display unevenness.

[0082] In summary, by reducing the difference between the line width D1 of the first signal line 11a and the line width D2 of the second signal line 11b, and / or reducing the difference between the area of ​​the first electrode 21 located in the stitching area B and the area of ​​the first electrode 21 located in the first area A or the second area B, the difference between the luminous brightness of the multiple light-emitting units located in the stitching area B and the luminous brightness of the multiple light-emitting units located in the first area A and the second area C is reduced, thereby improving display unevenness.

[0083] For example, in combination Figures 2 to 3 , the first signal line 11a is electrically connected to the first electrode 21 of at least one light-emitting unit arranged along the extension direction of the first signal line 11a. The second signal line 11b is electrically connected to the first electrode 21 of at least one light-emitting unit arranged along the extension direction of the second signal line 11b. A voltage can be applied to the first electrode 21 in at least one light-emitting unit through the first signal line 11a to control the brightness of the light-emitting unit; a voltage can be applied to the first electrode 21 in at least one light-emitting unit through the second signal line 11b to control the brightness of the light-emitting unit. In this embodiment, Figure 2 and Figure 3 As shown, the first electrode 21 of the light-emitting unit controlled by the first signal line 11a is connected to the first signal line 11a through a via, and the first electrode 21 of the light-emitting unit controlled by the second signal line 11b is connected to the second signal line 11b through a via.

[0084] In this embodiment, the display panel may be a passive OLED (Organic Light-Emitting Diode) display panel.

[0085] Optionally, the second electrodes 23 of the plurality of light emitting units arranged in the second direction y are connected.

[0086] Optionally, the light emitted by the plurality of light-emitting units 20 corresponding to the plurality of first electrodes 21 electrically connected to the connected first signal line 11a and the second signal line 11b has the same color. Figure 3 In the embodiment, the light emitted by each row of light emitting units 20 has the same color.

[0087] Optionally, as shown in the figure, the display panel includes a display area D and a non-display area E, and the non-display area E surrounds the display area D. The display panel includes a plurality of pads (not shown in the figure), and the plurality of pads are located in the non-display area E. The first signal line 11a and the second signal line 11b extend to the non-display area E and are electrically connected to one of the pads. It is convenient for the outside world to input voltage to the connected first signal line 11a and the second signal line 11b through the pads, so as to realize external control of the brightness of the plurality of light-emitting units in the display panel. Optionally, the plurality of pads are located on at least one side of the display backplane, for example, on one side of the display backplane in the first direction x.

[0088] In other possible embodiments, the first signal line 11 a and the second signal line 11 b are spaced apart from each other and both extend along the first direction x.

[0089] In other possible embodiments, the first signal line 11a and the second signal line 11b are spaced apart from each other and both extend along the second direction y. In this embodiment, the arrangement of the first signal line 11a and the second signal line 11b can also be referred to in the following text. Figure 4The arrangement of the first signal line 11a and the second signal line 11b is shown in FIG.

[0090] Figure 4 is a schematic diagram of a planar structure of another display panel provided by an embodiment of the present disclosure. Compared with the above-mentioned embodiment, Figure 4 In the embodiment described above, the film pattern in the splicing area is not changed to reduce the difference in the film pattern in the splicing area B and the first area A (or the second area C), thereby reducing the brightness difference in the splicing area B and the first area A (or the second area C) of the display panel. Figure 4 As shown, the first signal line 11a and the second signal line 11b are spaced from each other and extend in the second direction y, and the second direction y intersects the first direction x. The line width D1 of the first signal line 11a is smaller than the line width D2 of the second signal line 11b, and the area of ​​the first electrode 21 located in the splicing area B is larger than the area of ​​the first electrode 21 located in the first area A and the second area A. The first signal line 11a is used to control the brightness of the first light-emitting unit, which is one of the multiple light-emitting units located in the splicing area B, and the second signal line 11b is used to control the brightness of the second light-emitting unit, which is one of the multiple light-emitting units located in the first area A or the second area C. The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit, and the first voltage and the second voltage are different in magnitude, so that the brightness of the first light-emitting unit controlled by the first signal line 11a and the brightness of the second light-emitting unit controlled by the second signal line 11b are within 15%.

[0091] like Figure 4 As shown, when the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%, the first voltage is smaller than the second voltage.

[0092] If the first mask is used to make the film layer pattern (the film layer pattern may include the first electrode and the signal line) located in the first area and the stitching area, and the second mask is used to make the film layer pattern (the film layer pattern may include the first electrode and the signal line) located in the stitching area and the second area, the graphic size corresponding to the first area in the first mask is the same as the graphic size corresponding to the stitching area, and the graphic size corresponding to the stitching area in the second mask is the same as the graphic size corresponding to the second area, which may cause the aforementioned first signal line 11a and the second signal line 11b to have different line widths, for example, the first signal line 11a is thinner and the second signal line 11b is thicker. If the same voltage is applied to the thinner first signal line 11a and the thicker second signal line 11b, since the area of ​​the first electrode 21 located in the stitching area B is larger than the area of ​​the first electrode 21 located in the first area A and the second area B, the contact area between the first electrode 21 located in the stitching area B and the light-emitting layer 22 is larger, and the brightness of the light emitted by the light-emitting unit located in the stitching area B is greater. The embodiment of the present disclosure applies a smaller voltage to the first signal line 11a with a small line width, thereby reducing the difference between the luminous brightness of multiple light-emitting units located in the stitching area B and the luminous brightness of multiple light-emitting units located in the first area A and the second area B, thereby improving display unevenness.

[0093] In other embodiments, the line width D1 of the first signal line 11a is larger than the line width D2 of the second signal line 11b, and the area of ​​the first electrode 21 located in the stitching area B is smaller than the area of ​​the first electrode 21 located in the first area and the second area. In this case, for the same brightness, the first signal line 11a is used to provide a first voltage, the second signal line 11b is used to provide a second voltage, and the first voltage is greater than the second voltage. If the same voltage is applied to the thicker first signal line 11a and the thinner second signal line 11b, since the area of ​​the first electrode 21 located in the stitching area B is smaller than the area of ​​the first electrode 21 located in the first area A and the second area A, the contact area between the first electrode 21 located in the stitching area B and the light-emitting layer 22 is smaller, and the brightness of the light emitted by the light-emitting unit located in the stitching area B is smaller. The embodiment of the present disclosure reduces the difference between the light-emitting brightness of multiple light-emitting units located in the stitching area B and the light-emitting brightness of multiple light-emitting units located in the first area A and the second area B by applying a larger voltage to the first signal line 11a with a large line width, thereby improving display unevenness.

[0094] Figure 5 FIG. 1 is a schematic diagram of a planar structure of another display panel provided by an embodiment of the present disclosure. Figure 5 As shown, the line width of the first signal line 11a is the same as the line width of the second signal line 11b, and the area of ​​the first electrode 21 located in the splicing area B is different from the area of ​​the first electrode 21 located in the first area A and the second area B.

[0095] For example, see again Figure 2, the display panel further includes a plurality of microlenses 40 and a filling layer 41, the plurality of microlenses 40 and the filling layer 41 are sequentially located on the side of the light-emitting functional layer 20 away from the display backplane 10, the refractive index of the plurality of microlenses 40 is greater than the refractive index of the filling layer 41, the plurality of microlenses 40 correspond one-to-one to the plurality of light-emitting units, the plurality of microlenses correspond one-to-one to the plurality of light-emitting units, and the orthographic projection of the plurality of microlenses on the display backplane at least partially overlaps with the orthographic projection of the plurality of light-emitting units on the display backplane. Here, the plurality of microlenses 40 may also be referred to as a light extraction layer. The smaller the aperture ratio of the first electrode 21, that is, the smaller the area of ​​the first electrode 21, the less the light-emitting layer 22 in contact with the first electrode 21, and the light-emitting layer 22 emits light under the voltage on the first electrode 21 and the second electrode 23, so the brightness of the light emitted by the light-emitting layer 22 in contact with the first electrode 21 is smaller. Here, the aperture ratio of the first electrode 21 refers to the ratio of the contact area between the plurality of first electrodes 21 and the light-emitting layer 22 to the area of ​​the display area of ​​the display panel.

[0096] The microlens 40 and the filling layer 41 can refract the light emitted by the light emitting layer 22 to the human eye as much as possible, thereby improving the brightness of the display panel.

[0097] When the aperture ratio of the first electrode 21 is smaller, the area of ​​the first electrode 21 is smaller. When the area of ​​the first electrode 21 is infinitesimally small to be a point, correspondingly, the light emitted by the part of the light-emitting layer 22 located above the first electrode 21 is also a point light source. When the point light source is located at the focus of the microlens 40, the light emitted by the point light source can be completely collimated by the microlens 40 to the light emitting surface of the display panel. The emitted light is all located in the eye box and finally reaches the human eye. At this time, the gain of the microlens 40 on the brightness of the display panel is infinite.

[0098] It can be seen from the above that the brightness of the light-emitting unit is related to the aperture ratio of the first electrode 21 and the gain of the microlens 40, and the brightness is proportional to the gain of the microlens 40, and the brightness is inversely proportional to the aperture ratio of the first electrode 21. It has been experimentally verified that when the aperture ratio of the first electrode 21 is within a certain range (<40%, also called the saturated aperture ratio), even if the area size of the first electrode 21 in different regions fluctuates to a certain extent, the gain compensation effect of the microlens 40 will cause the brightness difference of each region of the display panel to be small. When designing this solution, it is only necessary to consider the size of the saturated aperture ratio, and the aperture ratio of the first electrode 21 is designed to be less than the saturated aperture ratio. The problem of uneven display of the display panel can be improved by adaptively compensating the aperture ratio of the first electrode 21 by the microlens 40.

[0099] In such Figures 3 to 5 In any of the illustrated embodiments, the microlens 40 and the filling layer 41 are provided, and the problem of uneven display of the display panel can be improved by adaptively compensating the aperture ratio of the first electrode 21 by the microlens 40 .

[0100] Exemplarily, the refractive index of the plurality of microlenses 40 is 0.15 to 0.8 greater than the refractive index of the filling layer 41, for example, the refractive index of the microlens 40 is 1.56, and the refractive index of the filling layer 41 is 1.41; or the refractive index of the microlens 40 is 2.12, and the refractive index of the filling layer 41 is 1.32. In an ideal design, the brightness of the display panel is maximum at a normal viewing angle, that is, when the line between the human eye and the center of the display panel is perpendicular to the display panel, the brightness of the display panel is maximum. When the human eye is at other positions, the angle between the line between the human eye and the center of the display panel and the line perpendicular to the display panel is recorded as α, and the larger α is, the brightness decreases parabolically. If the refractive index of the microlens 40 is too large compared with the refractive index of the filling layer 41, as α increases, the brightness will suddenly rise after decaying to a certain extent, which is manifested as the brightness of the display panel seen at a certain position other than the normal viewing angle being particularly bright, which also means that the brightness is not fully converged to the normal viewing angle.

[0101] Optionally, the shape of the microlens 40 is hemispherical, semi-elliptical, or a shape similar to a hemispherical or semi-elliptical shape with a smooth arc surface.

[0102] Optionally, the microlens 40 is made of photoresist, PDMS (polydimethylsiloxane), PMMA (polymethyl methacrylate), silicon, silicon oxide, silicon nitride, etc., and the filling layer 41 is made of UV glue (shadowless glue), AB glue (two-liquid mixed hardening glue), OCR glue (optically transparent glue), etc.

[0103] Alternatively, if Figure 2 As shown, the display panel further includes a protective layer 53, which is located on the side of the filling layer 41 away from the display back plate 10. The protective layer 53 plays a role in protecting the display panel. Optionally, the protective layer is made of glass.

[0104] Optionally, the shape of the display panel can be as follows Figures 3 to 5 The rectangle shown may also be a circle, etc. Optionally, the splicing area B passes through the middle of the rectangular display panel, or passes through the center of the circular display panel.

[0105] In other examples, the display panel may also be an active OLED (Organic Light-Emitting Diode) display panel. In this case, the display backplane 10 also includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected one-to-one with the plurality of light-emitting units, and the plurality of pixel driving circuits include a first pixel driving circuit connected to the first light-emitting unit and a second pixel driving circuit connected to the second light-emitting unit. The first signal line 11a is electrically connected to the first pixel driving circuit. The second signal line 11b is electrically connected to the second pixel driving circuit. The first signal line 11a controls the brightness of the first light-emitting unit through the first pixel driving circuit. The second signal line 11b controls the brightness of the second light-emitting unit through the second pixel driving circuit. Optionally, the pixel driving circuit includes a plurality of transistors, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0106] Exemplarily, the display backplane further includes a plurality of third signal lines, and the extension direction of the third signal lines intersects with the extension direction of the first signal lines 11a. Each third signal line is electrically connected to at least one pixel driving circuit. The first signal line 11a and the third signal line control the first pixel driving circuit electrically connected to the first signal line 11a and the third signal line at the same time, thereby controlling the first light-emitting unit electrically connected to the first pixel driving circuit; the second signal line 11b and the third signal line control the second pixel driving circuit electrically connected to the second signal line 11b and the third signal line at the same time, thereby controlling the second light-emitting unit electrically connected to the second pixel driving circuit, thereby realizing the display function.

[0107] Exemplarily, the first signal line 11a and the second signal line 11b are data lines, and the third signal line is a gate line. That is, the first signal line 11a can be connected to the source or drain of a transistor in the first pixel driving circuit through a via hole, and the first electrode 21 of the light-emitting unit controlled by the first signal line 11a is connected to the source or drain of another transistor in the first pixel driving circuit through a via hole; the second signal line 11b can be connected to the source or drain of a transistor in the second pixel driving circuit through a via hole, and the first electrode 21 of the light-emitting unit controlled by the second signal line 11b is connected to the source or drain of another transistor in the second pixel driving circuit through a via hole.

[0108] Exemplarily, when the display panel is an active OLED display panel, the display backplane 10 can be a silicon-based drive backplane. Since a silicon mask is used to make signal lines in the process of making a silicon-based drive backplane, and the silicon mask is small and requires secondary exposure of some areas, the embodiment of the present disclosure is particularly suitable for display panels including silicon-based drive backplanes. In addition, since the display panel made of a silicon-based drive backplane has a smaller overall size, smaller pixels, and higher resolution, the display panel made of a silicon-based drive backplane is particularly suitable for VR display devices.

[0109] The structure of the silicon-based driving backplane is exemplified below. Figure 6 Schematic diagram of the cross-sectional structure of a silicon-based driving backplane provided by an embodiment of the present disclosure. Figure 6 As shown, the silicon-based driving backplane includes a plurality of transistors, and the transistors may be metal oxide semiconductor field effect transistors (metal oxide semiconductor, MOS).

[0110] Exemplarily, the silicon-based driving backplane includes a substrate 101, a source-drain electrode layer 102, a gate insulating layer 103, a gate layer 104, a first insulating layer 105, a first wiring layer 106, a second insulating layer 107, a second wiring layer 108 and a planarization layer 12 stacked in sequence. The first signal line 11a and the second signal line 11b may be located in the second wiring layer 108.

[0111] Exemplarily, the display backplane includes a stacked first wiring layer 106 and a second wiring layer 108, and the second wiring layer 108 is located on the side of the first wiring layer 106 close to the light-emitting functional layer 20. Since the source-drain electrode layer 102 and the gate layer 104 have relatively large resistances, the first wiring layer 106 is provided as a single layer, for example, above the source-drain electrode layer 102; and the second wiring layer is provided as a single layer, for example, above the gate layer 104. It is convenient to use materials with relatively low resistance, such as metal materials, to make the first signal line 11a and the second signal line 11b. The second wiring layer 108 is provided on the side of the first wiring layer 106 close to the light-emitting functional layer 200. The interference of the electrical signals in the first signal line 11a and the second signal line 11b on the transistor can be reduced.

[0112] Exemplarily, the gate layer 104 includes a gate 1040 , the source-drain layer 102 includes a source 1021 and a drain 1022 , and the gate 1040 , the source 1021 , and the drain 1022 form a transistor.

[0113] Optionally, the transistor may be an N-type MOS transistor or a P-type MOS transistor. For an N-type MOS transistor, the substrate 101 located below the N-type MOS transistor may be a P-type semiconductor, and the source 1021 and the drain 1022 may be N-type semiconductors; for a P-type MOS transistor, the substrate 101 located below the P-type MOS transistor may be an N-type semiconductor, and the source 1021 and the drain 1022 may be P-type semiconductors.

[0114] Optionally, the sidewall of the gate 1040 has a spacer structure 111 (spacer) for protecting the sidewall of the gate 1040. Exemplarily, a spacer process is used to manufacture the spacer structure 111. Optionally, the manufacturing material of the spacer structure 111 is silicon oxide.

[0115] Optionally, a metal protection layer 112 is further provided on the surface of the gate 1040 away from the substrate 101 to protect the top surface of the gate 1040 without affecting the electrical connection between the gate 1040 and other structures. Optionally, the metal protection layer 112 is made of a refractory metal.

[0116] Optionally, the silicon-based driving backplane 10 further includes a plurality of isolation trenches 109, and the isolation trenches 109 are located between two adjacent transistors. Optionally, the isolation trenches 109 are made using a shallow trench isolation (STI) process. Optionally, the isolation trenches 109 are filled with deposited oxide.

[0117] Optionally, there are multiple vias in the gate insulating layer 103 to facilitate the connection of the wiring in the first wiring layer 106 with the transistor.

[0118] Optionally, the gate layer 104 is made of one or more metal materials such as aluminum, molybdenum, copper, and titanium.

[0119] Exemplarily, the gate insulating layer 103 , the first insulating layer 105 , the first wiring layer 106 , and the second insulating layer 107 may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0120] Optionally, a protective layer 110 is provided on the surface of the wiring (eg, the first signal line 11a) to prevent the migration and diffusion of metal in the wiring and silicon in the silicon-based driving backplane. The protective layer can be made of silicon oxide or silicon nitride.

[0121] Exemplarily, the planarization layer 12 is made of an organic insulating material, such as resin.

[0122] Alternatively, in other embodiments, the display backplane 10 may be a driving backplane including a plurality of TFTs (Thin Film Transistors) instead of the aforementioned silicon-based driving backplane 10. For example, the display backplane 10 may be an LTPO (Low-temperature Polycrystalline oxide) backplane, or an LTPS (Low-Temperature Poly-Silicon) backplane. Optionally, the display backplane includes a gate layer, an active layer, and a source and drain layer. The active layer is made of a metal oxide semiconductor material such as a low-temperature polycrystalline silicon material and IGZO (Indium Gallium Zinc Oxide), or the active layer is made of a low-temperature polycrystalline silicon material.

[0123] Figure 7 FIG. 1 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Figure 7 As shown, the method includes:

[0124] In step S1, a display backplane is manufactured, wherein the display backplane comprises a first region, a splicing region, and a second region which are sequentially connected in a first direction.

[0125] In step S2, a light-emitting functional layer is manufactured on one side of the display backplane. The light-emitting functional layer includes a plurality of light-emitting units distributed in an array, each light-emitting unit includes a first electrode, and the distribution density of the light-emitting units in the first area, the distribution density of the light-emitting units in the splicing area, and the distribution density of the light-emitting units in the second area are the same. The display backplane includes a first signal line and a second signal line in the same layer, the first signal line is located in the splicing area, the second signal line is located in the first area or the second area, the first signal line is used to control the brightness of the first light-emitting unit, the first light-emitting unit is one of the plurality of light-emitting units located in the splicing area, the second signal line is used to control the brightness of the second light-emitting unit, the second light-emitting unit is one of the plurality of light-emitting units located in the first area or the second area, the line width of the first signal line is different from the line width of the second signal line, and / or the area of ​​the first electrode located in the splicing area is different from the area of ​​the first electrode located in the first area and the second area. The difference between the brightness of the first light-emitting unit and the brightness of the second light-emitting unit under the same driving conditions is within 15%. This method can be used to manufacture Figure 3 The display panel shown.

[0126] The embodiment of the present disclosure also provides another method for manufacturing a display panel, the method comprising: replacing step S2 in the above method with: manufacturing a light-emitting functional layer on one side of a display backplane. The light-emitting functional layer comprises a plurality of light-emitting units distributed in an array, each light-emitting unit comprises a first electrode, the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region and the distribution density of the light-emitting units in the second region are the same, the display backplane comprises a first signal line and a second signal line in the same layer, the first signal line is located in the splicing region, the second signal line is located in the first region or the second region, the first signal line and the second signal line are spaced from each other and the extension direction is the second direction, the second direction intersects with the first direction, the first signal line is used to control the brightness of the first light-emitting unit, the first light-emitting unit is a light-emitting unit located in the splicing region among the plurality of light-emitting units, the second signal line is used to control the brightness of the second light-emitting unit, the second light-emitting unit is a light-emitting unit located in the first region or the second region among the plurality of light-emitting units, the line width of the first signal line is different from the line width of the second signal line, and the area of ​​the first electrode of the first light-emitting unit is different from the area of ​​the first electrode of the second light-emitting unit. The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit, so that the brightness of the first light-emitting unit and the brightness of the second light-emitting unit differ by 15%. Figure 4 The display panel shown.

[0127] Figure 8 The present invention provides a schematic diagram of a structure of a first mask and a second mask for manufacturing a plurality of signal lines located on the same layer. Manufacturing a display backplane includes:

[0128] The first step is to use Figure 8 The first mask 61 shown in part a forms a first photoresist pattern, wherein the first mask 61 includes a first portion 61a and a second portion 61b, and the first portion 61a and the second portion 61b are respectively used to form different portions of the first photoresist pattern in the first area and the stitching area.

[0129] The second step is to use Figure 8 The second mask 62 shown in part b forms a second photoresist pattern, wherein the second mask 62 includes a third part 62a and a fourth part 62b, and the third part 62a and the fourth part 62b are respectively used to form different parts of the second photoresist pattern in the splicing area and the second area, and the second photoresist pattern and the first photoresist pattern at least partially overlap in the splicing area.

[0130] In the third step, based on the first photoresist pattern and the second photoresist pattern, a wiring layer is formed, wherein the wiring layer includes a first signal line and a second signal line.

[0131] Among them, the width of the graphic of the second part 61b is equal to the width of the graphic of the third part 62a, the width of the graphic area of ​​the second part 61b is greater than the width of the graphic area of ​​the first part 61a, the width of the graphic area of ​​the second part 61b is greater than the width of the graphic area of ​​the fourth part 62b, and the graphic area is the area corresponding to the signal line.

[0132] Exemplarily, when manufacturing a signal line, a whole layer of conductive material layer is obtained by, for example, deposition, and a whole layer of photoresist is formed on the conductive material layer by, for example, coating. The photoresist is exposed and developed using a mask, and a portion of the photoresist is removed by, for example, solvent dissolution, and the portion of the photoresist that is not removed forms a photoresist structure. The portion of the conductive material layer that is not covered by the photoresist structure is removed by, for example, etching, so that the portion of the conductive material layer under the photoresist structure is retained to form a signal line. Finally, the photoresist structure is removed by, for example, etching.

[0133] In a possible embodiment, the photoresist used to make the signal line is a positive photoresist. Figure 8 As shown, the first mask 61 and the second mask 62 include a plurality of strip structures 601, and the plurality of strip structures 601 correspond to a plurality of signal lines, and the width of the strip structures 601 of the second portion 61b is greater than the width of the strip structures 601 of the first portion 61a. For positive photoresist, the exposed part of the photoresist is dissolved in the subsequent processing; the unexposed part of the photoresist is not dissolved in the subsequent processing, and this part of the photoresist is used to protect the position of the corresponding signal line, so as to facilitate the formation of the signal line by, for example, etching. If the width of the strip structure 601 of the first portion 61a is the same as the width of the strip structure 601 of the second portion 61b, since the photoresist in the splicing area has undergone repeated exposure, affected by the alignment accuracy of the repeated exposure, the area where the photoresist is exposed in the actual splicing area will be larger than the area where the photoresist is exposed in the splicing area in the theoretical design, so that too much photoresist is dissolved in the subsequent processing, less photoresist is left, and the signal line formed is thinner. In the embodiment of the present disclosure, the width of the strip structure 601 of the second portion 61b is made greater than the width of the strip structure 601 of the first portion 61a, so that the difference between the width of the signal line in the splicing area and the width of the signal line in the first area or the second area is small. Optionally, the photoresist in different areas is exposed using the first mask 61 and the second mask 62, and then a development and etching process is performed.

[0134] Optionally, the width of the strip structure 601 of the second portion 61b is 5% to 10% greater than the width of the strip structure 601 of the first portion 61a. If the percentage is too small, the width of the signal line in the splicing area will be too small relative to the width of the signal line in the non-splicing area; if the percentage is too large, the width of the signal line in the splicing area will be too large relative to the width of the signal line in the non-splicing area.

[0135] In another possible embodiment, the photoresist used to make the signal line is a negative photoresist. Correspondingly, the first mask 61 and the second mask 62 include a plurality of strip openings, the plurality of strip openings correspond to a plurality of signal lines, and the width of the strip opening of the second portion 61b is smaller than the width of the strip opening of the first portion 61a. For negative photoresist, the unexposed portion of the photoresist is dissolved in the subsequent processing; the exposed portion of the photoresist is not dissolved in the subsequent processing, and this portion of the photoresist is used to protect the location of the corresponding signal line, so as to facilitate the formation of the signal line by, for example, etching. If the width of the strip opening of the first portion 61a is the same as the width of the strip opening of the second portion 61b, since the photoresist in the splicing area has undergone repeated exposure, affected by the alignment accuracy of the repeated exposure, the area where the photoresist in the actual splicing area is exposed will be larger than the area where the photoresist in the splicing area is exposed in the theoretical design, so that too much photoresist is not dissolved in the subsequent processing, and more photoresist is left, and the signal line formed is thicker. In the embodiment of the present disclosure, the width of the strip opening of the second portion 61 b ​​is smaller than the width of the strip opening of the first portion 61 a , thereby reducing the difference between the width of the signal line in the joint area and the width of the signal line in the first area or the second area.

[0136] Optionally, the width of the strip opening of the first portion 61a is 5% to 10% greater than the width of the strip opening of the second portion 61b. If the percentage is too small, the width of the signal line in the splicing area will be too large relative to the width of the signal line in the non-splicing area; if the percentage is too large, the width of the signal line in the splicing area will be too small relative to the width of the signal line in the non-splicing area.

[0137] In other embodiments, the signal line can also be manufactured in the following manner: first, a whole layer of photoresist is formed by, for example, coating, and the photoresist is exposed and developed using a mask, and a portion of the photoresist is removed by, for example, solvent dissolution, and the portion of the photoresist that is not removed forms a photoresist structure; then, a conductive material layer covering the entire layer of the photoresist structure is obtained by, for example, deposition, and the photoresist structure and the conductive material layer above the photoresist structure are removed by, for example, a metal lift-off process, and the portion of the conductive material layer that is not removed forms a signal line.

[0138] In this manufacturing method, if the photoresist is a positive photoresist, the first mask 61 and the second mask 62 include a plurality of strip openings, and the width of the strip openings of the second portion 61b is smaller than the width of the strip openings of the first portion 61a. This is explained as follows: if the width of the strip openings of the second portion 61b is equal to the width of the strip openings of the first portion 61a, that is, the graphic size of the first signal line 11a corresponding to the first region A in the first mask is the same as the graphic size of the second signal line 11b corresponding to the second region C in the second mask, the graphic size of the first signal line 11a corresponding to the splicing region B in the first mask is the same as the graphic size of the second signal line 11b corresponding to the splicing region B in the second mask, and the graphic size of the first signal line 11a corresponding to the first region A in the first mask is the same as the graphic size of the second signal line 11b corresponding to the splicing region B in the second mask. After exposure and development, the stitching area B is affected by repeated exposure, and the size of the photoresist structure removed in the stitching area B is larger than the photoresist structure removed in the first area A and the second area B. The position of the removed photoresist structure corresponds to the position of the signal line, so the width of the first signal line 11a located in the stitching area B is larger than the width of the second signal line 11b located in the first area A or the second area C. The present disclosure reduces the gap between the line width of the first signal line 11a and the line width of the second signal line 11b formed by making the width of the strip opening of the second part 61b smaller than the width of the strip opening of the first part 61a.

[0139] If the photoresist is a negative photoresist, the first mask 61 and the second mask 62 include a plurality of strip structures 601, and the width of the strip structures 601 of the second portion 61b is greater than the width of the strip structures 601 of the first portion 61a. This is explained as follows: if the width of the strip structures of the second portion 61b is equal to the width of the strip structures of the first portion 61a, that is, the graphic size of the first signal line 11a corresponding to the first region A in the first mask is the same as the graphic size of the second signal line 11b corresponding to the second region C in the second mask, the graphic size of the first signal line 11a corresponding to the splicing region B in the first mask is the same as the graphic size of the second signal line 11b corresponding to the splicing region B in the second mask, and the graphic size of the first signal line 11a corresponding to the first region A in the first mask is the same as the graphic size of the second signal line 11b corresponding to the splicing region B in the second mask. After exposure and development, the stitching area B is affected by repeated exposure, and the size of the photoresist structure removed in the stitching area B is smaller than the photoresist structure removed in the first area A and the second area B. The position of the removed photoresist structure corresponds to the position of the signal line, so the width of the first signal line 11a located in the stitching area B is smaller than the width of the second signal line 11b located in the first area A or the second area C. The present disclosure reduces the gap between the line width of the first signal line 11a and the line width of the second signal line 11b formed by making the width of the strip structure of the second part 61b larger than the width of the strip structure of the first part 61a.

[0140] Fig. 9 The third mask and the fourth mask provided in the embodiment of the present disclosure are schematic diagrams of the structure of the first electrode layer. The first electrode layer includes a plurality of first electrodes.

[0141] The first step is to use Fig. 9 The third mask 63 shown in part (a) forms a second photoresist pattern, wherein the third mask 63 includes a fifth portion 63a and a sixth portion 63b, and the fifth portion 63a and the sixth portion 63b are respectively used to form different portions of the third photoresist pattern in the first area and the stitching area.

[0142] The second step is to use Fig. 9 The fourth mask 64 shown in part (b) forms a fourth photoresist pattern, wherein the fourth mask 64 includes a seventh portion 64a and an eighth portion 64b, and the seventh portion 64a and the eighth portion 64b are respectively used to form different portions of the fourth photoresist pattern in the stitching area and the second area.

[0143] The third step is to form a plurality of first electrodes based on the third photoresist pattern and the fourth photoresist pattern.

[0144] Among them, the figure of the sixth part 63b and the figure of the seventh part 64a are congruent figures, the figure of the fifth part 63a and the figure of the eighth part 64b are congruent figures, the area of ​​the figure of the sixth part 63b is smaller than the area of ​​the figure of the fifth part 63a, and the figure of the sixth part 63b and the figure of the fifth part 63a are similar figures, and the figure is the area corresponding to the first electrode 21.

[0145] When the photoresist used to make the signal line is a positive photoresist, and the widths of the strip structures of the first part and the second part in the first mask and the second mask are the same, the width of the signal line located in the splicing area B is smaller than the width of the signal line located in the first area A and the second area C. When the planarization layer located on the signal line is subsequently made, the concave curvature of the planarization layer located between two adjacent signal lines in the splicing area B is larger than the concave curvature of the planarization layer located between two adjacent signal lines in the first area A and the second area C. Therefore, when making the first electrode 21, the thickness of the first electrode material layer located in the splicing area B is larger than the thickness of the first electrode material layer located in the first area A and the second area C. When the first electrode material layer is formed into a plurality of first electrodes 21 by, for example, etching, if the area of ​​the graphic area of ​​the fifth part 63a is similar to or equal to the area of ​​the graphic area of ​​the sixth part 63b, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is longer than the etching time required to separate the plurality of first electrodes 21 located in the first area A and the second area C. In order to ensure that all the first electrodes 21 in the display panel are separated, the first electrodes 21 located in the first area A and the second area C are in an over-etched state after the etching process is completed, thereby causing the area of ​​the first electrode 21 located in the joint area B to be larger than the area of ​​the first electrode 21 located in the first area A and the second area C. In the embodiment of the present disclosure, the area of ​​the graphic area of ​​the sixth portion 63b is smaller than the area of ​​the graphic area of ​​the fifth portion 63a, so that the difference between the area of ​​the first electrode 21 in the joint area B and the area of ​​the first electrode 21 in the first area A or the second area C is smaller.

[0146] Exemplarily, when manufacturing the first electrode 21, a whole layer of the first electrode 21 material layer is obtained by, for example, deposition, and a whole layer of photoresist is formed on the first electrode 21 material layer by, for example, coating. The photoresist is exposed and developed using a mask, and a portion of the photoresist is removed by, for example, solvent dissolution, and the portion of the photoresist that is not removed forms a photoresist structure. The portion of the conductive material layer that is not covered by the photoresist structure is removed by, for example, etching, so that the portion of the first electrode 21 material layer located under the photoresist structure is retained to form a plurality of first electrodes 21. The photoresist structure is removed by, for example, etching.

[0147] In a possible embodiment, the photoresist used to make the first electrode 21 is a positive photoresist. Fig. 9 As shown, the third mask 63 and the fourth mask 64 include a plurality of block structures 602, and the plurality of block structures 602 correspond to a plurality of first electrodes 21. The area of ​​the block structure 602 of the sixth portion 63b is smaller than the area of ​​the block structure 602 of the fifth portion 63a. For positive photoresist, the exposed part of the photoresist is dissolved in the subsequent processing; the unexposed part of the photoresist is not dissolved in the subsequent processing, and this part of the photoresist is used to protect the position corresponding to the first electrode 21, so as to facilitate the formation of the first electrode 21 by, for example, etching. If the area of ​​the block structure 602 of the fifth portion 63a is the same as the area of ​​the block structure 602 of the sixth portion 63b, since the photoresist of the splicing area B has been repeatedly exposed, affected by the alignment accuracy of the repeated exposure, the area where the photoresist of the actual splicing area B is exposed will be larger than the area where the photoresist of the splicing area B is exposed in the theoretical design, so that too much photoresist is dissolved in the subsequent processing, less photoresist is left, and the area of ​​the first electrode 21 formed is smaller. In the embodiment of the present disclosure, the area of ​​the block structure 602 of the sixth portion 63b is smaller than the area of ​​the block structure 602 of the fifth portion 63a, so that the first electrode 21 located in the stitching area B is smaller, thereby improving the problem of the first electrode 21 in the stitching area B being too large.

[0148] Optionally, the area of ​​the block structure 602 of the sixth portion 63b is 5% to 20% smaller than the area of ​​the block structure 602 of the fifth portion 63a. This design can solve the problem that the area of ​​the first electrode 21 located in the stitching area B is large. If the percentage is too small, the area of ​​the first electrode 21 in the stitching area B will be too large relative to the area of ​​the first electrode 21 in the non-stitching area B; if the percentage is too large, the area of ​​the first electrode 21 in the stitching area B will be too small relative to the area of ​​the first electrode 21 in the non-stitching area B.

[0149] When the photoresist used to make the signal line is a negative photoresist, and the widths of the strip structures of the first part and the second part in the first mask and the second mask are the same, the width of the signal line located in the splicing area B is greater than the width of the signal line located in the first area A and the second area C. When the planarization layer located on the signal line is subsequently made, the concave curvature of the planarization layer located between two adjacent signal lines in the splicing area B is smaller than the concave curvature of the planarization layer located between two adjacent signal lines in the first area A and the second area C. Therefore, when making the first electrode 21, the thickness of the first electrode 21 material layer located in the splicing area B is smaller than the thickness of the first electrode 21 material layer located in the first area A and the second area C. When the first electrode 21 material layer is formed into a plurality of first electrodes 21 by, for example, etching, if the area of ​​the graphic area of ​​the fifth part 63a is similar to or equal to the area of ​​the graphic area of ​​the sixth part 63b, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is shorter than the etching time required to separate the plurality of first electrodes 21 located in the first area A and the second area C. In order to ensure that all the first electrodes 21 in the display panel are separated, the first electrodes 21 located in the splicing area B are in an over-etched state after the etching process is completed, which results in the area of ​​the first electrode 21 located in the splicing area B being smaller than the area of ​​the first electrode 21 located in the first area A and the second area C. In the embodiment of the present disclosure, the area of ​​the graphic area of ​​the sixth portion 63b is made larger than the area of ​​the graphic area of ​​the fifth portion 63a, so that the difference between the area of ​​the first electrode 21 in the splicing area B and the area of ​​the first electrode 21 in the first area A or the second area C is smaller.

[0150] In a possible embodiment, the photoresist used to make the first electrode 21 is a negative photoresist. Correspondingly, the third mask 63 and the fourth mask 64 include a plurality of block openings, the plurality of block openings correspond to the plurality of first electrodes 21, and the area of ​​the block openings of the sixth portion 63b is greater than the area of ​​the block openings of the fifth portion 63a. For negative photoresist, the unexposed portion of the photoresist is dissolved in the subsequent processing; the exposed portion of the photoresist is not dissolved in the subsequent processing, and this portion of the photoresist is used to protect the position corresponding to the first electrode 21, so as to facilitate the formation of the first electrode 21 by, for example, etching. If the area of ​​the block opening of the fifth portion 63a is the same as the area of ​​the block opening of the sixth portion 63b, since the photoresist of the splicing area B has undergone repeated exposure, affected by the alignment accuracy of the repeated exposure, the area of ​​the photoresist exposed in the actual splicing area B will be greater than the area of ​​the photoresist exposed in the splicing area B in the theoretical design, so that too much photoresist is dissolved in the subsequent processing, less photoresist is left, and the area of ​​the first electrode 21 formed is larger. In the embodiment of the present disclosure, the area of ​​the block structure 602 of the sixth portion 63b is made larger than the area of ​​the block structure 602 of the fifth portion 63a, so that the first electrode 21 located in the stitching area B is smaller, thereby improving the problem of the first electrode 21 in the stitching area B being too small.

[0151] Optionally, the area of ​​the block opening of the fifth portion is 5% to 20% smaller than the area of ​​the block opening of the sixth portion. If the percentage is too small, the area of ​​the first electrode 21 in the splicing area will be too small relative to the area of ​​the first electrode 21 in the non-splicing area; if the percentage is too large, the area of ​​the first electrode 21 in the splicing area will be too large relative to the area of ​​the first electrode 21 in the non-splicing area.

[0152] Exemplarily, when manufacturing the first electrode 21, a whole layer of photoresist may be formed by coating, for example, and the photoresist may be exposed and developed using a mask. A portion of the photoresist may be removed by solvent dissolution, for example, and the portion of the photoresist that is not removed forms a photoresist structure. A first electrode 21 material layer covering the whole layer of the photoresist structure may be obtained by deposition, for example, and the photoresist structure and the first electrode 21 material layer located above the photoresist structure may be removed by laser lift-off (LLO), for example, and the portion of the first electrode 21 material layer that is not removed forms the first electrode 21. In this manufacturing method, if the photoresist is a positive photoresist, the third mask 63 and the fourth mask 64 include a plurality of block openings, and the area of ​​the block opening of the sixth portion 63b is smaller than the area of ​​the block opening of the fifth portion 63a. If the photoresist is a negative photoresist, the third mask 63 and the fourth mask 64 include a plurality of block structures 602 , and the area of ​​the block structure 602 of the sixth portion 63 b is greater than the area of ​​the block structure 602 of the fifth portion 63 a .

[0153] Exemplarily, the first mask 61, the second mask 62, the third mask 61 or the fourth mask 64 further includes a transparent substrate, such as a quartz substrate, which can support the graphic area of ​​the mask, and the transparent material does not affect the exposure and development manufacturing process.

[0154] An embodiment of the present disclosure further provides a display device, which includes any one of the aforementioned display panels and a power supply circuit, wherein the power supply circuit is used to supply power to the display panel.

[0155] Illustratively, the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0156] The display device has the same effect as the above-mentioned display panel, which will not be described in detail here.

[0157] Exemplarily, the display device further includes a control circuit, the control circuit and Figure 4 The display panel in the illustrated embodiment is electrically connected and configured to provide a first voltage to a first signal line and a second voltage to a second signal line, and the first voltage and the second voltage are different in magnitude.

[0158] For a first light-emitting unit controlled by a first signal line and a second light-emitting unit controlled by a second signal line, in the related art, when the brightness of the first light-emitting unit and the second light-emitting unit are the same, the first voltage and the second voltage are the same in magnitude; while in the embodiment of the present disclosure, the brightness of the first light-emitting unit and the second light-emitting unit are the same, and the first voltage and the second voltage are different.

[0159] Optionally, when the display panel is Figure 4 In the display panel shown, the first voltage is greater than the second voltage, so that the brightness of the light-emitting unit controlled by the first signal line is the same as the brightness of the light-emitting unit controlled by the second signal line.

[0160] The disclosed embodiment also provides a mask plate, which is used to make a film layer of a display panel, and the display backplane includes a first area A, a splicing area B, and a second area C that are sequentially connected in a first direction x. The mask plate includes a first part and a second part that are connected, the first part is used to make a film layer in the first area or the second area, and the second part is used to make a film layer in the splicing area. The size of the graphics in the graphic area of ​​the first part and the graphics in the graphic area of ​​the second part are different. Here, the graphics in the graphic area of ​​the first part and the graphics in the graphic area of ​​the second part can be a strip structure, a strip opening, a block structure, or a block opening.

[0161] For example, for a mask used to make signal lines (including the first signal line 11a and the second signal line 11b), the difference in size of the patterns in the pattern area of ​​the first portion and the pattern area of ​​the second portion means that the sizes of the patterns in the pattern area of ​​the first portion and the pattern area of ​​the second portion in the second direction y are different. For a mask used to make a first electrode, the difference in size of the patterns in the pattern area of ​​the first portion and the pattern area of ​​the second portion means that the sizes of the patterns in the pattern area of ​​the first portion and the pattern area of ​​the second portion in the first direction x and the second direction y are different.

[0162] Exemplarily, the mask includes a first mask and a second mask. The first mask includes a first part and a second part, and the first part and the second part are respectively used to form signal lines in the first area A and the splicing area B. The second mask includes a third part and a fourth part, and the third part and the fourth part are respectively used to form signal lines in the splicing area B and the second area C. The figure of the second part is a congruent figure with the figure of the third part, the width of the figure of the second part is greater than the width of the figure of the first part, and the width of the figure of the second part is greater than the width of the figure of the fourth part.

[0163] Optionally, the first mask and the second mask include a plurality of strip structures, and the width of the strip structures in the second portion is greater than 5% to 10% of the width of the strip structures in the first portion.

[0164] Optionally, the first mask and the second mask include a plurality of strip-shaped openings, and the width of the strip-shaped openings in the first portion is greater than 5% to 10% of the width of the strip-shaped openings in the second portion.

[0165] Exemplarily, the mask includes three masks and a fourth mask. The third mask includes a fifth part and a sixth part, and the fifth part and the sixth part are respectively used to form a plurality of first electrodes in the first area A and the splicing area B, and the fourth mask includes a seventh part and an eighth part, and the seventh part and the eighth part are respectively used to form a plurality of first electrodes in the splicing area B and the second area C. The figure of the sixth part is congruent with the figure of the seventh part, the figure of the fifth part is congruent with the figure of the eighth part, the area of ​​the figure of the sixth part is smaller than the area of ​​the figure of the fifth part, and the figure of the sixth part is similar to the figure of the fifth part, and the figure is the area corresponding to the first electrode.

[0166] Optionally, the third mask and the fourth mask include a plurality of block structures, and an area of ​​the block structure of the sixth portion is smaller than 5% to 20% of an area of ​​the block structure of the fifth portion.

[0167] Optionally, the third mask and the fourth mask include a plurality of block openings, and the area of ​​the block openings in the fifth portion is smaller than 5% to 20% of the area of ​​the block openings in the sixth portion.

[0168] For other contents of the mask, please refer to the aforementioned embodiment and will not be described again here.

[0169] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises a stacked display backplane (10) and a light-emitting functional layer (20), wherein the display backplane (10) comprises a first region, a splicing region, and a second region which are sequentially connected in a first direction; The light-emitting functional layer (20) comprises a plurality of light-emitting units distributed in an array, each of the light-emitting units comprises a first electrode (21), wherein the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region and the distribution density of the light-emitting units in the second region are the same; The display backplane (10) comprises a first signal line (11a) and a second signal line (11b) of the same layer, the first signal line (11a) being located in the splicing area, the second signal line (11b) being located in the first area or the second area, the first signal line (11a) being used to control the brightness of a first light-emitting unit, the first light-emitting unit being one of the plurality of light-emitting units located in the splicing area, and the second signal line (11b) being used to control the brightness of a second light-emitting unit, the second light-emitting unit being one of the plurality of light-emitting units located in the first area or the second area; The line width of the first signal line (11a) is different from the line width of the second signal line (11b), and / or the area of ​​the first electrode (21) of the first light-emitting unit is different from the area of ​​the first electrode (21) of the second light-emitting unit; The difference between the brightness of the first light emitting unit and the brightness of the second light emitting unit under the same driving conditions is within 15%.

2. The display panel according to claim 1, characterized in that: The first signal line (11a) and the second signal line (11b) are connected and extend along the first direction, or the first signal line (11a) and the second signal line (11b) are spaced from each other and extend in a second direction, and the second direction intersects with the first direction; The line width of the first signal line (11a) is different from the line width of the second signal line (11b), and the area of ​​the first electrode (21) located in the splicing area is the same as the area of ​​the first electrode (21) located in the first area or the second area.

3. A display panel, characterized in that: The display panel comprises a stacked display backplane (10) and a light-emitting functional layer (20), wherein the display backplane (10) comprises a first region, a splicing region, and a second region which are sequentially connected in a first direction; The light-emitting functional layer (20) comprises a plurality of light-emitting units distributed in an array, each of the light-emitting units comprises a first electrode (21), wherein the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region and the distribution density of the light-emitting units in the second region are the same; The display backplane (10) comprises a first signal line and a second signal line in the same layer, the first signal line is located in the splicing area, the second signal line is located in the first area or the second area, the first signal line (11a) and the second signal line (11b) are spaced from each other and extend in a second direction, and the second direction intersects with the first direction; The first signal line (11a) is used to control the brightness of a first light-emitting unit, the first light-emitting unit being a light-emitting unit located in the splicing area among the plurality of light-emitting units, and the second signal line is used to control the brightness of a second light-emitting unit, the second light-emitting unit being a light-emitting unit located in the first area or the second area among the plurality of light-emitting units; The line width of the first signal line (11a) is different from the line width of the second signal line (11b), and the area of ​​the first electrode (21) of the first light-emitting unit is different from the area of ​​the first electrode (21) of the second light-emitting unit; The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit. The first voltage and the second voltage are different in magnitude so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%.

4. The display panel according to claim 3, characterized in that: The line width of the first signal line (11a) is smaller than the line width of the second signal line (11b), and the area of ​​the first electrode (21) located in the splicing area is larger than the areas of the first electrode (21) located in the first area and the second area, and the first voltage is smaller than the second voltage; or, The line width of the first signal line (11a) is larger than the line width of the second signal line (11b), and the area of ​​the first electrode (21) located in the splicing area is smaller than the areas of the first electrode (21) located in the first area and the second area, and the first voltage is larger than the second voltage.

5. The display panel according to any one of claims 1 to 4, characterized in that: The display panel further comprises a plurality of microlenses (40) and a filling layer (41), wherein the plurality of microlenses (40) and the filling layer (41) are sequentially located on a side of the light-emitting functional layer (20) away from the display backplane (10), the refractive index of the plurality of microlenses (40) is greater than the refractive index of the filling layer (41), the plurality of microlenses (40) correspond one-to-one to the plurality of light-emitting units, and the orthographic projections of the plurality of microlenses (40) on the display backplane (10) at least partially overlap with the orthographic projections of the plurality of light-emitting units on the display backplane (10).

6. The display panel according to claim 5, characterized in that: The refractive index of the plurality of microlenses (40) is 0.15 to 0.8 greater than the refractive index of the filling layer (41).

7. The display panel according to any one of claims 1 to 4 and claim 6, characterized in that: The display backplane (10) is a silicon-based driving backplane.

8. The display panel according to any one of claims 1 to 4 and claim 6, characterized in that: The display backplane (10) further comprises a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are connected to the plurality of light-emitting units in a one-to-one correspondence; The plurality of pixel driving circuits include a first pixel driving circuit connected to the first light-emitting unit and a second pixel driving circuit connected to the second light-emitting unit, the first signal line (11a) is electrically connected to the first pixel driving circuit, and the second signal line (11b) is electrically connected to the second pixel driving circuit.

9. A display device, characterized in that: The display device comprises a power supply circuit and a display panel according to any one of claims 1 to 8, wherein the power supply circuit supplies power to the display panel.

10. The display device according to claim 9, characterized in that: The display device further includes a control circuit, which is used to be electrically connected to the display panel according to claim 3 or 4 and is configured to provide the first voltage to the first signal line and provide the second voltage to the second signal line.

11. A mask, characterized in that: A film layer for making a display panel, wherein the display panel is the display panel according to any one of claims 1 to 8; The mask plate comprises a first part (61a) and a second part (61b) connected to each other, wherein the first part (61a) is used to make a film layer in the first area or the second area, and the second part (61b) is used to make a film layer in the splicing area; The sizes of the graphics in the graphic area of ​​the first portion (61a) and the graphics in the graphic area of ​​the second portion (61b) are different.

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