Hardware module for realizing intermediate frequency signal sampling and processing based on FPGA (Field Programmable Gate Array)

Abstract

The utility model discloses a hardware module for realizing intermediate frequency signal sampling and processing based on FPGA, which adopts a radio frequency transformer, an ADC sampling circuit, an FPGA and a clock circuit, the input end of the ADC sampling circuit is connected with the radio frequency transformer, the output end of the ADC sampling circuit is connected with the FPGA, and the clock circuit is respectively connected with the ADC sampling circuit and the FPGA. The FPGA-based hardware module for realizing intermediate frequency signal sampling and processing provided by the embodiment of the utility model can realize high-sensitivity sampling and digital processing of intermediate frequency signals, and supports multiple data communication modes.

Description

Technical Field

[0001] The utility model relates to the field of intermediate frequency signal processing, and in particular discloses a hardware module for implementing intermediate frequency signal sampling and processing based on FPGA. Background Art

[0002] Intermediate frequency signal is a signal obtained by frequency conversion of high frequency signal. It is widely used in fields such as telecommunications and electronics. Due to its strong interference and noise and complex modulation method, the development of its sampling and processing technology is of great significance to improving system performance and reliability. With the continuous development of embedded technology, the intermediate frequency sampling and processing platform based on FPGA technology has become an important tool. However, the existing hardware modules for sampling and processing intermediate frequency signals based on FPGA have low sampling sensitivity and do not support multiple data communication methods.

[0003] Therefore, the existing hardware modules based on FPGA for implementing intermediate frequency signal sampling and processing have low sampling sensitivity and do not support multiple data communication methods, which is a technical problem that needs to be solved urgently. Utility Model Content

[0004] The utility model provides a hardware module for sampling and processing intermediate frequency signals based on FPGA, aiming to solve the technical problems that the existing hardware modules for sampling and processing intermediate frequency signals based on FPGA have low sampling sensitivity and do not support multiple data communication modes.

[0005] The utility model relates to a hardware module for implementing intermediate frequency signal sampling and processing based on FPGA, comprising a radio frequency transformer, an ADC sampling circuit, an FPGA and a clock circuit, wherein the input end of the ADC sampling circuit is connected to the radio frequency transformer, the output end of the ADC sampling circuit is connected to the FPGA, and the clock circuit is respectively connected to the ADC sampling circuit and the FPGA.

[0006] Furthermore, the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes a T-type attenuation circuit, and the output end of the T-type attenuation circuit is connected to the input end of the radio frequency transformer.

[0007] Furthermore, the radio frequency transformer adopts a QSRTC1-1TI radio frequency transformer.

[0008] Furthermore, the ADC sampling circuit includes an ADC sampling chip, and the model of the ADC sampling chip used is CX7442.

[0009] Furthermore, the FPGA adopts the FMQL45T900 chip.

[0010] Furthermore, the clock circuit includes a VCO chip, and the model of the VCO chip is GM4384A.

[0011] Furthermore, the clock circuit includes a clock distributor chip, and the model of the clock distributor chip is CX3E04.

[0012] Furthermore, the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes a power supply module, which is respectively connected to the ADC sampling circuit, FPGA and clock circuit.

[0013] Furthermore, the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes an EMMC module, and the EMMC module is connected to the FPGA.

[0014] Furthermore, the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes DDR particles, and the DDR particles are connected to the FPGA.

[0015] The beneficial effects achieved by the utility model are:

[0016] The utility model provides a hardware module for sampling and processing intermediate frequency signals based on FPGA, which adopts a radio frequency transformer, an ADC sampling circuit, an FPGA and a clock circuit, wherein the input end of the ADC sampling circuit is connected to the radio frequency transformer, the output end of the ADC sampling circuit is connected to the FPGA, and the clock circuit is connected to the ADC sampling circuit and the FPGA respectively. The hardware module for sampling and processing intermediate frequency signals based on FPGA provided in this embodiment can realize high-sensitivity sampling and digital processing of intermediate frequency signals, and support multiple data communication modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a functional block diagram of the first embodiment of the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA in the utility model;

[0018] Figure 2 This is a schematic diagram of module connections of a hardware module for implementing intermediate frequency signal sampling and processing based on FPGA in the utility model;

[0019] Figure 3 This is a functional block diagram of the second embodiment of the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA in the utility model;

[0020] Figure 4 This is a chip connection diagram of the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA in the utility model;

[0021] Figure 5 This is a schematic diagram of the connection between the clock circuit and the FPGA in the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA in the utility model;

[0022] Figure 6This is a connection diagram of the power supply module in the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA in the utility model.

[0023] Description of Figure Numbers:

[0024] 10. RF transformer; 20. ADC sampling circuit; 30. FPGA; 40. Clock circuit; 50. T-type attenuation circuit; 60. Power module. DETAILED DESCRIPTION

[0025] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0026] like Figure 1 and Figure 2 As shown, the first embodiment of the utility model proposes a hardware module for sampling and processing intermediate frequency signals based on FPGA, including a radio frequency transformer 10, an ADC sampling circuit 20, an FPGA 30 and a clock circuit 40, wherein the input end of the ADC sampling circuit 20 is connected to the radio frequency transformer 10, the output end of the ADC sampling circuit 20 is connected to the FPGA 30, and the clock circuit 40 is connected to the ADC sampling circuit 20 and the FPGA 30 respectively. In this embodiment, the radio frequency transformer 10 is used to obtain a differential intermediate frequency signal after coupling and impedance matching of the intermediate frequency signal; the ADC sampling circuit 20 is used to receive the differential intermediate frequency signal output by the radio frequency transformer 10, and is also used to receive the clock signal sent by the clock circuit 40, and convert the differential intermediate frequency signal and the clock signal into digital data; the FPGA 30 is used to implement sampling digital data, processing instructions, executing operations and processing digital data. Further, the model of the FPGA 30 is the FMQL45T900 chip. The radio frequency transformer 10, the ADC sampling circuit 20, the FPGA 30 and the clock circuit 40 can all use existing circuits or functional modules, all within the protection scope of this patent.

[0027] The FPGA30 logic operation center is also the data processing center, which is used to receive data from other parts and analyze and process the received data according to the program setting scheme. It includes: receiving the data sampled by A / D, converting it into 16-bit parallel data and storing it in RAM, and handing the data over to the upper application for processing; analyzing the data instructions received from MCU and performing corresponding data processing according to its instruction requirements.

[0028] The FMQL45T900 chip can sample data, process instructions, execute operations and process data. The ADC sampling chip CX7442 from CityCore Technology is used to sample the input signal. The chip integrates 4-channel ADC, with a maximum sampling rate of up to 750MSPS, a data bit width of 14bit, ENOB (effective number of bits)>=10.7bit@170MHz (500MSPS), a dual-channel digital down-mixer (NCO (numerically controlled oscillator) frequency is continuously variable), a programmable decimation filter (1 / 2 / 4 / 8 / 16 times) and a SerDes (parallel clock) interface (single-channel maximum output bit rate of 15Gbps), and the receiving channel input signal frequency range: 0~1200MHz. The chip can realize 4-channel independent signal input, integrate flexible and configurable digital channels, maximize the user system integration, and reduce the power consumption of the whole machine.

[0029] FMQL45T900 chip, the processor integrates 4 ARM Cortex-A7 cores, the main frequency is 800MHz, the memory data width of PS (Processor System) and PL (Programmable Logic) is 32 bits, and the GTX transceiver is 16X. The PS system integrates a quad-core high-performance processor, bus interconnection, internal memory, external memory interface and peripherals. These peripherals mainly include USB bus interface, Ethernet interface, SD (Secure Digital) / SDIO (Secure Digital Input and Output) interface, I2C (Inter-Integrated Circuit, two-wire serial bus) bus interface, CAN (Controller Area Network) bus interface, UART (Universal Asynchronous Receiver / Transmitter, universal asynchronous receiver / transmitter) interface, GPIO (General-Purpose IO ports, general input / output interface), etc. The PS (Processor System) side can run independently and start under power-on or reset. The PL (Programmable Logic) side has a 4QAUD high-speed transceiver GTX interface.

[0030] Further, see Figures 1 to 6The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA proposed in this embodiment also includes a T-type attenuation circuit 50, and the output end of the T-type attenuation circuit 50 is connected to the input end of the RF transformer 10. The T-type attenuation circuit 50 is used to reduce the signal amplitude and output it to the input end of the RF transformer 10 after attenuation. In this embodiment, the RF transformer 10 adopts a QSRTC1-1TI RF transformer. In this embodiment, the ADC sampling circuit 20 includes an ADC sampling chip, and the model of the ADC sampling chip is CX7442. The clock circuit 40 includes a VCO (voltage-controlled oscillator) chip, and the model of the VCO chip is GM4384A. The clock circuit 40 includes a clock distributor chip, and the model of the clock distributor chip is CX3E04. CX3E04 has a total of 14 clocks and SYNC (synchronization) channels, and each channel can independently configure the division ratio, delay and output mode. Each channel can be independently configured as a CLK (Clock) channel or a SYNC channel. When configured in SYNC output mode, the SYNC signal can be input from the outside or generated by the internal circuit in continuous or pulse mode. The CX3E04 has multi-channel and multi-chip synchronization functions. It can synchronize the chips according to the internal or external input SYNC signal, and ensure that each channel outputs a synchronized clock signal.

[0031] The ADC sampling chip is a fully integrated IF and RF signal processing system chip that integrates high-speed and high-precision 4-channel ADC and a SERDES interface based on the JESD204B subclass 1 standard. The CX7442 includes a 4-channel ADC with a maximum sampling rate of up to 750MSPS, a data bit width of 14bit, ENOB>=10.7bit@170MHz (500MSPS), input frequency, dual-channel digital down-mixer (NCO frequency is continuously variable), programmable decimation filter (1 / 2 / 4 / 8 / 16 times) and SERDES interface (single-channel maximum output bit rate of 15Gbps), and the receiving channel input signal frequency range is: 0~1500MHz. The chip can realize 4-channel independent real signal input and be used as the intermediate frequency processing system of 4 independent RF receivers (maximum instantaneous bandwidth up to 375MHz). It can also realize IQ (in-phase quadrature) complex input and be used as the intermediate frequency processing system of two orthogonal mixing receivers with IQ signal output (such as zero intermediate frequency receiver, in this case the maximum instantaneous bandwidth can be up to 750MHz).

[0032] Preferably, see Figures 1 to 6The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA proposed in this embodiment also includes a power module 60, an EMMC (Embedded Multi Media Card) module and a DDR (Double Data Rate SDRAM) particle. The power module 60 is respectively connected to the ADC sampling circuit 20, the FPGA 30 and the clock circuit 40. The EMMC module is connected to the FPGA 30. The DDR particle is connected to the FPGA 30. In the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA proposed in this embodiment, the power module 60 is all powered by LDO (low dropout regulator) with small ripple.

[0033] like Figures 1 to 6 As shown, the hardware module for implementing intermediate frequency signal sampling and processing based on FPGA provided in this embodiment has the following working principle:

[0034] The intermediate frequency signal is input at the RF connector end, and a T-type attenuation circuit 50 is designed at the front end to reduce the signal amplitude. After attenuation, the signal is output to the PRID pin of the primary coil of Qingshan Technology's RF transformer QSRTC1-1TI. After coupling and impedance matching, a differential intermediate frequency signal is obtained and input to the acquisition pin of the AD converter chip CX7442.

[0035] The VCO (voltage-controlled oscillator) chip GM4384A from Zhenxin Technology is selected as the clock generation chip. Its clock frequency can be generated by the fractional / integer frequency source chip integrated in the VCO of the chip. The output signal frequency range is 50MHz~4GHz. The VCO output signal can be output off-chip through 1 / 2 / 4 / 8 / 16 / 32 / 64 frequency division. Its register is controlled through the FPGA SPI interface to output a pair of 250MHz differential clocks. After receiving the 250MHz differential reference clock, the clock distributor chip CX3E04 also controls its register through the FPGA SPI interface, and extends the output of 1 global differential clock and 2 GTX (Gitabyte Transceiver extended high-speed serial transceiver) differential reference clocks to the FPGA, and also provides 1 differential sampling clock and 1 differential synchronization clock input to the AD converter chip CX7442.

[0036] The receiving part of the AD converter chip CX7442 directly receives the differential intermediate frequency signal and converts it into digital data that can be used by the baseband chip BBP (Baseband processor). CX7442 is a 4ADC chip. The digital channel includes 2 channels, namely channel 0 and channel 1. Each channel includes two digital down-conversion channels ddc0 and ddc1, baseband data interface, etc. CX7442 supports Serdes interface mode and is designed for the JESD204B subclass 1 standard to realize data transmission between the baseband chip BBP. The JESD204 interface protocol is a high-speed serial interface protocol that connects data converters (ADC and DAC) and logic devices (FPGA). The B version of the standard (JESD204B) supports serial data rates up to 12.5Gbps. As high-speed ADCs enter the GSPS range, the preferred interface protocol for data transmission with FPGAs is JESD204B.

[0037] The main power supply of the frequency division source chip GM4384A, the clock distributor chip CX3E04, and the analog-to-digital conversion chip CX7442 are all obtained by 3.3V conversion through LDO. Magnetic beads are added to different power supply ends to reduce the ripple as much as possible.

[0038] The PS processing system of FPGA is the SOC (System on Chip) part of ARM that is unrelated to FPGA. The PL programmable logic is the programmable logic part in FPGA. The PS end inside the chip connects to the various functional modules of PL through the AXI (Advanced Xtensible Interface, a bus protocol) bus to the local bus LB (Local Bus). The PS processing system completes the functions of each module by configuring the registers of each module through LB; the PL part directly uses code to implement electronic circuits, and uses electronic circuits for acquisition and control, which can greatly improve the acquisition frequency and control accuracy. PS belongs to the ARM part, which can process data bare metal or interact with the host computer, and then control it through the PL part, or it can be applied on the operating system. The four groups of SERDES transmission interfaces of the AD converter chip CX7442 are respectively connected to the four groups of GTX reception of FPGA. The center frequency of the AD acquisition intermediate frequency signal is 60MHz, and the sampling rate is 80MHz. Its data interface adopts the JESD204B interface protocol.

[0039] The AD converter chip CX7442 converts the intermediate frequency analog signal into standard JESD204B format data and transmits it to the FPGA. The FPGA internally calls the two IP cores of XILINX official IP-JESD204B and JESD204B_PHY and configures its registers through the LB bus to implement the JESD204B interface protocol, realize its interface function, complete the analysis of the intermediate frequency data, and transmit the parsed data to the upper layer for processing.

[0040] The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA provided in this embodiment, compared with the prior art, adopts a radio frequency transformer, an ADC sampling circuit, an FPGA and a clock circuit, the input end of the ADC sampling circuit is connected to the radio frequency transformer, the output end of the ADC sampling circuit is connected to the FPGA, and the clock circuit is connected to the ADC sampling circuit and the FPGA respectively. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA provided in this embodiment can realize high-sensitivity sampling and digital processing of intermediate frequency signals, and support multiple data communication modes.

[0041] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A hardware module for implementing intermediate frequency signal sampling and processing based on FPGA, characterized in that: The invention comprises a radio frequency transformer (10), an ADC sampling circuit (20), an FPGA (30) and a clock circuit (40), wherein the input end of the ADC sampling circuit (20) is connected to the radio frequency transformer (10), the output end of the ADC sampling circuit (20) is connected to the FPGA (30), and the clock circuit (40) is connected to the ADC sampling circuit (20) and the FPGA (30) respectively.

2. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 1, characterized in that: The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA further comprises a T-type attenuation circuit (50), the output end of the T-type attenuation circuit (50) being connected to the input end of the radio frequency transformer (10).

3. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 2, characterized in that: The radio frequency transformer (10) adopts a QSRTC1-1TI radio frequency transformer.

4. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 2, characterized in that: The ADC sampling circuit (20) comprises an ADC sampling chip, and the model of the ADC sampling chip is CX7442.

5. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 2, characterized in that: The model of the FPGA (30) is FMQL45T900 chip.

6. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 2, characterized in that: The clock circuit (40) comprises a VCO chip, and the model of the VCO chip is GM4384A.

7. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 6, characterized in that: The clock circuit (40) comprises a clock distributor chip, and the model of the clock distributor chip is CX3E04.

8. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 2, characterized in that: The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes a power supply module (60), and the power supply module (60) is respectively connected to the ADC sampling circuit (20), the FPGA (30) and the clock circuit (40).

9. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 2, characterized in that: The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes an EMMC module, and the EMMC module is connected to the FPGA (30).

10. The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA as claimed in claim 9, characterized in that: The hardware module for implementing intermediate frequency signal sampling and processing based on FPGA also includes DDR particles, and the DDR particles are connected to the FPGA (30).

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