Semiconductor device, power electronic apparatus, and vehicle

Abstract

The utility model discloses a semiconductor device, power electronic equipment and a vehicle, and the semiconductor device comprises a substrate of a first conductive type; the collector electrode structure is positioned on the back surface of the substrate; the collector structure comprises a second conductive type heavily-doped first collector region and a second conductive type heavily-doped second collector region, the first conductive type heavily doped second collector region is positioned on the side surface of the first collector region along a first direction parallel to the substrate; the third collector region is located on the side face of the first collector region in the first direction and located on the side, close to the substrate, of the second collector region. The device provided by the utility model realizes rapid extraction of electrons when the device is turned off reversely, inhibits minority carrier injection of a collector, shortens turn-off time, and reduces turn-off loss.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device, a power electronic device and a vehicle. Background Art

[0002] In the related technology, for some semiconductor devices such as bipolar power devices such as IGBT (Insulate-Gate Bipolar Transistor), during high-frequency operation, the participation of minority carriers not only brings about the conductivity modulation effect but also brings about inevitable switching losses. When the device is turned off, minority carriers are injected into the collector, prolonging the turn-off time and causing turn-off losses. Utility Model Content

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a semiconductor device that can quickly extract electrons when the device is reversely turned off, suppress collector minority carrier injection, shorten the turn-off time, and reduce the turn-off loss.

[0004] The second objective of the present invention is to provide a power electronic device.

[0005] The third objective of the present invention is to provide a vehicle.

[0006] In order to achieve the above-mentioned purpose, the semiconductor device of the embodiment of the first aspect of the utility model includes: a substrate of a first conductive type; a collector structure, the collector structure is located on the back side of the substrate; the collector structure includes: a first collector region heavily doped with a second conductive type; a second collector region heavily doped with the first conductive type, the second collector region is located on the side of the first collector region along a first direction parallel to the substrate; a third collector region lightly doped with the second conductive type, the third collector region is located on the side of the first collector region along the first direction and on the side of the second collector region close to the substrate along a second direction perpendicular to the substrate.

[0007] According to the semiconductor device of the embodiment of the utility model, the collector structure is separated into three collector regions, wherein the first collector region of the second conductivity type is retained to achieve normal device conduction, and the second collector region of the first conductivity type and the third collector region of the second conductivity type are set, so that the substrate of the first conductivity type, the third collector region and the second collector region constitute a transistor structure, and when the device is reversely turned off, the transistor structure can be turned on, so that electrons can be quickly extracted, the collector minority carrier injection is suppressed, the turn-off time is shortened, and the turn-off loss is reduced.

[0008] In some embodiments, the second collector region includes: a first collector region and a second collector region, wherein the first collector region and the second collector region are located at two sides of the first collector region along the first direction.

[0009] In some embodiments, the third collector region includes: a third collector region and a fourth collector region, the third collector region and the fourth collector region are distributed on both sides of the first collector region along the first direction, the third collector region is located on a side of the first collector region close to the substrate, and the fourth collector region is located on a side of the second collector region close to the substrate.

[0010] In some embodiments, in a second direction perpendicular to the substrate, a side of the first collector region in contact with the back side of the substrate is closer to the front side of the substrate than a surface of the collector region, wherein the surface of the collector region is a side of the third collector region or the fourth collector region in contact with the back side of the substrate.

[0011] In some embodiments, the collector structure further includes: a collector, wherein the collector is located on a side of the first collector region away from the third collector region, a side of the first collector region away from the substrate, and a side of the second collector region away from the fourth collector region.

[0012] In some embodiments, the semiconductor device further includes: a drift layer lightly doped with a first conductivity type, the drift layer being located on the front side of the substrate; and a current spreading layer of the first conductivity type, the current spreading layer being located on a side of the drift layer away from the substrate along a second direction perpendicular to the substrate.

[0013] In some embodiments, the semiconductor device further includes: a trench gate structure, the trench gate structure including a gate trench, a gate oxide layer, a first gate and a second gate; wherein the gate trench extends along the second direction and penetrates the current spreading layer, and the bottom of the gate trench extends into the drift layer; the gate oxide layer is located in the gate trench and isolates the first gate and the second gate; the first gate and the second gate are both located in the gate trench and arranged along the second direction.

[0014] In some embodiments, a length of the second gate along the second direction is less than a length of the first gate along the second direction.

[0015] In some embodiments, the semiconductor device further includes: a first well region of a second conductivity type, the first well region being located at one side of the trench gate structure in the first direction and on a side of the current spreading layer away from the drift layer along the second direction.

[0016] In some embodiments, the semiconductor device further includes: a first emitter region heavily doped with the first conductivity type and a second emitter region heavily doped with the second conductivity type, wherein in the second direction, the first emitter region and the second emitter region are both located on a side of the first well region away from the current spreading layer, and in the first direction, the first emitter region and the second emitter region are in contact with each other.

[0017] In some embodiments, the semiconductor device also includes: an emission trench structure, which extends along the second direction and penetrates the current expansion layer, and the bottom of the emission trench structure extends into the drift layer; a floating well region of the second conductivity type is formed between the emission trench structure and the trench gate structure along the first direction, and the floating well region is located on a side of the current expansion layer away from the drift layer in the second direction.

[0018] In some embodiments, the emitter trench structure includes: an emitter trench, which extends along the second direction and penetrates the current spreading layer, and the bottom of the emitter trench structure extends into the drift layer; an emitter polysilicon, which is located in the emitter trench; and a first insulating layer, which is located between the inner wall of the emitter trench and the emitter polysilicon.

[0019] In some embodiments, the semiconductor device further includes: a second insulating layer, wherein the second insulating layer covers the emission trench structure, the floating well region, and the trench gate structure along the second direction.

[0020] In some embodiments, the semiconductor device further includes: a first emitting electrode, the first emitting electrode covers the first emitting region and the second emitting region in the second direction, and one end of the first emitting electrode contacts one end of the second insulating layer.

[0021] In some embodiments, the semiconductor device further includes: a second well region of a second conductivity type, the second well region being located on a side of the trench gate structure away from the first well region in the first direction and on a side of the current diffusion layer away from the drift layer.

[0022] In some embodiments, the semiconductor device further includes: a third emitter region heavily doped with the first conductivity type and a fourth emitter region heavily doped with the second conductivity type, wherein in the second direction, the third emitter region and the fourth emitter region are both located on a side of the second well region away from the current spreading layer, and in the first direction, the third emitter region and the fourth emitter region are in contact with each other.

[0023] In some embodiments, the semiconductor device further includes: a second emitter electrode, the second emitter electrode covering the first emitter region, the second emitter region, the trench gate structure, the third emitter region, and the fourth emitter region in the second direction.

[0024] In order to achieve the above object, a power electronic device according to a second aspect of the present invention includes at least one semiconductor device as described in the above embodiment.

[0025] According to the power electronic equipment of the embodiment of the utility model, by adopting the semiconductor device described in the above embodiment, it is possible to quickly extract electrons when the device is reversely turned off, suppress collector minority carrier injection, shorten the turn-off time, and reduce the turn-off loss.

[0026] In order to achieve the above-mentioned object, a vehicle according to an embodiment of the third aspect of the utility model comprises the power electronic device described in the above embodiment.

[0027] The vehicle according to the embodiment of the utility model, by adopting the power electronic device described in the above embodiment, can realize the rapid extraction of electrons when the device is reversely turned off, suppress the collector minority carrier injection, shorten the turn-off time, reduce the turn-off loss, and thus improve the overall performance of the vehicle.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the utility model;

[0031] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the utility model;

[0032] Figure 3 It is a schematic diagram of forming a drift layer, a first collector region and a third collector region according to an embodiment of the utility model;

[0033] Figure 4 is a schematic diagram of forming a current spreading layer according to an embodiment of the utility model;

[0034] Figure 5 is a schematic diagram of forming a first well region according to an embodiment of the utility model;

[0035] Figure 6is a schematic diagram of forming a second emission area according to an embodiment of the utility model;

[0036] Figure 7 is a schematic diagram of forming a first emission area according to an embodiment of the utility model;

[0037] Figure 8 is a schematic diagram of forming a gate trench according to an embodiment of the utility model;

[0038] Fig. 9 is a schematic diagram of forming a gate oxide layer according to an embodiment of the utility model;

[0039] Fig.10 is a schematic diagram of forming a first gate and a second gate according to an embodiment of the utility model;

[0040] Fig.11 is a schematic diagram of forming a second insulating layer according to an embodiment of the utility model;

[0041] Fig.12 is a schematic diagram of forming a first emitting electrode according to an embodiment of the utility model;

[0042] Fig.13 is a block diagram of a power electronic device according to an embodiment of the utility model;

[0043] Fig.14 is a block diagram of a vehicle according to an embodiment of the present utility model.

[0044] Reference numerals:

[0045] Vehicle 100;

[0046] Power Electronics 101;

[0047] Semiconductor device 1;

[0048] Substrate 10; collector structure 20; drift layer 30; current spreading layer 40; first well region 50; first emitter region 60; second emitter region 70; floating well region 80; first emitter electrode 90;

[0049] First collector region 21; second collector region 22; third collector region 23; collector electrode 24; gate trench 41; gate oxide layer 42; first gate 43; second gate 44; emitter trench 45; emitter polysilicon 46; first insulating layer 47; second insulating layer 48; second well region 51; third emitter region 81; fourth emitter region 82; second emitter electrode 91;

[0050] The first electron collection region 221; the second electron collection region 222; the third electron collection region 231; and the fourth electron collection region 232. DETAILED DESCRIPTION

[0051] The embodiments of the present utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present utility model are described in detail below.

[0052] Reference below Figure 1-Figure 11 A semiconductor device according to an embodiment of the present invention is described.

[0053] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the utility model, such as Figure 1 As shown, the semiconductor device 1 includes: a substrate 10 of a first conductivity type and a collector structure 20 .

[0054] The first conductivity type generally refers to the dominant electron type in the semiconductor device 1, which can be N-type (electrons are the main carriers) or P-type (holes are the main carriers), depending on the doping type of the material. Figure 1 As shown, the substrate 10 of the first conductivity type may be an N-type substrate 10 , and the N-type substrate 10 may refer to a base layer in the semiconductor device 1 , and its conductivity type is N-type.

[0055] In some embodiments, the substrate 10 of the semiconductor device 1 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or other composite materials as semiconductor materials. Taking a semiconductor device in which the substrate 10 is made of Si as an example, the doping concentration of the first conductive type substrate 10 may be , preferably ; The thickness can be 40-60μm, preferably 40-50μm.

[0056] In some embodiments, the collector structure 20 may refer to a structure for collecting charge carriers (electrons or holes) in the semiconductor device 1. The collector structure 20 is located on the back side of the substrate 10, which helps to optimize the current flow path, form a suitable electric field distribution and current path in the device, reduce the resistance of the device, and improve the current transmission efficiency, thereby achieving better performance and controlling the on and off states of the device.

[0057] like Figure 1 As shown, the collector structure 20 of the embodiment of the utility model includes: a first collector region 21 heavily doped with the second conductivity type, a second collector region 22 heavily doped with the first conductivity type, and a third collector region 23 lightly doped with the second conductivity type.

[0058] The second conductivity type is a type different from the first conductivity type, for example, if the first conductivity type is N-type, the second conductivity type is P-type, and if the first conductivity type is P-type, the second conductivity type is N-type. Heavily doped may mean that a large amount of impurities are introduced into the region, which may increase the carrier concentration in the region, thereby changing the conductive properties of the semiconductor device 1.

[0059] For example, the second conductivity type heavy doping may refer to P-type heavy doping. Therefore, the second conductivity type heavily doped first collector region 21 may refer to increasing the hole concentration in the P-type semiconductor material by doping a high concentration of impurities (usually trivalent elements such as boron, indium or gallium) into the P-type semiconductor material, thereby forming a highly doped region to improve the efficiency of minority carrier injection into the region, that is, to quickly inject minority carriers when the device is in the on state, thereby enhancing the conductivity in the on state.

[0060] In some embodiments, in the semiconductor device 1, the second conductive type heavily doped first collector region 21 may be formed by ion implantation, the doping ions may preferably be B (boron) ions, and the doping concentration of the second conductive type heavily doped first collector region 21 may be , preferably The thickness requirement of the second conductivity type heavily doped first collector region 21 can be determined according to the thickness of the second conductivity type lightly doped third collector region 23 , the first conductivity type heavily doped second collector region 22 , and the first conductivity type substrate 10 .

[0061] In some embodiments, minority carriers may refer to carriers in the semiconductor device 1 (eg, IGBT), and may be electrons or holes.

[0062] In some embodiments, the first conductive type heavily doped may refer to N-type heavily doped. For example, the first conductive type heavily doped second collector region 22, i.e., the N-type heavily doped second collector region 22, may refer to a highly doped region formed by doping a high concentration of impurities (usually pentavalent elements, such as phosphorus, arsenic, or antimony) into an N-type semiconductor material to increase the electron concentration in the N-type semiconductor material, thereby improving the efficiency of current flow and conductivity.

[0063] In some embodiments, the second collector region 22 heavily doped with the first conductivity type may be formed by chemical vapor deposition, and the selection of doping concentration and thickness affects the conductivity of the region. The doping ions may preferably be P (phosphorus) ions, and the doping concentration of the second collector region 22 heavily doped with the first conductivity type may be , preferably The thickness may be 0.1-0.5 μm, preferably 0.2-0.3 μm.

[0064] In some embodiments, the second conductivity type light doping may refer to P-type light doping. Light doping may mean that relatively few impurities are introduced into the region to maintain a low carrier concentration. For example, the second conductivity type lightly doped third collector region 23 may refer to the addition of low concentrations of impurities (usually trivalent elements such as boron, indium or gallium) into the P-type semiconductor material to reduce the hole concentration in the P-type semiconductor material, which helps the semiconductor device 1 to quickly extract minority carriers when in the off state.

[0065] In some embodiments, the third collector region 23 lightly doped with the second conductivity type may be formed in a chemical vapor deposition process, and the selection of doping concentration and thickness affects the electrical properties and structure of the region. The doping ions may preferably be B (boron) ions, and the doping concentration of the third collector region 23 lightly doped with the second conductivity type may be , preferably The thickness may be 0.5-2 μm, preferably 0.5-1 μm.

[0066] like Figure 1 As shown, the second collector region 22 is located on the side of the first collector region 21 along a first direction parallel to the substrate 10; the third collector region 23 is located on the side of the first collector region 21 along the first direction and is located on the side of the second collector region 22 close to the substrate 10 along a second direction perpendicular to the substrate. In this way, the substrate 10, the third collector region 23 and the second collector region 22 can form a transistor structure such as an NPN or PNP structure.

[0067] Specifically, taking the first conductivity type as N type as an example, the substrate 10, the third collector region 23 and the second collector region 22 form an NPN transistor. When the device is forward-conducting, the injected electrons are transmitted through the first collector region, and at this time the NPN transistor is in the cut-off state, achieving normal conduction. When the device is reversely turned off, when the minority carriers flowing through the first collector region 21 reach the NPN transistor conduction threshold, the NPN transistor is turned on, and electrons can be quickly extracted, suppressing the collector minority carrier injection, shortening the turn-off time, and reducing the turn-off loss.

[0068] According to the semiconductor device 1 of the embodiment of the utility model, the collector structure 20 is separated into three collector regions, wherein the first collector region 21 of the second conductivity type is retained to achieve normal device conduction, and the second collector region 22 of the first conductivity type and the third collector region 23 of the second conductivity type are arranged, so that the first conductivity type substrate 10, the third collector region 23 and the second collector region 22 constitute a transistor structure, and when the device is reversely turned off, the transistor structure can be turned on, so that electrons can be quickly extracted, collector minority carrier injection is suppressed, the turn-off time is shortened, and the turn-off loss is reduced.

[0069] like Figure 1As shown, the second collector region 22 includes: a first collector region 221 and a second collector region 222. The first collector region 221 and the second collector region 222 are located at two sides of the first collector region 21 along the first direction.

[0070] like Figure 1 As shown, the third collector region 23 includes: a third collector region 231 and a fourth collector region 232. The third collector region 231 and the fourth collector region 232 are distributed on both sides of the first collector region 21 along the first direction, the third collector region 231 is located on the side of the first collector region 221 close to the substrate 10, and the fourth collector region 232 is located on the side of the second collector region 222 close to the substrate 10.

[0071] Specifically, Figure 1 As shown, the substrate 10, the third collector region 231 and the first collector region 221 form a transistor structure, and the substrate 10, the fourth collector region 232 and the second collector region 222 also form a transistor structure. When the device is reversely turned off, the transistor structure formed above is turned on, which can quickly extract electrons, shorten the turn-off time, and reduce the turn-off loss.

[0072] In some embodiments, in the second direction perpendicular to the substrate 10, the side of the first collector region 21 in contact with the back of the substrate 10 is closer to the front of the substrate 10 than the surface of the collector region, wherein the surface of the collector region is the side of the third collector region 231 or the fourth collector region 232 in contact with the back of the substrate 10. This layout design can increase the contact area between the first collector region 21 and the substrate 10, thereby compensating for the effect on the minority carrier injection efficiency caused by the reduction of the first collector region 21 area, and improving the efficiency of minority carrier injection during forward conduction. It can be ensured that when the device is forward-conducted, the first collector region.

[0073] like Figure 1 As shown, the collector structure also includes a collector 24. The collector 24 is usually composed of a metal layer for transmitting current. Metal materials have good electrical conductivity and current transmission properties, and therefore can be used as the material of the collector 24, such as silver / aluminum / titanium / nickel alloys, or any desired metal or metal alloy that forms an ohmic contact with the second collector region 22 and the first collector region 21. Preferably, the thickness of the collector 24 may be 1-2 μm. In semiconductor devices, especially in devices such as transistors, a metal collector may be connected to a specific area of ​​the semiconductor material in order to effectively collect charge carriers and transmit current.

[0074] In some embodiments, the collector 24 is located on a side of the first collector region 221 away from the third collector region 231, a side of the first collector region 21 away from the substrate 10, and a side of the second collector region 222 away from the fourth collector region 232. The layout design of the collector 24 can ensure current transmission.

[0075] like Figure 1 As shown, the semiconductor device 1 further includes: a drift layer 30 lightly doped with a first conductivity type and a current spreading layer 40 of a first conductivity type.

[0076] In some embodiments, the first conductive type lightly doped drift layer 30 may refer to a channel layer into which relatively less N-type doping substances are introduced, and is located on the front side of the substrate 10. The main function of the drift layer 30 in the semiconductor device 1 may be to provide a drift channel for electrons so that they can be freely transmitted in the device. The lightly doped characteristic makes the electron concentration in the drift layer 30 relatively low, thereby forming a region where the electron concentration gradually changes, which helps to reduce the resistance of current transmission and improve the conductivity of the drift layer 30.

[0077] In some embodiments, the first conductive type lightly doped drift layer 30 may be formed by chemical vapor deposition, and the doping ions may preferably be P (phosphorus) ions. The selection of doping concentration and thickness affects the electrical properties and structure of the region. The doping concentration may be , preferably The thickness can be 70-90 μm, preferably 75-85 μm.

[0078] In some embodiments, the current spreading layer 40 of the first conductivity type is located on the side of the drift layer 30 away from the substrate 10 along the second direction perpendicular to the substrate 10. The introduction of the current spreading layer 40 in the front structure, combined with the structure 20 of the partitioned collector, can avoid the reduction of minority carriers during forward conduction due to the reduction of the area of ​​the first collector region 21, thereby affecting the conductivity modulation effect. When the device is forward-conducted, the current spreading layer 40 is equivalent to forming a barrier layer, which can keep the minority carriers in the drift layer 30, enhance the conductivity modulation effect, reduce the on-state voltage drop, and thus better compromise the relationship between the on-state voltage drop and the turn-off loss.

[0079] In some embodiments, the doping concentration of the current spreading layer 40 may be , preferably The doping ions are preferably P (phosphorus) ions, with a depth of 8-10μm.

[0080] like Figure 1 As shown, the semiconductor device 1 also includes a trench gate structure. The trench gate structure may refer to an electrode structure that forms a trench or depression at the bottom of the gate to reduce the contact area between the gate and the semiconductor surface, thereby forming a trench-shaped structure. The trench gate structure may include a gate trench 41, a gate oxide layer 42, a first gate 43, and a second gate 44.

[0081] The gate trench 41 extends along the second direction and penetrates the current spreading layer 40, and the bottom of the gate trench 41 extends into the drift layer 30. The existence of the gate trench 41 helps to locate and isolate the gate oxide layer 42 and the gate, thereby achieving more precise electric field control. The gate oxide layer 42 may be an oxide layer formed in the gate trench 41, which is used to isolate the first gate 43 and the second gate 44, ensuring that there is no electrical contact between them, thereby preventing current short circuit. The material of the gate oxide layer 42 is generally an insulating material such as silicon dioxide.

[0082] In some embodiments, the thickness of the gate oxide layer 42 can be in the range of 50-60nm. If the thickness of the gate oxide layer 42 is too thin, it is easy to cause breakdown. If the thickness of the gate oxide layer 42 is too thick, it is easy to cause the threshold voltage of the device to increase. Therefore, the gate oxide layer 42 can be manufactured within a reasonable thickness range.

[0083] In some embodiments, the first gate 43 may be an electrode in a trench gate structure, typically made of a conductive material, such as polysilicon. The second gate 44 is another electrode in the trench gate structure, such as a bottom split electrode, and the design of the second gate 44 may affect the electric field distribution and current control, thereby helping to optimize the performance of the device. The first gate 43 and the second gate 44 are both located in the gate trench 41 and arranged along the second direction, which may achieve better electric field control, current modulation, and conductivity regulation.

[0084] In some embodiments, the trench gate structure adopts a split gate structure to reduce the capacitance between the gate and the substrate 10, that is, the Miller capacitance. This helps to reduce the charging and discharging time of the current and improve the response speed of the device, which is of great significance in high-frequency applications. In addition, in the traditional planar gate structure, since the current passes through the area between the gate and the substrate 10, it is easy to generate the concentration phenomenon of the electric field. The trench gate structure can extend the gate trench 41 into the drift layer 30 and adopt a split gate structure. Such a design slows down the concentration of the electric field at the bottom of the gate and helps to improve the stability of the device.

[0085] In some embodiments, the length of the second gate 44 along the second direction is less than the length of the first gate 43 along the second direction, so as to reduce the concentration of the electric field at the bottom of the gate while ensuring the front side conduction of the device, thereby preventing breakdown.

[0086] like Figure 1As shown, the semiconductor device 1 also includes a first well region 50 of a second conductivity type, i.e., a P-type well region. The carriers therein are mainly positive charges (holes). In this case, the P-type well region can be formed by introducing impurities (usually trivalent elements, such as boron) into the semiconductor material, thereby increasing the concentration of positive charges. The first well region 50 is located on one side of the trench gate structure in the first direction and on the side of the current extension layer 40 away from the drift layer 30 along the second direction. Such an arrangement design can be used to modulate the electric field distribution, affect the injection and extraction of carriers, so that the device can more effectively control the current in both the on and off states. In addition, this arrangement can also be related to factors such as electric field distribution and carrier diffusion to better meet the performance requirements of the device.

[0087] like Figure 1 As shown, the semiconductor device 1 also includes: a first emitter region 60 heavily doped with a first conductivity type and a second emitter region 70 heavily doped with a second conductivity type. The first emitter region 60 can be heavily doped to increase the concentration of electrons in the region. For example, this can be achieved by introducing a high concentration of impurities (such as pentavalent elements such as phosphorus, arsenic or antimony) into an N-type semiconductor material. The second emitter region 70 can be heavily doped to increase the concentration of holes in the region. Specifically, this can be achieved by introducing a high concentration of trivalent elements (such as boron, indium or gallium) into a P-type semiconductor material. In the second direction, the first emitter region 60 and the second emitter region 70 are both located on the side of the first well region 50 away from the current spreading layer 40, and in the first direction, the first emitter region 60 and the second emitter region 70 are in contact with each other.

[0088] In some embodiments, the doping ions of the first conductive type heavily doped first emitter region 60 may be As (arsenic) ions, and the doping concentration may be The depth of the first emitter region 60 may be 0.2-0.5 μm, preferably 0.5 μm. The doping ions of the second emitter region 70 heavily doped with the second conductivity type may be B (boron) ions, and the doping concentration may be The depth of the second emission region 70 may be 0.2-0.5 μm, preferably 0.5 μm.

[0089] For example Figure 1 As shown, the semiconductor device 1 further includes an emission groove structure. The emission groove structure may be a groove or groove-shaped design, the emission groove structure extends along the second direction and penetrates the current extension layer 40, and the bottom of the emission groove structure extends into the drift layer 30. The introduction of the emission groove structure can better distribute the current, reduce the local current density, expand the safe operating area, reduce the probability of breakdown, and thus improve the stability of the device.

[0090] In some embodiments, a floating well region 80 of the second conductivity type is formed between the emitting groove structure and the groove gate structure along the first direction. The floating well region 80 may refer to a region with a specific electronic energy level structure introduced in the device, in which the selection of impurity concentration and type may affect the behavior of carriers. Here, the floating well region 80 is of the second conductivity type. In the second direction, the floating well region 80 is located on the side of the current extension layer 40 away from the drift layer 30. The introduction of the floating well region 80 helps to adjust the electric field distribution, reduces the current density in the device, and thus improves the short-circuit safe operating area of ​​the device. In addition, the introduction of the floating well region 80 can also adjust the carrier concentration distribution of the drift layer 30, which helps to optimize the movement of carriers in the drift layer 30, improve the conductivity in the on state, and thus improve the working performance of the device.

[0091] In some embodiments, the doping ions of the second conductivity type floating well region 80 may be B (boron) ions, which may be formed simultaneously by boron ion implantation. The doping concentration may be , preferably , with a depth of 5-8μm.

[0092] In some embodiments, the emission trench structure includes: an emission trench 45, an emitter polysilicon 46, and a first insulating layer 47. The emission trench 45 extends along the second direction and penetrates the current spreading layer 40, and the bottom of the emission trench structure extends into the drift layer 30. The emission trench 45 helps to improve the current distribution and reduce the current density to improve the device performance.

[0093] In some embodiments, the emitter polysilicon 46 may refer to a portion or the whole of the emitter being composed of polysilicon. Polysilicon generally has good electrical conductivity and stability and is suitable for use as an electrode material in the semiconductor device 1. The emitter polysilicon 46 is located in the emitter trench 45 and can be used as a current injection source in the emitter trench structure, that is, a source for providing electron injection or a ground for receiving electrons to achieve control of current.

[0094] In some embodiments, the first insulating layer 47 may be an insulating oxide layer, and may be made of silicon nitride, silicon oxide, aluminum oxide or other insulating materials, and the specific material selection depends on the application requirements and the preparation process. The first insulating layer 47 is located between the inner wall of the emitter trench 45 and the emitter polysilicon 46, and is used to isolate the emitter polysilicon 46 in the emitter trench 45 to prevent accidental leakage or short circuit of current, thereby improving the safety and reliability of the device.

[0095] like Figure 1As shown, the semiconductor device 1 further includes a second insulating layer 48. The second insulating layer 48 covers the emission trench 45 structure, the floating well region 80 and the trench gate structure along the second direction. The second insulating layer 48 can provide good insulation isolation between different regions of the device, prevent unnecessary diffusion of charge or current, and thus improve the stability and reliability of the device.

[0096] In some embodiments, the second insulating layer 48 may be made of materials such as silicon oxide, silicon nitride or boron phosphorus silicon glass (BPSG) as an insulating dielectric layer, and the height of the upper surface of the insulating dielectric layer is higher than the upper surface of other materials. Such a design may be used to form an insulating layer in the device structure to isolate different electronic components or structures and ensure that there is no electrical or electromagnetic interference between them.

[0097] For example Figure 1 As shown, the semiconductor device 1 further includes a first emitter electrode 90, which is generally an electrode for controlling or guiding the current of the emitter region in the semiconductor device 1. In an embodiment, the first emitter electrode 90 may be an ohmic contact electrode, that is, an electrode that forms a good ohmic contact with the semiconductor material. The first emitter electrode 90 covers the first emitter region 60 and the second emitter region 70 in the second direction, and one end of the first emitter electrode 90 contacts one end of the second insulating layer 48.

[0098] In some embodiments, the first emitter electrode 90 can be made by high temperature annealing of metal, for example, silver, aluminum, titanium, nickel alloy, etc., and any desired metal or metal alloy that can form an ohmic contact with the first conductive type heavily doped first emitter region 60 can also be selected according to actual needs. The thickness of the first emitter electrode 90 can be 2-10 μm.

[0099] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention, such as Figure 2 As shown, the semiconductor device 1 also includes a second well region 51 of the second conductivity type. The second well region 51 generally refers to a region where a second conductivity type material is introduced into the semiconductor device 1, and this region can be formed by ion implantation or other doping techniques. The introduction of the second conductivity type material can change the local charge carrier type, thereby adjusting the electrical characteristics of the device. The second well region 51 is located on the side of the trench gate structure away from the first well region 50 in the first direction and on the side of the current diffusion layer away from the drift layer 30, which helps to form a more favorable current path in the device. This layout can improve the on- and off-performance of the device by affecting processes such as electric field distribution, carrier injection and extraction.

[0100] like Figure 2As shown, the semiconductor device 1 further includes: a third emitter region 81 heavily doped with the first conductivity type and a fourth emitter region 82 heavily doped with the second conductivity type. The third emitter region 81 can enhance its conductivity by introducing a high concentration of the first conductivity type doping. The fourth emitter region 82 can enhance its conductivity by introducing a high concentration of the second conductivity type doping. In the second direction, the third emitter region 81 and the fourth emitter region 82 are both located on a side of the second well region 51 away from the current spreading layer 40, and in the first direction, the third emitter region 81 and the fourth emitter region 82 are in contact.

[0101] For example Figure 2 As shown, the semiconductor device 1 further includes a second emitter electrode 91. The second emitter electrode 91 covers the first emitter region 60, the second emitter region 70, the trench gate structure, the third emitter region 81 and the fourth emitter region 82 in the second direction. The coverage of the second emitter electrode 91 on multiple emission regions helps to control the injection and extraction of current. By introducing current on multiple regions, the injection and extraction positions of electrons can be more accurately controlled. In addition, the coverage design of the second emitter electrode 91 also helps to improve the uniformity of the current and avoid the concentration of current in a local area, thereby improving the overall performance of the device.

[0102] In some embodiments, the second emitting electrode 91 may be a structure composed of multiple layers of metal or metal alloy, and these metal layers may include but are not limited to silver / aluminum / titanium / nickel alloy, etc. In addition, the electrical properties of the electrode can be adjusted by controlling the thickness and combination of each metal layer to meet the needs of specific applications.

[0103] As Figure 1 As an example, the semiconductor device structure shown below Figure 3-Figure 11 The process flow of the semiconductor device of the embodiment of the utility model is described. The process flow of the semiconductor device 1 may include the following steps:

[0104] First, at a doping concentration of The crystal surface of the first conductive type substrate 10 is epitaxially grown by chemical vapor deposition with a first conductive type doping concentration of The drift layer 30 is formed by a plurality of channels.

[0105] Second, after the substrate 10 is turned over, a second conductive type doping concentration of 10 is epitaxially grown on the back side of the substrate 10 by chemical vapor deposition. The third collector region 23 is epitaxially grown with a second conductivity type doping concentration of The second collector region 22 has a structure such as Figure 3 shown.

[0106] Third, phosphorus ions with different energies and doses are implanted into the surface layer of the drift layer 30 to form a current spreading layer 40 of the first conductivity type, with a doping concentration of , with a depth of 10 μm, the resulting structure is as follows Figure 4 shown.

[0107] Fourth, multiple injections of boron ions with different energies and different doses are performed to form a first well region 50 of the second conductivity type, with a doping concentration of , with a thickness of 3 μm, the resulting structure is as follows Figure 5 shown.

[0108] Fifth, boron ion implantation with different energies and different doses is performed multiple times into the surface area of ​​the first well region 50 to form a second emitter region 70 heavily doped with the second conductivity type, with a doping concentration of , with a depth of 0.5 μm, the resulting structure is as follows Figure 6 shown.

[0109] Sixth, arsenic ions with different energies and different doses are implanted into the surface area of ​​the first well region 50 for multiple times to form a first emitter region 60 heavily doped with the first conductivity type, with a doping concentration of , with a depth of 0.5 μm, wherein the first emission region 60 and the second emission region 70 are in contact with each other, and the resulting structure is as follows Figure 7 shown.

[0110] Seventh, the gate trench 41 and the emitter trench 45 are formed by reactive ion etching or chemical etching. Boron ions with different energies and different doses are injected multiple times to form a floating well region 80. The resulting structure is as follows: Figure 8 shown.

[0111] Eighth, a 50 nm thick gate oxide layer 42 is formed on the inner wall of the gate trench 41 by thermal oxidation. The resulting structure is as follows: Fig. 9 shown.

[0112] Ninth, polysilicon is deposited on the surface of the gate oxide layer 42 by low pressure chemical vapor deposition. The gate with a split gate structure should first be deposited to form the second gate 44. Then, the dielectric layer is thermally oxidized and then deposited to form the first gate 43. The resulting structure is as follows: Fig.10 shown.

[0113] Tenth, borophosphosilicate glass is deposited to form a second insulating layer 48. The resulting structure is as follows: Fig.11 shown.

[0114] Eleventh, sputtering silver / nickel / titanium / aluminum alloy as the ohmic contact metal layer of the first emitting electrode 90, so that it covers the upper surface of the first emitting region 60, the metal layer and the second emitting region 70 and the first emitting region 60 form an ohmic contact electrode, that is, the first emitting electrode 90, the resulting structure is as follows Fig.12 shown.

[0115] Twelfth, the first conductive type substrate 10 is removed by chemical mechanical polishing, a metal titanium / aluminum alloy is sputtered on the back surface, a collector electrode 24 is formed on the lower surface of the third collector region 23, and laser annealing is performed to make a back ohmic contact. The obtained structure is as follows: Figure 1 shown.

[0116] In some embodiments, the specific parameters of the high temperature annealing during the manufacturing process are not limited and can be selected according to actual needs. The temperature of the high temperature annealing is generally greater than 800° C. The annealing temperature can be 1600-1700° C.

[0117] In some embodiments, the present invention does not limit the method for forming the metal layer, and the metal layer can be made by evaporation, sputtering and other processes.

[0118] In some embodiments, Figure 2 The process flow of the semiconductor device is similar to the above process, except that the floating well region 80 is not provided, which will not be described in detail here.

[0119] Reference below Fig.13 A power electronic device according to an embodiment of the present invention is described.

[0120] Fig.13 is a block diagram of a power electronic device according to an embodiment of the utility model, such as Fig.13 As shown, the power electronic device 101 includes at least one semiconductor device 1 as described in the above embodiments.

[0121] In some embodiments, the power electronic device 101 of the embodiment of the utility model can be a power electronic device, such as an inverter, a rectifier, a frequency converter, an electric drive system, an electric vehicle controller, etc. These power electronic devices 101 are used to process high-power electrical signals and achieve effective power conversion. By integrating the semiconductor device 1, the power electronic device 101 can achieve efficient and reliable power circuit control to meet the requirements of various application fields.

[0122] According to the power electronic device 101 of the embodiment of the utility model, by adopting the semiconductor device 1 described in the above embodiment, it is possible to quickly extract electrons when the device is reversely turned off, suppress collector minority carrier injection, shorten the turn-off time, and reduce the turn-off loss.

[0123] Reference below Fig.14 A vehicle according to an embodiment of the present invention is described.

[0124] Fig.14 is a block diagram of a vehicle according to an embodiment of the present utility model, such as Fig.14As shown, the vehicle 100 includes the power electronic device 101 described in the above embodiment.

[0125] In some embodiments, the vehicle 100 may be various types of vehicles, including but not limited to electric vehicles, hybrid vehicles, electric bicycles, motorcycles, and electric buses.

[0126] According to the vehicle 100 of the embodiment of the utility model, by adopting the power electronic device 101 described in the above embodiment, it is possible to quickly extract electrons when the device is reversely turned off, suppress collector minority carrier injection, shorten the turn-off time, reduce the turn-off loss, and thus improve the overall performance of the vehicle 100.

[0127] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0128] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a substrate of a first conductivity type; a collector structure, the collector structure being located on the back side of the substrate; The collector structure comprises: a first collector region heavily doped with a second conductivity type; A second collector region heavily doped with a first conductivity type, the second collector region being located on a side of the first collector region along a first direction parallel to the substrate; A third collector region lightly doped with the second conductivity type is located at a side of the first collector region along the first direction and at a side of the second collector region close to the substrate along a second direction perpendicular to the substrate.

2. The semiconductor device according to claim 1, wherein: The second collector region comprises: A first collector region and a second collector region, wherein the first collector region and the second collector region are located at two sides of the first collector region along the first direction.

3. The semiconductor device according to claim 2, characterized in that The third collector region comprises: A third collector region and a fourth collector region, the third collector region and the fourth collector region are distributed on both sides of the first collector region along the first direction, the third collector region is located on a side of the first collector region close to the substrate, and the fourth collector region is located on a side of the second collector region close to the substrate.

4. The semiconductor device according to claim 3, characterized in that In a second direction perpendicular to the substrate, a side of the first collector region in contact with the back side of the substrate is closer to the front side of the substrate than a surface of the collector region, wherein the surface of the collector region is a side of the third collector region or the fourth collector region in contact with the back side of the substrate.

5. The semiconductor device according to claim 3, characterized in that The collector structure further comprises: A collector electrode is located on a side of the first collector region away from the third collector region, a side of the first collector region away from the substrate, and a side of the second collector region away from the fourth collector region.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device further comprises: A drift layer lightly doped with a first conductivity type, the drift layer being located on the front side of the substrate; A current spreading layer of a first conductivity type is located along a second direction perpendicular to the substrate on a surface of the drift layer away from the substrate.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: A trench gate structure, the trench gate structure comprising a gate trench, a gate oxide layer, a first gate and a second gate; Wherein, the gate trench extends along the second direction and penetrates the current spreading layer, and the bottom of the gate trench extends into the drift layer; The gate oxide layer is located in the gate trench and isolates the first gate and the second gate; The first gate and the second gate are both located in the gate trench and arranged along the second direction.

8. The semiconductor device according to claim 7, characterized in that A length of the second gate along the second direction is smaller than a length of the first gate along the second direction.

9. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises: A first well region of a second conductivity type is located at one side of the trench gate structure in the first direction and is located on a side of the current spreading layer away from the drift layer along the second direction.

10. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises: A first emitter region that is heavily doped with a first conductivity type and a second emitter region that is heavily doped with a second conductivity type. In the second direction, the first emitter region and the second emitter region are both located on a side of the first well region away from the current spreading layer. In the first direction, the first emitter region and the second emitter region are in contact with each other.

11. The semiconductor device according to claim 10, characterized in that The semiconductor device further comprises: an emission trench structure, wherein the emission trench structure extends along the second direction and penetrates the current spreading layer, and a bottom of the emission trench structure extends into the drift layer; A floating well region of the second conductivity type is formed between the emission trench structure and the trench gate structure along the first direction, and the floating well region is located on a side of the current spreading layer away from the drift layer in the second direction.

12. The semiconductor device according to claim 11, characterized in that The emission groove structure comprises: An emission groove, the emission groove extends along the second direction and penetrates the current spreading layer, and the bottom of the emission groove structure extends into the drift layer; Emitter polysilicon, the emitter polysilicon is located in the emitter trench; A first insulating layer is located between an inner wall of the emitter trench and the emitter polysilicon.

13. The semiconductor device according to claim 11, characterized in that The semiconductor device further comprises: A second insulating layer covers the emission trench structure, the floating well region and the trench gate structure along the second direction.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: A first emitting electrode, wherein the first emitting electrode covers the first emitting region and the second emitting region in the second direction, and one end of the first emitting electrode contacts one end of the second insulating layer.

15. The semiconductor device according to claim 10, wherein: The semiconductor device further comprises: A second well region of a second conductivity type, wherein the second well region is located on a side of the trench gate structure away from the first well region in the first direction and on a side of the current diffusion layer away from the drift layer.

16. The semiconductor device according to claim 15, characterized in that The semiconductor device further comprises: A third emitter region that is heavily doped with the first conductivity type and a fourth emitter region that is heavily doped with the second conductivity type. In the second direction, the third emitter region and the fourth emitter region are both located on a side of the second well region away from the current spreading layer. In the first direction, the third emitter region and the fourth emitter region are in contact with each other.

17. The semiconductor device according to claim 16, characterized in that The semiconductor device further comprises: A second emitting electrode, wherein the second emitting electrode covers the first emitting region, the second emitting region, the trench gate structure, the third emitting region and the fourth emitting region in the second direction.

18. A power electronic device, characterized in that: Comprising at least one semiconductor device according to any one of claims 1 to 17.

19. A vehicle, characterized in that: Comprising the power electronic device as claimed in claim 18.

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