Half-bridge rectification chip
By integrating two reverse parallel diodes in the half-bridge rectifier chip and optimizing the chip structure, the power density and cost problems caused by the complex packaging of traditional half-bridge rectifier devices are solved, and efficient power density improvement and cost reduction are achieved.
Patent Information
- Application Number
- CN202421096592.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-05-20
AI Technical Summary
The packaging process of traditional half-bridge rectifier devices is complex, resulting in reduced power density and increased cost of the device, making it difficult to meet the high requirements of modern semiconductor devices for power density and cost-effectiveness.
A half-bridge rectifier chip is designed to simplify the packaging process by integrating two reverse parallel diodes on one chip and utilizing vertical and horizontal conductive diode structures.
The power density of the device is improved, and the power density of traditional half-bridge devices is doubled, while reducing the packaging process steps and costs and reducing chip usage.
Smart Images
Figure CN222485187U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a half-bridge rectifier chip. Background Art
[0002] In the field of power electronic device technology, AC to DC conversion has always been an important application field. The current rectification methods include diode rectification, half-bridge rectification and full-bridge rectification.
[0003] Half-bridge rectification is a commonly used rectification method and needs to be implemented using a rectification half-bridge. The traditional rectification half-bridge is to package two diode chips in reverse parallel into a device. The packaging process is complicated and the package body is large, resulting in a decrease in device power density and an increase in cost. As power semiconductors have higher and higher requirements for power density and cost-effectiveness, improving the power density of the rectification half-bridge is an issue that technical personnel in this field urgently need to solve. Utility Model Content
[0004] In view of the above problems, the utility model provides a half-bridge rectifier chip which can effectively improve the power density of the rectifier half-bridge.
[0005] The technical solution of the utility model is:
[0006] Half-bridge rectifier chip, including:
[0007] A first heavily doped P region is located in the substrate, and an end portion thereof extends upward to the upper surface of the substrate; a lower surface of the first heavily doped P region is higher than a lower surface of the first lightly doped N region;
[0008] a second lightly doped N region, located in the first heavily doped P region, with an end portion extending upward to the upper surface of the substrate;
[0009] A plurality of second heavily doped P regions are provided and are spaced apart in the substrate;
[0010] A plurality of second heavily doped N regions are provided, located in the substrate and spaced apart on both sides of the second heavily doped P region;
[0011] A first isolation layer, located on the upper surface of the substrate;
[0012] a first anode extending downward from the top surface of the first isolation layer and connected to the first heavily doped P region to form an ohmic contact;
[0013] a second cathode, the top surface of the first isolation layer extending downward and connected to the second heavily doped N region to form an ohmic contact;
[0014] A second isolation layer, located on an upper surface of the first isolation layer;
[0015] The second anode extends downward from the top surface of the second isolation layer and is connected to the second heavily doped P region to form an ohmic contact.
[0016] Specifically, the substrate is an N-type substrate, including a first heavily doped N region and a first lightly doped N region from bottom to top, and the first cathode is connected to the first heavily doped N region to form an ohmic contact.
[0017] Specifically, the doping concentration of the first heavily doped N region is 2e 19 .cm -3 , thickness is 500um.
[0018] Specifically, the doping concentration of the first lightly doped N region is 1e 14. cm -3 , thickness is 100um.
[0019] Specifically, the upper surface of the second lightly doped N region is level with the upper surface of the substrate, the lower surface is higher than the lower surface of the first heavily doped P region, and the junction depth is set to 1-90 um.
[0020] Specifically, the upper surface of the second heavily doped P region is level with the upper surface of the substrate, the lower surface is higher than the lower surface of the second lightly doped N region, and the junction depth is 1-80 um.
[0021] Beneficial effects of the utility model:
[0022] The half-bridge rectifier chip in this case integrates two reverse-parallel diodes on one chip. The diodes from the first anode to the first cathode area conduct electricity vertically, and the diodes from the second anode to the second cathode area conduct electricity horizontally, which effectively utilizes the chip area. Using the half-bridge rectifier chip in this case only requires packaging one chip, which reduces the packaging process steps and costs. Using the half-bridge rectifier chip in this case can reduce the chip usage by half, and the device power density is twice that of traditional half-bridge devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a process flow chart of the utility model.
[0024] Figure 2 is a schematic diagram of the cross-sectional structure of the device in step S100,
[0025] Figure 3 is a schematic diagram of the cross-sectional structure of the device in step S200,
[0026] Figure 4 is a schematic diagram of the cross-sectional structure of the device in step S300,
[0027] Figure 5 is a schematic diagram of the cross-sectional structure of the device in step S400,
[0028] Figure 6is a schematic diagram of the structure of depositing the first isolation layer in step S500,
[0029] Figure 7 is a schematic diagram of the cross-sectional structure of the device in step S500,
[0030] Figure 8 is a schematic diagram of the structure of depositing the second isolation layer in step S600,
[0031] Fig. 9 is a schematic diagram of the cross-sectional structure of the device in step S600,
[0032] Fig.10 is a schematic diagram of the cross-sectional structure of the device in step S700,
[0033] In the figure, 1 is the substrate, 2 is the first heavily doped P region, 3 is the second lightly doped N region, 4 is the second heavily doped P region, 5 is the second heavily doped P region, 6 is the first isolation layer, 7 is the first anode, 8 is the second anode, 9 is the second cathode, 10 is the first cathode, 11 is the first heavily doped N region, 12 is the first lightly doped N region, and 13 is the second isolation layer. DETAILED DESCRIPTION
[0034] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0035] Reference below Figure 1-10 Describe the utility model;
[0036] A half-bridge rectifier chip and a preparation method thereof, comprising the following steps:
[0037] Step S100, preparing a first heavily doped P region 2 on a substrate 1; Figure 2 As shown;
[0038] Step S110, using a mask to protect the outer area of the first heavily doped P region 2 through a photolithography process;
[0039] Step S120: forming a first heavily doped P region 2 by diffusion or ion implantation.
[0040] Correspondingly, the substrate 1 is an N-type substrate, consisting of a first heavily doped N region 11 and a first lightly doped N region 12 from bottom to top, the substrate thickness is 110-2500um, the first heavily doped N region 11 is 100-2000um thick, the first lightly doped N region 12 is 10-500um thick, the first heavily doped P region 2 is located inside the first lightly doped N region 12, the upper surface is level with the upper surface of the substrate 1, and the lower surface is higher than the lower surface of the first lightly doped N region 12, the junction depth is set to 1-100um, the width is set to 100-10000um, and the doping concentration of all lightly doped regions is 1e 13 .cm -3 To 1e 17 .cm -3 , the doping concentration of the heavily doped region is 1e 19 .cm -3 To 1e 21 .cm -3 , the N-type doping element is phosphorus or arsenic, the P-type doping element is boron, and the relevant parameter settings are related to the device electrical design;
[0041] In this embodiment, the thickness of the substrate 1 is 600 um, the doping element of the first heavily doped N region 11 is phosphorus, and the doping concentration is 2e 19 .cm -3 , with a thickness of 500um, the doping element of the first lightly doped N region 12 is phosphorus, and the doping concentration is 1e 14. cm -3 , thickness is 100um, the doping element of the first heavily doped P region 2 is boron, and the doping concentration is 2e 19 .cm -3 The junction depth is 30um and the width is 660um. The first heavily doped P region 2 is formed using a diffusion process.
[0042] Step S200, preparing a second lightly doped N region 3 in the first heavily doped P region 2; Figure 3 As shown;
[0043] Step S210, using a mask to protect the outer area of the second lightly doped N region 3 through a photolithography process;
[0044] Step S220: forming a second lightly doped N region 3 by diffusion or ion implantation.
[0045] Accordingly, the second lightly doped N region 3 is located inside the first heavily doped P region 2, with the upper surface being level with the upper surface of the substrate 1, and the lower surface being higher than the lower surface of the first heavily doped P region 2, the junction depth being set to 1-90um, and the width being set to 90-9990um, and the relevant parameter settings being related to the device electrical design;
[0046] In this embodiment, the doping element of the second lightly doped N region 3 is phosphorus, and the doping concentration is 1e14. cm -3 , junction depth is 25um, width is 600um, and the second lightly doped N region 3 is prepared using a diffusion process.
[0047] Step S300, preparing a plurality of second heavily doped P regions 4 in the second lightly doped N region 3; Figure 4 As shown;
[0048] Step S310, using a mask to protect the outer regions of the second heavily doped P regions 4 through a photolithography process;
[0049] Step S320: forming a second heavily doped P region 4 by diffusion or ion implantation.
[0050] Accordingly, a plurality of second heavily doped P regions 4 are located inside the second lightly doped N region 3, with the upper surface being level with the upper surface of the substrate 1, and the lower surface being higher than the lower surface of the second lightly doped N region 3, the junction depth being set to 1-80um, and the width being set to 5-50um, and the relevant parameter settings are related to the electrical design of the device;
[0051] In this embodiment, the doping element of the second heavily doped P region 4 is boron, and the doping concentration is 2e 19 .cm -3 The junction depth is 5um and the width is 30um. Three second heavily doped P regions 4 are prepared using an ion implantation process.
[0052] Step S400, a plurality of second heavily doped N regions 5 separated by second heavily doped P regions 4 are prepared in the second lightly doped N region 3; Figure 5 As shown;
[0053] Step S410, using a mask to protect the outer regions of the second heavily doped N regions 5 by photolithography process;
[0054] Step S420: forming a second heavily doped N region 5 by diffusion or ion implantation.
[0055] Accordingly, a plurality of second heavily doped N regions 5 are located inside the second lightly doped N region 3, with the upper surface being level with the upper surface of the substrate 1, and the lower surface being higher than the lower surface of the second lightly doped N region 3, the junction depth being set to 1-80um, the width being set to 5-50um, the second heavily doped P region 4 being spaced from the second heavily doped N region 5, and the distance between the two being set to 10-500um, and the relevant parameter settings are related to the electrical design of the device;
[0056] In this embodiment, the doping element of the second heavily doped N region 5 is phosphorus, and the doping concentration is 2e 19 .cm -3, the junction depth is 5um, the width is 30um, and four second heavily doped N regions 5 are prepared by ion implantation process, and the second heavily doped P region 4 and the second heavily doped N region 5 are spaced apart, and the distance between the two is set to 70um.
[0057] Step S500, depositing a first isolation layer 6 on the substrate 1; and opening windows at the first heavily doped P region 2 and the second heavily doped N region 5 to prepare a first anode 7 and a second cathode 9; Figure 6-7 As shown;
[0058] Step S510, preparing a first isolation layer 6 by chemical vapor deposition;
[0059] Step S520, using a mask to protect the outer regions of the first heavily doped P region 2 and the second heavily doped N region 5 through a photolithography process, and using an etching process to open windows in the first heavily doped P region 2 and the second heavily doped N region 5;
[0060] Step S530 , preparing the first anode 7 and the second cathode 9 at the openings of the first heavily doped P region 2 and the second heavily doped N region 5 by a stripping process or an etching process.
[0061] Accordingly, the first isolation layer 6 plays a protective role, and is made of SiO2 or Si3N4, with a thickness set to 10-5000nm. ICP dry etching is used to open windows, and the first anode 7 and the second cathode 9 are in contact with the first heavily doped P region 2 and the second heavily doped N region 5 below to form ohmic contacts. The upper surfaces of the first anode 7 and the second cathode 9 are level with the upper surface of the first isolation layer 6. The relevant parameter settings are related to the electrical design of the device.
[0062] In this embodiment, Si3N4 is used as the first isolation layer 6 with a thickness set to 200nm. CF4 is used for ICP dry etching with an etching rate of 10nm / min to ensure the accuracy of etching. The etching time is set to 21min to ensure successful window opening. The metal stripping process is used to prepare the first anode 7 and the second cathode 9, and four layers of metal Al / Ti / Ni / Ag are used as ohmic contact metals.
[0063] Step S600, depositing a second isolation layer 13 on the substrate 1 and opening a window at the second heavily doped P region 4 to prepare a second anode 8; Figure 8-9 As shown;
[0064] Step S610, preparing a second isolation layer 13 by chemical vapor deposition;
[0065] Step S620, using a mask to protect the outer area of the second heavily doped P region 4 through a photolithography process, and using an etching process to open a window in the second heavily doped P region 4;
[0066] Step S630 , preparing a second anode 8 at the opening of the second heavily doped P region 4 by a stripping process or an etching process.
[0067] Accordingly, the second isolation layer 13 plays a protective role, and its material is SiO2 or Si3N4, and its thickness is set to 10-5000nm. ICP dry etching is used to open the window, and the second anode 8 contacts and forms an ohmic contact with the second heavily doped P region 4 below. The upper surface of the second anode 8 is level with the upper surface of the second isolation layer 13. The relevant parameter settings are related to the electrical design of the device;
[0068] In this embodiment, Si3N4 is used as the second isolation layer 13, the thickness is set to 200nm, CF4 is used for ICP dry etching, the etching rate is 10nm / min to ensure the accuracy of etching, the etching time is set to 41min to ensure successful window opening, and the second anode 8 is prepared by metal stripping process, using Al / Ti / Ni / Ag four-layer metal as ohmic contact metal.
[0069] Step S700, prepare the first cathode 10 at the bottom of the substrate 1, and the entire device is prepared. Fig.10 shown.
[0070] Step S700 is to prepare the first cathode 10 at the bottom of the substrate 1 by thinning process and back-gold process.
[0071] Accordingly, the first cathode 10 contacts the upper first heavily doped N region 11 and forms an ohmic contact;
[0072] In this embodiment, a 600um substrate 1 is thinned to 180um using a thinning process, and a four-layer metal of Al / Ti / Ni / Ag is deposited using a back-gold process as the ohmic contact metal of the first cathode 10, and the entire device is prepared.
[0073] The half-bridge rectifier chip in this case includes:
[0074] A first heavily doped P region 2 is located in the substrate 1, and an end portion thereof extends upward to the upper surface of the substrate 1; a lower surface of the first heavily doped P region 2 is higher than a lower surface of the first lightly doped N region 12;
[0075] A second lightly doped N region 3 is located in the first heavily doped P region 2, and an end portion thereof extends upward to the upper surface of the substrate 1; a lower surface of the second lightly doped N region 3 is higher than a lower surface of the first heavily doped P region 2;
[0076] A plurality of second heavily doped P regions 4 are provided and are spaced apart in the substrate 1; the upper surface of the second heavily doped P region 4 is level with the upper surface of the substrate 1, and the lower surface is higher than the lower surface of the second lightly doped N region 3;
[0077] The second heavily doped N region 5 is provided with a plurality of them, located in the substrate 1 and spaced apart on both sides of the second heavily doped P region 4; the upper surface of the second heavily doped N region 5 is level with the upper surface of the substrate 1, and the lower surface is higher than the lower surface of the second lightly doped N region 3; the second heavily doped P region 4 is spaced apart from the second heavily doped N region 5;
[0078] A first isolation layer 6, located on the upper surface of the substrate 1;
[0079] A first anode 7, extending downward from the top surface of the first isolation layer 6, and connected to the first heavily doped P region 2 to form an ohmic contact;
[0080] A second cathode 9, the top surface of the first isolation layer 6 extends downward and is connected to the second heavily doped N region 5 to form an ohmic contact;
[0081] A second isolation layer 13, located on the upper surface of the first isolation layer 6;
[0082] A second anode 8 extends downward from the top surface of the second isolation layer 13 and is connected to the second heavily doped P region 4 to form an ohmic contact;
[0083] The substrate 1 is an N-type substrate, comprising a first heavily doped N region 11 and a first lightly doped N region 12 from bottom to top;
[0084] The first cathode 10 is connected to the first heavily doped N region 11 to form an ohmic contact.
[0085] In this case, the doping concentration of the lightly doped region is 1e 13 .cm -3 To 1e 17 .cm -3 , the doping concentration of the heavily doped region is 1e 19 .cm -3 To 1e 21 .cm -3 The N-type doping element is phosphorus or arsenic, and the P-type doping element is boron.
[0086] Traditional half-bridge devices require two diode chips to be packaged in reverse parallel. The packaging process is complicated and the package body is large, resulting in a decrease in the power density of the device and an increase in cost. In this case, the half-bridge rectifier chip integrates two reverse-parallel diodes on one chip. The first anode and the second cathode are interconnected by interconnecting metal and connected to one end of an external AC power supply. The second anode and the first cathode are interconnected by a packaging frame and a jumper and connected to the other end of the power supply. When the first anode and the second cathode are connected to a positive voltage when power is turned on, the current flows from the first anode through the first heavily doped P region, the first lightly doped N region, and the first heavily doped N region to the first cathode, and the NP junction composed of the second lightly doped N region and the second heavily doped P region of the second cathode and the second anode is reversely cut off; when power is turned on, the second anode and the first cathode are connected to a positive voltage, the current flows from the second anode through the second heavily doped P region, the second lightly doped N region, and the second heavily doped N region to the second cathode, and the NP junction composed of the first lightly doped N region and the first heavily doped P region of the first cathode and the first anode is reversely cut off.
[0087] The use of the half-bridge rectifier chip in this case only requires packaging of one chip, which reduces the packaging process steps and costs. The use of the half-bridge rectifier chip in this case can reduce the number of chips used by half, and the device power density is twice that of traditional half-bridge devices.
[0088] Regarding the contents disclosed in this case, there are a few points that need to be explained:
[0089] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;
[0090] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;
[0091] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. Half-bridge rectifier chip, characterized in that: include: A first heavily doped P region (2) located in the substrate (1), with an end portion extending upward to the upper surface of the substrate (1); The lower surface of the first heavily doped P region (2) is higher than the lower surface of the first lightly doped N region (12); A second lightly doped N region (3), located in the first heavily doped P region (2), with an end portion extending upward to the upper surface of the substrate (1); A plurality of second heavily doped P regions (4) are provided and arranged at intervals in the substrate (1); A plurality of second heavily doped N regions (5) are provided, located in the substrate (1) and arranged at intervals on both sides of the second heavily doped P region (4); A first isolation layer (6) located on the upper surface of the substrate (1); A first anode (7), extending downward from the top surface of the first isolation layer (6) and connected to the first heavily doped P region (2) to form an ohmic contact; A second cathode (9), extending downward from the top surface of the first isolation layer (6) and connected to the second heavily doped N region (5) to form an ohmic contact; A second isolation layer (13), located on the upper surface of the first isolation layer (6); The second anode (8) extends downward from the top surface of the second isolation layer (13) and is connected to the second heavily doped P region (4) to form an ohmic contact.
2. The half-bridge rectifier chip according to claim 1, characterized in that: The substrate is an N-type substrate, comprising a first heavily doped N region (11) and a first lightly doped N region (12) from bottom to top, and the first cathode (10) and the first heavily doped N region (11) are connected to form an ohmic contact.
3. The half-bridge rectifier chip according to claim 2, characterized in that: The doping concentration of the first heavily doped N region (11) is 2e 19 .cm -3 , thickness is 500um.
4. The half-bridge rectifier chip according to claim 2, characterized in that: The doping concentration of the first lightly doped N region (12) is 1e 14. cm -3 , thickness is 100um.
5. The half-bridge rectifier chip according to claim 1, characterized in that: The upper surface of the second lightly doped N region (3) is level with the upper surface of the substrate (1), and the lower surface is higher than the lower surface of the first heavily doped P region (2), and the junction depth is set to 1-90 um.
6. The half-bridge rectifier chip according to claim 1, characterized in that: The upper surface of the second heavily doped P region (4) is level with the upper surface of the substrate (1), the lower surface is higher than the lower surface of the second lightly doped N region (3), and the junction depth is 1-80 um.