Display panel and electronic device including the same

Abstract

The utility model provides a display panel and an electronic device including the same. The display panel includes: a first pixel including a first light emitting portion in a first area and a first pixel driver in a second area; a second pixel including a second light emitting portion in the second region and a second pixel driver in the second region; a first connecting line connecting the first light emitting portion and the first pixel driver; and a second connection line connecting the second light emitting portion and the second pixel driver, in which each of the first light emitting portion and the second light emitting portion includes a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer, and each of the first connection line and the second connection line includes a driver connection portion and an emission connection portion spaced apart from the driver connection portion.

Description

Technical Field

[0001] Embodiments relate to a display panel including regions having different light transmittances and an electronic device including the display panel. Background Art

[0002] The electronic device may include various electronic components such as a display panel and an electronic optical module. The electronic optical module may include a camera, an infrared sensor, or a proximity sensor. The electronic optical module may be disposed under the display panel. The transmittance of some areas of the display panel may be higher than the transmittance of other areas of the display panel. The electronic optical module may receive a light signal or output a light signal through an area with high transmittance. Utility Model Content

[0003] The embodiment provides a display panel including a region having high light transmittance capable of transmitting a light signal and an electronic device including the display panel.

[0004] However, the embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0005] In an embodiment, a display panel may include: a first pixel, including a first light-emitting portion arranged in a first area and a first pixel driver arranged in a second area different from the first area; a second pixel, including a second light-emitting portion arranged in the second area and a second pixel driver arranged in the second area; a first connecting line connecting the first light-emitting portion and the first pixel driver; and a second connecting line connecting the second light-emitting portion and the second pixel driver, wherein each of the first light-emitting portion and the second light-emitting portion includes: a first electrode; an intermediate layer arranged on the first electrode and including a light-emitting material; and a second electrode arranged on the intermediate layer, each of the first connecting line and the second connecting line includes: a driver connecting part connected to a corresponding pixel driver of the first pixel driver and the second pixel driver; and an emission connecting part spaced apart from the driver connecting part and connected to the second electrode, and the first area has a transmittance higher than that of the second area.

[0006] In an embodiment, in a plan view, the first pixel driver and the second pixel driver may not overlap the first region.

[0007] In an embodiment, the emission connection portion of the first connection line may be disposed along a boundary between the first region and the second region.

[0008] In an embodiment, the emission connection portion of the first connection line may be disposed in the first region.

[0009] In an embodiment, the first connection line may overlap the first region in a plan view.

[0010] In an embodiment, the first electrode may be an anode and the second electrode may be a cathode.

[0011] In an embodiment, each of the first connection line and the second connection line may have an undercut shape in a cross-sectional view.

[0012] In an embodiment, the second electrode of the first light emitting part may contact a side surface of the first connection line, and the intermediate layer of the first light emitting part may be spaced apart from the side surface of the first connection line.

[0013] In an embodiment, the display panel may further include: a partition disposed between the first light emitting part and the second light emitting part, wherein the second electrode of the first light emitting part and the second electrode of the second light emitting part may be separated from each other by the partition.

[0014] In an embodiment, a shape of a spacer disposed in the first region in a plan view and a shape of a spacer disposed in the second region in a plan view may be different from each other.

[0015] In an embodiment, the number of second electrodes per unit area in the first region may be smaller than the number of second electrodes per unit area in the second region.

[0016] In an embodiment, the first connection line may be connected to a driving transistor of a first pixel driver, and the second connection line may be connected to a driving transistor of a second pixel driver.

[0017] In an embodiment, the first electrode of the first light emitting portion may be integral with the first electrode of the second light emitting portion.

[0018] In an embodiment, the first electrode of the first light emitting part may include: a plurality of patterns spaced apart from each other; and a connecting pattern connecting the plurality of patterns to each other, the connecting pattern and the plurality of patterns being arranged at different layers, wherein the first electrode of the second light emitting part may be connected to the connecting pattern.

[0019] In an embodiment, the display panel may further include: a third pixel including a third light emitting portion disposed in the first region; and a third pixel driver disposed in the peripheral region and connected to the third light emitting portion.

[0020] In an embodiment, an electronic device includes: a display panel including a first area and a second area adjacent to the first area; and an electronic optical module overlapping the first area in a plan view, wherein the display panel includes: a first pixel including a first light-emitting portion arranged in the first area and a first pixel driver arranged in the second area; a second pixel including a second light-emitting portion arranged in the second area and a second pixel driver arranged in the second area; a first connecting line connecting the first light-emitting portion and the first pixel driver, the first connecting line including a first emission connecting portion electrically connected to the first light-emitting portion; and a second connecting line connecting the second light-emitting portion and the second pixel driver, the second connecting line including a second emission connecting portion electrically connected to the second light-emitting portion, and in a cross-sectional view, each of the first emission connecting portion and the second emission connecting portion has an undercut shape.

[0021] In an embodiment, the first emission connection portion may be arranged along a boundary between the first region and the second region, and the first connection line and the second connection line may not overlap the first region in a plan view.

[0022] In an embodiment, the first emission connection portion may be disposed in the first region, and the first connection line may overlap the first region in a plan view.

[0023] In an embodiment, the anode of the first light emitting portion and the anode of the second light emitting portion may be integral with each other.

[0024] In an embodiment, the anode of the first light emitting portion may include: a plurality of patterns spaced apart from each other; and a connecting pattern connecting the plurality of patterns to each other, the connecting pattern and the plurality of patterns being disposed at different layers, and the anode of the second light emitting portion may be connected to the connecting pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments and together with the description serve to explain the principles of the present invention.

[0026] In the attached picture:

[0027] Figure 1 is a schematic block diagram of a display device according to an embodiment;

[0028] Figure 2A and Figure 2B is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0029] Figure 3 is a schematic perspective view of an electronic device according to an embodiment;

[0030] Figure 4Ais an exploded schematic perspective view of an electronic device according to an embodiment;

[0031] Figure 4B is a schematic block diagram of an electronic device according to an embodiment;

[0032] Figure 5A and Figure 5B is a schematic plan view schematically showing a display panel according to an embodiment;

[0033] FIG. 6A to FIG. 6C is an enlarged schematic plan view of a partial area of ​​a display panel according to an embodiment;

[0034] Figure 7 is a schematic cross-sectional view of a display panel according to an embodiment;

[0035] Fig. 8A is an enlarged schematic cross-sectional view of a partial region of a display panel according to an embodiment;

[0036] Figure 8B is an enlarged schematic cross-sectional view of a partial region of a display panel according to an embodiment;

[0037] Fig. 9A is a schematic plan view of a display panel according to an embodiment;

[0038] Fig. 9B is a schematic cross-sectional view of a display panel according to an embodiment;

[0039] Fig. 10A yes Figure 5A an enlarged schematic plan view of a portion of

[0040] Fig. 10B yes Fig. 10A an enlarged schematic plan view of a portion of

[0041] Fig. 10C is a schematic plan view of a display panel according to an embodiment;

[0042] Fig.11A and Fig. 11B is a schematic plan view of a display panel according to an embodiment;

[0043] Fig.12 is a schematic plan view of a display panel according to an embodiment; and

[0044] Fig.13A and Fig. 13B is an enlarged schematic plan view of a portion of a display panel according to an embodiment. DETAILED DESCRIPTION

[0045] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the utility model. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed in this article. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0046] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter, individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0047] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not express or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. Further, in the drawings, the size and relative size of the elements may be magnified for the purpose of clarity and / or description. When the embodiment can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or can be performed in an order opposite to the described order. Similarly, the same reference numerals represent the same elements.

[0048] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this purpose, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. Further, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 are not limited to three axes of a rectangular coordinate system such as an X-axis, a Y-axis, and a Z-axis, and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be understood to refer to only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] Although the terms "first", "second", etc. can be used to describe various types of elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0050] Spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and thereby to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented as being "above" the other elements or features. Thus, the term "below" may include both above and below orientations. Further, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0051] The terms used in this article are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used in this article, the singular forms "one" and "the (said)" are also intended to include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include", "comprise", "contain", "contain" and / or "have" indicate the existence of the described features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or increase of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used in this article, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, and similarly, are used to illustrate the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0052] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. Therefore, changes in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to specific illustrated shapes of regions, but should include shape deviations, for example, caused by manufacturing. In this way, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and are therefore not necessarily intended to be limiting.

[0053] As is customary in the art, some embodiments are described and shown in the accompanying drawings with functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, these blocks, units and / or modules can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, each block, unit and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present invention.

[0054] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0055] Figure 1 is a schematic block diagram of a display device DD according to an embodiment. Figure 1 , the display device DD may include a display panel DP, panel drivers SDC, EDC and DDC, a power supply PWS and a timing control unit TC. In an embodiment, the display panel DP is described as a light-emitting display panel. The light-emitting display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel or a quantum dot light-emitting display panel. In the embodiments described below, an organic light-emitting display panel will be described as an example. The panel drivers SDC, EDC and DDC may include a scan driver SDC, a light-emitting driver EDC and a data driver DDC.

[0056] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. The display panel DP may include pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. Here, m and n are integers greater than 1.

[0057] For example, the pixel PXij (where i and j are integers greater than 1) arranged at the i-th horizontal line (or i-th pixel row) and the j-th vertical line (or j-th pixel column) can be connected to the i-th first scan line GWLi (or write scan line), the i-th second scan line GCLi (or compensation scan line), the i-th third scan line GILi (or first initialization scan line), the i-th fourth scan line GBLi (or second initialization scan line), the i-th fifth scan line GRLi (or reset scan line), the j-th data line DLj and the i-th emission line ESLi.

[0058] The pixel PXij may include an emission element, a transistor, and a capacitor. The pixel PXij may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF (or a reference voltage), a fourth power supply voltage VINT1 (or a first initialization voltage), a fifth power supply voltage VINT2 (or a second initialization voltage), and a sixth power supply voltage VCOMP (or a compensation voltage) from a power supply PWS.

[0059] The voltage values ​​of the first power supply voltage VDD and the second power supply voltage VSS may be set so that current can flow through the emission element to emit light. For example, the first power supply voltage VDD may be set to a higher voltage than the second power supply voltage VSS.

[0060] The third power supply voltage VREF may be a voltage for initializing a gate electrode of a driving transistor included in a pixel PXij. The third power supply voltage VREF may be used to implement a specific grayscale based on a voltage difference with a data signal. For example, the third power supply voltage VREF may be set to a specific voltage within a voltage range of a data signal.

[0061] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the embodiment is not limited thereto.

[0062] The fifth power supply voltage VINT2 may be a voltage for initializing a cathode of an emission element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1 or may be set to a voltage similar to or equal to the third power supply voltage VREF, but the embodiment is not limited thereto and the fifth power supply voltage VINT2 may be set to a voltage similar to or equal to the first power supply voltage VDD.

[0063] In the case where the threshold voltage of the driving transistor is compensated, the sixth power supply voltage VCOMP may supply a certain current to the driving transistor.

[0064] exist Figure 1 , it is shown that all of the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are supplied from the power supply PWS, but the embodiment is not limited thereto. For example, both the first power supply voltage VDD and the second power supply voltage VSS may be supplied regardless of the structure of the pixel PXij, and according to the structure of the pixel PXij, at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied.

[0065] In an embodiment, the signal line connected to the pixel PXij may be set in various ways according to the circuit structure of the pixel PXij.

[0066] The scan driver SDC may receive a first control signal SCS from the timing control unit TC and may supply a scan signal to each of the first, second, third, fourth, and fifth scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn.

[0067] The scan signal can be set to a voltage at which the transistor receiving the scan signal is turned on. For example, the scan signal supplied to the P-type transistor can be set to a logic low level, and the scan signal supplied to the N-type transistor can be set to a logic high level. In the following, the meaning of "the scan signal is supplied" can be understood as the scan signal being supplied at a logic level that turns on the transistor controlled by the scan signal.

[0068] exist Figure 1 , for ease of description, the scan driver SDC is shown as a single component, but the embodiment is not limited thereto. According to the embodiment, in order to supply a scan signal to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, a plurality of scan drivers SDC may be included.

[0069] The light emitting driver EDC may supply the emission signal to the emission lines ESL1 to ESLn based on the second control signal ECS. For example, the emission signal may be sequentially supplied to the emission lines ESL1 to ESLn.

[0070] The transistors connected to the emission lines ESL1 to ESLn may be formed as N-type transistors. For example, the emission signals supplied to the emission lines ESL1 to ESLn may be set to a gate-off voltage. The transistors receiving the emission signals may be turned off when the emission signals are supplied, and may be turned on in other cases.

[0071] The second control signal ECS may include an emission start signal and a clock signal, and the light emitting driver EDC may be implemented as a shift register that sequentially generates and outputs a pulse type emission signal by sequentially shifting the pulse type emission start signal using the clock signal.

[0072] The data driver DDC may receive the third control signal DCS and the image data RGB from the timing control unit TC. The data driver DDC may convert the digital image data RGB into analog data signals (or data signals). The data driver DDC may supply data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0073] The third control signal DCS may include a data enable signal indicating the output of a valid data signal, a horizontal start signal, and a data clock signal. For example, the data driver DDC may include a shift register that generates a sampling signal by shifting the horizontal start signal in synchronization with the data clock signal, a latch that latches the image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data RGB (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0074] The power supply PWS may supply the first power supply voltage VDD, the second power supply voltage VSS and the third power supply voltage VREF for driving the pixel PXij to the display panel DP. For example, the power supply PWS may supply at least one of the fourth power supply voltage VINT1, the fifth power supply voltage VINT2 and the sixth power supply voltage VCOMP to the display panel DP.

[0075] As an example, the power supply PWS may be respectively connected to the first power supply line VDL (see Figure 2A ), the second power line VSL (see Figure 2A ), the third power line VRL (or reference voltage line, see Figure 2A ), the fourth power line VIL1 (or the first initialization voltage line, see Figure 2A ), the fifth power line VIL2 (or the second initialization voltage line, see Figure 2A ) and the sixth power line VCL (or compensation voltage line, see Figure 2A ) supplies a first power voltage VDD, a second power voltage VSS, a third power voltage VREF, a fourth power voltage VINT1, a fifth power voltage VINT2 and a sixth power voltage VCOMP to the display panel DP.

[0076] The power supply PWS may be implemented as a power management integrated circuit, but the embodiment is not limited thereto.

[0077] The timing control unit TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, a clock signal, etc. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the light emitting driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power supply PWS. The timing control unit TC may rearrange the input image data IRGB to correspond to the arrangement of the pixels PXij in the display panel DP, and may generate image data RGB (or frame data).

[0078] For example, the scan driver SDC, the light emitting driver EDC, the data driver DDC, the power supply PWS and / or the timing control unit TC may be formed (e.g., directly formed) on the display panel DP, or may be provided in the form of a separate driver chip and connected to the display panel DP. For example, at least two of the scan driver SDC, the light emitting driver EDC, the data driver DDC, the power supply PWS and the timing control unit TC may be provided as a driver chip (e.g., a single driver chip). For example, the data driver DDC and the timing control unit TC may be provided as a driver chip (e.g., a single driver chip).

[0079] In the above, reference has been made to Figure 1 The display device DD according to the embodiment is described, but the embodiment is not limited thereto. Depending on the configuration of the pixel, an additional signal line may be added or omitted. In addition, the connection relationship between a pixel and a signal line may be changed. In the case where one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0080] Figure 2A and Figure 2B is a schematic diagram of an equivalent circuit of pixels PXij and PXij-1 according to an embodiment. Figure 2A and Figure 2B A schematic diagram showing an equivalent circuit of pixels PXij and PXij-1 connected to an i-th first scan line GWLi (hereinafter, referred to as a first scan line) and to a j-th data line DLj (hereinafter, referred to as a data line) is shown.

[0081] like Figure 2A As shown in , the pixel PXij may include an emission element LD and a pixel driver PDC. The emission element LD may be connected to the first power line VDL and the pixel driver PDC.

[0082] The pixel driver PDC may be connected to the scan lines GWLi, GCLi, GILi, GBLi, and GRLi, the data lines DLj, the emission lines ESLi, and the power supply voltage lines VDL, VSL, VRL, VIL1, VIL2, and VCL. The pixel driver PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Hereinafter, the case where each of the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 is an N-type transistor will be described as an example. However, the embodiment is not limited thereto, and some of the first to eighth transistors T1 to T8 may be N-type transistors and the other transistors may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be a P-type transistor.

[0083] The gate electrode of the first transistor T1 may be connected to the first node N1. The first electrode of the first transistor T1 may be connected to the second node N2, and the second electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL to the second power line VSL via the emission element LD in response to the voltage of the first node N1. For example, the first power supply voltage VDD may be set to a voltage having a potential higher than that of the second power supply voltage VSS.

[0084] As used herein, “electrically connected between a transistor and a signal line or between transistors” means “a transistor in which a source electrode, a drain electrode, and a gate electrode have an integral shape with a signal line or the source electrode, the drain electrode, and the gate electrode are connected through a connecting electrode”.

[0085] The second transistor T2 may include a gate electrode connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply the data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on to connect (e.g., electrically connect) the data line DLj and the first node N1 when the write scan signal GW is supplied to the write scan line GWLi.

[0086] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, the gate electrode of the third transistor T3 may receive the reset scan signal GR through the i-th fifth scan line GRLi (hereinafter, referred to as the fifth scan line). The third transistor T3 may be turned on when the reset scan signal GR is supplied to the reset scan line GRLi, and the reference voltage VREF may be provided to the first node N1.

[0087] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 may be connected to the third node N3, and the second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 providing the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. The gate electrode of the fourth transistor T4 may receive the first initialization scan signal GI through the i-th third scan line GILi (hereinafter, referred to as the third scan line). The fourth transistor T4 may be turned on to supply the first initialization voltage VINT1 to the third node N3 when the first initialization scan signal GI is supplied to the first initialization scan line GILi.

[0088] The fifth transistor T5 may be connected between the compensation voltage line VCL and the second node N2. The first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP through the compensation voltage line VCL, and the second electrode of the fifth transistor T5 may be connected to the second node N2 and connected (e.g., electrically connected) to the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 may receive the compensation scan signal GC through the i-th second scan line GCLi (hereinafter, referred to as the second scan line). The fifth transistor T5 may be turned on when the compensation scan signal GC is supplied to the compensation scan line GCLi to provide the compensation voltage VCOMP to the second node N2, and during the compensation period, the threshold voltage of the first transistor T1 may be compensated.

[0089] The sixth transistor T6 may be connected between the first transistor T1 and the emission element LD. For example, the gate electrode of the sixth transistor T6 may receive the emission signal EM through the i-th emission line ESLi (hereinafter, referred to as the emission line). The first electrode of the sixth transistor T6 may be connected to the cathode of the emission element LD through the fourth node N4, and the second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 through the second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. In the case where the emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 may be turned on and may connect (e.g., electrically connect) the emission element LD to the first transistor T1.

[0090] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the seventh transistor T7 may receive the second power supply voltage VSS through the second power line VSL. The gate electrode of the seventh transistor T7 may be connected (e.g., electrically connected) to the emission line ESLi. The seventh transistor T7 may be referred to as a second emission control transistor. The seventh transistor T7 may be turned on when the emission signal EM is supplied to the emission line ESLi, and the second electrode of the first transistor T1 may be connected (e.g., electrically connected) to the second power line VSL.

[0091] In an embodiment, the sixth transistor T6 and the seventh transistor T7 may be connected to the same emission line ESLi and may be turned on by the same emission signal EM, and this is shown as an example and the sixth transistor T6 and the seventh transistor T7 may be turned on individually by different signals that are distinct from each other. In the pixel driver PDC according to an embodiment, the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0092] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. For example, the eighth transistor T8 may include a gate electrode connected to the i-th fourth scan line GBLi (hereinafter, referred to as the fourth scan line), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the emission element LD in response to the second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the emission element LD may be initialized by the second initialization voltage VINT2.

[0093] In an embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7 and T8 can be turned on at the same time by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be turned on at the same time by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 can be turned on / off at the same time by the same compensation scan signal GC. For example, the compensation scan line GCLi and the second initialization scan line GBLi can be substantially provided as a single scan line. Accordingly, the initialization operation of the cathode of the emission element LD and the threshold voltage compensation operation of the first transistor T1 can be performed with the same timing. However, this is shown as an example, but the embodiment is not limited thereto.

[0094] According to an embodiment, the initialization operation of the cathode of the emission element LD and the threshold voltage compensation operation of the first transistor T1 can be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be substantially provided as a single power supply voltage line. For example, the initialization operation of the cathode of the emission element LD and the threshold voltage compensation operation of the driving transistor T1 can be performed using the power supply voltage, and thus the driver design can be simplified. However, this is shown as an example, but the embodiment is not limited thereto.

[0095] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store charges corresponding to a voltage difference between a voltage of the first node N1 and a voltage of the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0096] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. For example, one electrode of the second capacitor C2 may be connected to the second power line VSL receiving the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power voltage VSS and the voltage of the third node N3. The second capacitor C2 may be referred to as a holding capacitor. The second capacitor C2 may have a storage capacity higher than that of the first capacitor C1. Accordingly, the second capacitor C2 may minimize a voltage change of the third node N3 in response to a voltage change of the first node N1.

[0097] In an embodiment, the emission element LD may be connected to the pixel driver PDC through a fourth node N4. The emission device LD may include an anode connected to the first power line VDL and a cathode opposite to the anode. In an embodiment, the cathode of the emission element LD may be connected to the pixel driver PDC through a fourth node N4. For example, in a pixel PXij according to an embodiment, the connection node to which the emission element LD and the pixel driver PDC are connected may be a fourth node N4, and the fourth node N4 may correspond to a connection node between the first electrode of the sixth transistor T6 and the cathode of the emission element LD. Accordingly, the potential of the fourth node N4 may substantially correspond to the potential of the cathode of the emission element LD.

[0098] For example, the anode of the emission element LD may be connected to the first power line VDL so that the first power supply voltage VDD, which is a constant voltage, is applied to the anode of the emission element LD, and the cathode of the emission element LD may be connected to the first transistor T1 through the sixth transistor T6. For example, in an embodiment in which the first to eighth transistors T1 to T8 are N-type transistors, the potential of the third node N3 corresponding to the source electrode of the driving transistor (the first transistor T1) may not be directly affected by the characteristics of the emission element LD. Therefore, in the event of degradation of the emission element LD, the influence on the gate-source voltage (Vgs) of the transistor (e.g., the driving transistor) forming the pixel driver PDC may be reduced. For example, since the amount of change in the driving current ILD caused by the degradation of the emission element LD is reduced, the afterimage defect of the display panel caused by the increase in the use time may be reduced, and the life of the display panel may be improved.

[0099] like Figure 2B As shown in FIG. 1 , the pixel PXij- 1 may include a pixel driver PDC- 1 including two transistors T1 and T2 and a capacitor C1. The pixel driver PDC- 1 may be connected to the emission element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. Figure 2B The pixel driver PDC-1 shown in FIG. Figure 2A This corresponds to the case where the third to eighth transistors T3 to T8 and the second capacitor C2 are omitted in the pixel driver PDC shown in FIG.

[0100] Each of the first transistor T1 and the second transistor T2 may be an N-type transistor or a P-type transistor. In an embodiment, each of the first transistor T1 and the second transistor T2 will be described as an N-type transistor.

[0101] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node disposed toward a first power line VDL, and the third node N3 may be a node disposed toward a second power line VSL. The first transistor T1 may be connected to the emission element LD through the second node N2, and may be connected to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0102] The second transistor T2 may include a gate electrode receiving a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0103] The capacitor C1 may include an electrode connected to the first node N1 and an electrode connected to the third node N3. The capacitor C1 may store charges corresponding to a voltage difference between a voltage of the data signal DATA transmitted to the first node N1 and a voltage of the third node N3.

[0104] The emission element LD may include an anode and a cathode. In an embodiment, the anode of the emission element LD may be connected to the first power line VDL, and the cathode of the emission element LD may be connected to the pixel driver PDC-1 through the second node N2. In an embodiment, the cathode of the emission element LD may be connected to the first transistor T1. The emission element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driver PDC-1.

[0105] In an embodiment in which the first transistor T1 and the second transistor T2 are N-type transistors, the cathode of the emission element LD and the second node N2 to which the pixel driver PDC-1 is connected may correspond to the drain electrode of the first transistor T1. For example, a change in the gate-source voltage (Vgs) of the first transistor T1 due to the emission element LD may be prevented. Accordingly, since the amount of change in the drive current ILD due to the degradation of the emission element LD is reduced, the afterimage defect of the display panel due to the increase in the use time may be reduced, and the life of the display panel may be improved.

[0106] Figure 2A and Figure 2B The circuits of the pixel drivers PDC and PDC-1 according to the embodiments are shown, and with respect to the display panel according to the embodiments, in the case where the circuit is connected to the cathode of the emission element LD, the number or arrangement of transistors and the number or arrangement of capacitors can be designed in various ways and this is not limited to any one embodiment.

[0107] Figure 3 1 is a schematic perspective view of an electronic device 1000 according to an embodiment. Figure 3 , the electronic device 1000 shows a mobile phone as an example. However, the embodiment is not limited thereto, and the electronic device 1000 may be a tablet computer, a monitor, a television, a car navigation system, a game console, or a wearable device.

[0108] The electronic device 1000 may display an image through the display area 1000A. The display area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. The display area 1000A may further include curved surfaces bent from at least two sides of the plane, respectively. However, the shape of the display area 1000A is not limited thereto. For example, the display area 1000A may include only a plane, or the display area 1000A may further include at least two curved surfaces (e.g., four curved surfaces bent from four sides of the plane, respectively).

[0109] A portion of the display area 1000A may be defined as a sensing area 1000SA. Figure 1 1000SA is shown as an example, but the number of sensing areas 1000SA is not limited thereto. The sensing area 1000SA may be a part of the display area 1000A, but may have a higher light signal transmittance than other areas of the display area 1000A. Accordingly, the sensing area 1000SA may display an image and transmit a light signal at the same time.

[0110] The electronic device 1000 may include an electronic optical module disposed in an area overlapping the sensing area 1000SA. The electronic optical module may receive an optical signal provided from the outside through the sensing area 1000SA, or may output an optical signal through the sensing area 1000SA. For example, the electronic optical module may be a camera module, a sensor such as a proximity sensor that measures the distance between an object and a mobile phone, a sensor that recognizes a part of a user's body (e.g., a fingerprint, an iris, or a face), or a small lamp that outputs light, but the embodiment is not limited thereto.

[0111] The thickness direction of the electronic device 1000 may be a third direction DR3 that is a normal direction of the display area 1000A. Front (or upper) and rear (or lower) surfaces of members forming the electronic device 1000 may be defined with respect to the third direction DR3.

[0112] Figure 4A is an exploded schematic perspective view of an electronic device 1000 according to an embodiment. Figure 4B is a schematic block diagram of an electronic device 1000 according to an embodiment.

[0113] like Figure 4A and Figure 4B As shown in FIG. 1 , the electronic device 1000 may include a display device DD, an electronic module ELM, an electronic optical module EOM, a power supply module PSM, and a housing HM. The electronic device 1000 may further include additional components.

[0114] The display device DD may generate an image and may at least detect an external input. The display device DD may include a window WN and a display module DM.

[0115] The window WN may provide a front surface of the electronic device 1000. The window WN may include a glass film or a synthetic resin film as a base film. The window WN may further include an anti-reflection layer or an anti-fingerprint layer. The window WN may further include a light blocking pattern overlapping the peripheral area DP-NA of the display panel DP. The light blocking pattern may define a frame of the electronic device 1000. The window WN and the display module DM may be coupled to each other by an adhesive layer.

[0116] The display module DM may include at least a display panel DP. Figure 4A Only the display panel DP among the stacked structure of the display module DM is shown in FIG. 1 , but the display module DM may further include a plurality of components disposed above the display panel DP. A detailed description of the stacked structure of the display module DM will be given below.

[0117] The display panel DP may include a display area DP-A and a peripheral area DP-NA. The display area DP-A may be Figure 3 5. The pixel PX (see FIG. 5) may be disposed in the display area DP-A. The emission element may be disposed in the display area DP-A, and the emission element may not be disposed in the peripheral area DP-NA.

[0118] The display panel DP may include Figure 3 The sensing area 100SA corresponds to the sensing area 1000SA of the display area DP-A. The sensing area 100SA may have a resolution lower than that of other areas of the display area DP-A. A detailed description of the sensing area 100SA will be given below.

[0119] like Figure 4A As shown in , the driving chip DIC may be disposed on the peripheral area DP-NA of the display panel DP. The flexible printed circuit board FCB may be coupled to the peripheral area DP-NA of the display panel DP. The flexible printed circuit board FCB may be connected to the main circuit board. The main circuit board may be an electronic component forming the electronic module ELM. The bending area BA of the peripheral area DP-NA may be bent so that the flexible printed circuit board FCB may be disposed below the display area DP-A.

[0120] The driving chip DIC may include a driving element (eg, a data driver DDC (see Figure 1 )).although Figure 4AA structure in which the driving chip DIC is mounted on the display panel DP is shown, but the embodiment is not limited thereto. For example, the driving chip DIC may be mounted on a flexible printed circuit board FCB.

[0121] refer to Figure 4A , the electronic module ELM and the power supply module PSM may be accommodated in the housing HM. The housing HM may be combined with a display device DD (eg, a window WN) to accommodate other modules.

[0122] like Figure 4B As shown in , the display device DD may include a display panel DP and a sensor SS. The sensor SS may include any one or more of an input sensor, an antenna sensor, and a fingerprint sensor.

[0123] The electronic module ELM may include a control module E-10, a wireless communication module E-20, an image input module E-30, a sound input module E-40, a sound output module E-50, a memory E-60, and an external interface module E-70. The electronic module ELM may include a main circuit board, and each module may be mounted on the main circuit board or may be connected (e.g., electrically connected) to the main circuit board through a flexible circuit board. The electronic module ELM may be connected (e.g., electrically connected) to a power supply module PSM.

[0124] The control module E-10 may control the overall operation of the electronic device 1000. For example, the control module E-10 may activate or deactivate the display device DD according to user input. The control module E-10 may control the image input module E-30, the sound input module E-40, and the sound output module E-50, etc. according to user input. The control module E-10 may include at least one microprocessor.

[0125] The wireless communication module E-20 can use Bluetooth or Wi-Fi lines to send wireless signals to other terminals / receive wireless signals from other terminals. The wireless communication module E-20 can use a general communication line to send / receive voice signals. The wireless communication module E-20 can include an antenna module.

[0126] The image input module E-30 can process an image signal and can convert the processed image signal into image data displayed on the display device DD. The sound input module E-40 can receive an external sound signal through a microphone in a recording mode or a voice recognition mode, and can convert the external sound signal into electronic voice data. The sound output module E-50 can convert the sound data received from the wireless communication module E-20 or the sound data stored in the memory E-60, and can output the converted sound data to the outside.

[0127] The external interface module E-70 may be used as an interface to connect to an external charger, a wired / wireless data port, or a card (eg, memory card and SIM / UIM card) slot, etc.

[0128] The power supply module PSM may supply power required for the overall operation of the electronic device 1000. The power supply module PSM may include a conventional battery device.

[0129] The electronic optical module EOM may be an electronic component that outputs or receives an optical signal. The electronic optical module EOM may include a camera module and / or a proximity sensor. The camera module may capture an external image through the sensing area 1000SA.

[0130] Figure 5A and Figure 5B is a schematic plan view schematically showing display panels DP and DP0 according to an embodiment. Figure 5A and Figure 5B In each of the above, some parts are omitted. Figure 5A and Figure 5B Describes the embodiments. Figure 5A , the display panel DP may include a display area DP-A and a peripheral area DP-NA. The peripheral area DP-NA may be adjacent to the display area DP-A and may surround at least a portion of the display area DP-A. However, this is shown as an example, and the peripheral area DP-NA may be provided on one side of the display area DP-A or may be omitted, but the embodiment is not limited thereto.

[0131] The display area DP-A may include a first area DP-A1, a second area DP-A2, and a third area DP-A3. Figure 3 In the embodiment, the first area DP-A1 is shown as a circular shape, but the first area DP-A1 may have various shapes such as a polygon, an ellipse, a figure having at least one curved side, or an irregular shape, and the embodiment is not limited thereto.

[0132] The display panel DP may include pixels PX. The display panel DP may include a first group of pixels PX-A (or first region pixels) including a light emitting portion disposed in a first region DP-A1, a second group of pixels PX-B (or second region pixels) including a light emitting portion disposed in a second region DP-A2, and a third group of pixels PX-C (or third region pixels) including a light emitting portion disposed in a third region DP-A3. Figure 5A The positions of the first group of pixels PX-A, the second group of pixels PX-B, and the third group of pixels PX-C shown in FIG. 1 are shown based on the positions of the corresponding light emitting parts. The light emitting parts may be connected to the emission element LD (see Figure 2A or Figure 2B ) corresponds to the luminous area.

[0133] Each of the first pixel group PX-A, the second pixel group PX-B, and the third pixel group PX-C may include a plurality of pixels. For example, according to an embodiment, each of the first to third pixel groups PX-A, PX-B, and PX-C may include red pixels, green pixels, and blue pixels, and may further include white pixels.

[0134] The first area DP-A1, the second area DP-A2, and the third area DP-A3 may be defined according to transmittance or resolution. The transmittance and resolution are measured within a reference area.

[0135] The light transmittance of the first area DP-A1 may be higher than the light transmittance of the second area DP-A2 and the third area DP-A3. This is because the occupied area ratio of the light blocking structure described below is lower in the first area DP-A1 than in the second area DP-A2 and the third area DP-A3. The non-occupied area of ​​the light blocking structure corresponds to the transmission area of ​​the light signal. The light blocking structure may include a conductive pattern, a pixel defining film, a pixel defining pattern, etc., which will be described below.

[0136] The third area DP-A3 may have a higher resolution than the first area DP-A1 and the second area DP-A2. In the third area DP-A3, a greater number of emitting elements may be set within the reference area (or the same area / unit area) than in the first area DP-A1 and the second area DP-A2. However, this is described as an example, and the third area DP-A3 may have a resolution substantially the same as that of the first area DP-A1 or the second area DP-A2, and this is not limited to any one embodiment.

[0137] Based on the transmittance, the first area DP-A1 may be a first transmittance area, and the second area DP-A2 and the third area DP-A3 may be different parts of a second transmittance area separated from the first transmittance area. The transmittances of the second area DP-A2 and the third area DP-A3 may be substantially the same as each other. In the case where the transmittances of the second area DP-A2 and the third area DP-A3 are different from each other, since the transmittance of the first area DP-A1 is significantly higher than the transmittance of each of the second area DP-A2 and the third area DP-A3, in the case where the first area DP-A1 is defined as the first transmittance area, the second area DP-A2 and the third area DP-A3 may be defined as the second transmittance area.

[0138] Based on the resolution, the first area DP-A1 and the second area DP-A2 may be different parts of the first resolution area, and the third area DP-A3 may be a second resolution area that is distinct from the first resolution area. The number of emitting elements per reference area of ​​the first area DP-A1 may be substantially the same as the number of emitting elements per reference area of ​​the second area DP-A2.

[0139] In an embodiment, the scan driver SDC (refer to Figure 1 ) and data driver DDC (reference Figure 1 ) may be mounted on the display panel DP. In an embodiment, the scan driver SDC may be disposed in the display area DP-A, and the data driver DDC may be disposed in the peripheral area DP-NA. The data driver DDC may be a separate driver chip DIC (refer to Figure 4A ) is provided in the form of a display panel DP, and may be connected to the display panel DP. However, this is described as an example, and the data driver DDC may be formed in the same process as the scan driver SDC to constitute the display panel DP, but the embodiment is not limited thereto.

[0140] In a plan view, the scan driver SDC may be connected to the light emitting portion EP (see Figure 6C As the scan driver SDC is placed in the display area DP-A, the area of ​​the peripheral area DP-NA can be reduced compared to a conventional display panel in which the scan driver is provided in the peripheral area, and a display device with a thin frame can be easily implemented.

[0141] With reference Figure 5A Different from the description, in another example, the scan driver SDC may be provided as two distinct parts. Two scan drivers SDC may be arranged on the left and right sides, wherein the center of the display area DP-A is between the left and right sides. In another example, two or more scan drivers SDC may be provided, and the number of the scan drivers SDC is not limited to any one embodiment. In another example, the data driver DDC may be arranged in the display area DP-A. For example, in a plan view, some of the light emitting parts EP arranged in the display area DP-A may overlap with the data driver DDC.

[0142] like Figure 5BAs shown in , the display panel DP0 may have a shape in which a length extending in the first direction DR1 is longer than a length extending in the second direction DR2. The display area DP0-A is shown to have a rectangular shape having long sides extending in the first direction DR1 and short sides extending in the second direction DR2. The peripheral area DP0-NA is shown to have a rectangular frame shape having long sides extending in the first direction DR1 and short sides extending in the second direction DR2.

[0143] like Figure 5B As shown in FIG. 1 , the display area DP0-A may include a first area DP0-A1, a second area DP0-A2, and a third area DP0-A3. The first area DP0-A1, the second area DP0-A2, and the third area DP0-A3 may be respectively Figure 5A The first area DP-A1, the second area DP-A2 and the third area DP-A3 shown in FIG.

[0144] In an embodiment, the display panel DP0 may include scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 are shown to include a first scan driver SDC1 and a second scan driver SDC2 spaced apart from each other in a first direction DR1.

[0145] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0146] For the convenience of description, Figure 5B 1 and 2 show pads PD of the data lines DL1 to DLm. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC (see FIG. 1 ) through the pads PD. Figure 1 ). For example, the pixels PX11 to PXnm may be arranged in the third area DP0-A3.

[0147] According to an embodiment, the pads PD may be divided and arranged at positions spaced apart from each other in the peripheral area DP-NA, with the display area DP-A between the pads PD. For example, some of the pads PD may be disposed on the upper side (e.g., a side adjacent to the first scan line GL1 among the scan lines GL1 to GLn), and other pads of the pads PD may be disposed on the lower side (e.g., a side adjacent to the last scan line GLn among the scan lines GL1 to GLn). In an embodiment, the pads PD connected to the odd-numbered data lines among the data lines DL1 to DLm may be disposed on the upper side, and the pads PD connected to the even-numbered data lines among the data lines DL1 to DLm may be disposed on the lower side.

[0148] For example, the display panel DP0 may include a plurality of upper data drivers connected to the pads PD disposed on the upper side and / or a plurality of lower data drivers connected to the pads PD disposed on the lower side. However, this is explained illustratively, and the display panel DP0 may include one upper data driver connected to the pads PD disposed on the upper side and / or one lower data driver connected to the pads PD disposed on the lower side. For example, the pads PD according to the embodiment may be disposed on a single side of the display panel DP0 and may be connected to a single data driver, but the embodiment is not limited thereto.

[0149] As above Figure 5A As stated in Figure 5B In the display panel DP0 of the embodiment, the scan driver and / or the data driver may be provided in the display area DP0-A, and accordingly, some of the light emitting parts provided in the display area DP0-A may overlap with the scan driver and / or the data driver in a plan view. The display panels DP and DP0 according to the embodiment may have various shapes and may be connected to various types of drivers SDC, SDC1, SDC2, and DDC, but the embodiment is not limited thereto.

[0150] FIG. 6A to FIG. 6C is an enlarged schematic plan view of a partial area of ​​a display panel according to an embodiment. Fig. 6A shows an area where a total of four light emitting units UT are arranged in two rows and two columns, and Figure 6B Shows Fig. 6A An enlarged schematic diagram of a portion of the area shown in FIG. Figure 6C middle, Fig. 6A Some of the components shown in FIG. 1 are omitted or emphasized. FIG. 6A to FIG. 6C Embodiments are described.

[0151] Fig. 6AThe light emitting cells UT11, UT12, UT21 and UT22 in two rows and two columns are shown. The light emitting cells of the first row Rk include light emitting cells forming the first row and first column light emitting cells UT11 and the first row and second column light emitting cells UT12, and the light emitting cells of the second row Rk+1 include light emitting cells forming the second row and first column light emitting cells UT21 and the second row and second column light emitting cells UT22. Figure 6B The light emitting parts of the first row Rk are shown. FIG. 6A to FIG. 6C A spacer SPR, light emitting parts EP1, EP2, and EP3 disposed in regions partitioned by the spacer SPR, connection lines CN1, CN2, and CN3, a first electrode EL1, and second electrodes EL2_1, EL2_2, and EL2_3 are shown among components of the display panel.

[0152] As described above, each of the light emitting parts EP1, EP2, and EP3 may be connected to the light emitting opening OP-PDL (see Figure 7 For example, each of the light emitting parts EP1, EP2, and EP3 may be a region in which light is emitted by the above-mentioned emission element LD, and may correspond to the region displayed on the display panel DP (see Figure 1 ) corresponds to a unit of an image displayed on the image display. For example, each of the light emitting parts EP1, EP2 and EP3 may correspond to an area defined by the light emitting opening OP-PDL described below (eg, an area defined by the lower surface of the light emitting opening OP-PDL).

[0153] The light emitting parts EP1, EP2 and EP3 may include a first light emitting part EP1, a second light emitting part EP2 and a third light emitting part EP3. The first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 may emit light of different colors from each other. For example, the first light emitting part EP1 may emit red light, the second light emitting part EP2 may emit green light and the third light emitting part EP3 may emit blue light, and the combination of colors is not limited thereto. For example, at least two of the light emitting parts EP1, EP2 and EP3 may emit light of the same color. For example, all of the first to third light emitting parts EP1, EP2 and EP3 may emit blue light, or all of the first to third light emitting parts EP1, EP2 and EP3 may emit white light.

[0154] For example, among the light emitting parts EP1, EP2, and EP3, the third light emitting part EP3 emitting light emitted by the third emission element may include two sub-light emitting parts EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is shown as an example, and like the other light emitting parts EP1 and EP2, the third light emitting part EP3 may be provided in a pattern having an integral shape, and at least one of the other light emitting parts EP1 and EP2 may include spaced apart sub-light emitting parts, but the embodiment is not limited thereto.

[0155] In an embodiment, the light emitting portion of the first row Rk may be composed of a light emitting portion in which the first row and first column light emitting cells UT11 and the first row and second column light emitting cells UT12 are repeatedly arranged. The light emitting portion of the second row Rk+1 may be composed of a light emitting portion having a shape and arrangement that is symmetrical to the shape and arrangement axis of the light emitting portion of the first row Rk about an axis parallel to the first direction DR1. Accordingly, the light emitting portions forming the first row and first column light emitting cells UT11 and the first row and second column light emitting cells UT12 and the connecting portions of the connecting lines may have a shape and arrangement that is symmetrical to the shape and arrangement axis of the light emitting portions forming the second row and first column light emitting cells UT21 and the second row and second column light emitting cells UT22 and the connecting portions of the connecting lines about an axis parallel to the first direction DR1.

[0156] Hereinafter, the first row and first column light emitting unit UT11 will be described. For the convenience of description, Figure 6B The second electrodes EL2_1 (e.g., EL2_1a and EL2_1b), EL2_2 (e.g., EL2_2a and EL2_2b), and EL2_3 (e.g., EL2_3a and EL2_3b), pixel drivers PDC (e.g., PDC1a, PDC1b, PDC2a, PDC2b, PDC3a, and PDC3b), and connection lines CN (e.g., CN1a, CN1b, CN2a, CN2b, CN3a, and CN3b) are shown. The second electrodes EL2_1, EL2_2, and EL2_3 may be electrically disconnected from each other by being separated from each other by means of a separator SPR. In an embodiment, the light emitting unit UT may include three light emitting portions EP1, EP2, and EP3. Accordingly, the light emitting unit UT may include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter, referred to as first to third cathodes), three pixel drivers PDC1, PDC2, and PDC3, and three connection lines CN1, CN2, and CN3. However, this is shown as an example, and the number and arrangement of the light emitting units UT may be designed in various ways, but the embodiment is not limited thereto.

[0157] The first to third pixel drivers PDC1, PDC2 and PDC3 may be connected (e.g., electrically connected) to the emission elements forming the first to third light emitting parts EP1, EP2 and EP3, respectively. In the description, "connected" includes not only a case of being physically connected by direct contact but also a case of being electrically connected.

[0158] For example, Figure 6B As shown in FIG. 1 , each region in which pixel drivers PDC1, PDC2, and PDC3 are defined in the plan view may be a region in which circuits forming emission elements for driving pixels are repeatedly arranged ( Figure 2A The pixel driver PDC or Figure 2B Corresponding to the units of transistor and capacitor elements of the pixel driver PDC-1).

[0159] The first to third pixel drivers PDC1, PDC2 and PDC3 may be sequentially arranged along the first direction DR1. For example, the arrangement positions of the first to third pixel drivers PDC1, PDC2 and PDC3 may be independently designed regardless of the positions or shapes of the first to third light emitting parts EP1, EP2 and EP3.

[0160] For example, the first to third pixel drivers PDC1, PDC2 and PDC3 may be disposed in an area defined by being separated by means of a partition SPR (e.g., disposed at a position different from the position where the first to third cathodes EL2_1, EL2_2 and EL2_3 are disposed), or may be formed into a shape having an area different from the area of ​​the first to third cathodes EL2_1, EL2_2 and EL2_3. In another example, the first to third pixel drivers PDC1, PDC2 and PDC3 may be disposed to overlap with the positions where the first to third light emitting parts EP1, EP2 and EP3 are disposed, respectively, and may be formed into an area defined by being separated by means of a partition SPR (e.g., an area similar to the area of ​​the first to third cathodes EL2_1, EL2_2 and EL2_3).

[0161] In an embodiment, each of the first to third pixel drivers PDC1, PDC2 and PDC3 can be shown as a rectangular shape, each of the first to third light-emitting portions EP1, EP2 and EP3 can be arranged into a smaller area and a different shape, and the first to third cathodes EL2_1, EL2_2 and EL2_3 are set at positions overlapping with the first to third light-emitting portions EP1, EP2 and EP3 but are shown as irregular shapes.

[0162] Accordingly, if Figure 6BAs shown in , the first pixel driver PDC1 can be set at a position partially overlapping with the first light-emitting part EP1, the second light-emitting part EP2 and other adjacent light-emitting parts EP. The second pixel driver PDC2 can be set at a position overlapping with the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3. The third pixel driver PDC3 can be set at a position overlapping with the third light-emitting part EP3. For example, this is shown as an example, and the positions of the first to third pixel drivers PDC1, PDC2 and PDC3 can be designed in various shapes and arrangements independently of the light-emitting parts EP1, EP2 and EP3, but the embodiment is not limited thereto.

[0163] A plurality of connection lines CN may be provided and may be spaced apart from each other. The connection lines CN may connect the pixel driver PDC and the emission element LD (see Figure 7 ) connection (eg, electrical connection). For example, the connection line CN may be connected to the node of the pixel driver PDC (see Figure 2A The fourth node N4 in Figure 2B Corresponding to the second node N2) in.

[0164] The connection line CN may include a first connection portion CE (or emission connection portion) and a second connection portion CD (or driver connection portion). The emission connection portion CE may be provided at one end of the connection line CN, and the driver connection portion CD may be provided at the other end of the connection line CN.

[0165] The driver connection portion CD may be a portion of the connection line CN connected to the pixel driver PDC. In an embodiment, the driver connection portion CD may be connected to an electrode of a transistor forming the pixel driver PDC. For example, the driver connection portion CD may be connected to Figure 2A The drain electrode of the sixth transistor T6 shown in FIG. Figure 2B Accordingly, the position of the driver connection portion CD can be aligned with the position of the transistor TR (see FIG. 1 ) physically connected to the connection line CN in the pixel driver PDC. Figure 7 ) corresponds to the position of the emission connection portion CE. The emission connection portion CE may be a portion of the connection line CN connected to the emission element LD. In an embodiment, the emission connection portion CE may be connected to the second electrode EL2 of the emission element LD (see Figure 7 ) (hereinafter, referred to as cathode).

[0166] The light emitting unit UT may include first to third connection lines CN1, CN2, and CN3. The first connection line CN1 may connect the emission element LD forming the first light emitting portion EP1 with the first pixel driver PDC1, the second connection line CN2 may connect the emission element LD forming the second light emitting portion EP2 with the second pixel driver PDC2, and the third connection line CN3 may connect the emission element LD forming the third light emitting portion EP3 with the third pixel driver PDC3.

[0167] For example, the first to third connection lines CN1, CN2, and CN3 may connect the first to third cathodes EL2_1, EL2_2, and EL2_3 to the first to third pixel drivers PDC1, PDC2, and PDC3, respectively. The first connection line CN1 may include a first driver connection portion CD1 (e.g., CD1a and CD1b) connected to the first pixel driver PDC1 and a first emission connection portion CE1 (e.g., CE1a and CE1b) connected to the first cathode EL2_1. The second connection line CN2 may include a second driver connection portion CD2 (e.g., CD2a and CD2b) connected to the second pixel driver PDC2 and a second emission connection portion CE2 (e.g., CE2a and CE2b) connected to the second cathode EL2_2. The third connection line CN3 may include a third driver connection portion CD3 (e.g., CD3a and CD3b) connected to the third pixel driver PDC3 and a third emission connection portion CE3 (e.g., CE3a and CE3b) connected to the third cathode EL2_3.

[0168] The first to third driver connection parts CD1, CD2 and CD3 may be aligned along the first direction DR1. As described above, the first to third driver connection parts CD1, CD2 and CD3 may correspond to positions of connection transistors forming the first to third pixel drivers PDC1, PDC2 and PDC3, respectively. In a pixel, the connection transistor may be a transistor including a pixel driver PDC as one electrode and a connection node to which the emission element LD is connected, and may be connected to, for example, Figure 2A The sixth transistor T6 or Figure 2B According to the embodiment, the shape, position and arrangement of the pixel driver PDC of all pixels can be simply configured and designed regardless of the shape or size of the light emitting parts EP1, EP2 and EP3 and the color of the emitted light.

[0169] In an embodiment, the first to third emission connection parts CE1, CE2 and CE3 may be disposed at positions that do not overlap with the light emitting parts EP1, EP2 and EP3 in a plan view. Figure 7 ) is the emitting element LD (see Figure 7 ) is connected to and defines a tip portion TP therein (see Figure 7 ), so the emission connection part CE may be provided at a position that does not overlap with the light emitting opening OP-PDL. For example, in each of the cathodes EL2_1, EL2_2, and EL2_3, the emission connection parts CE1, CE2, and CE3 may be provided at a position spaced apart from the light emitting parts EP1, EP2, and EP3, and in order to be connected with the connection lines CN1, CN2, and CN3 at the positions where the emission connection parts CE1, CE2, and CE3 are placed, the cathodes EL2_1, EL2_2, and EL2_3 may include a partial area protruding from the light emitting parts EP1, EP2, and EP3 in a plan view.

[0170] For example, in order to connect to the first connection line CN1 at a position where the first emission connection part CE1 is provided, the first cathode EL2_1 may include a protruding portion protruding from the first light emitting part EP1 at a position not overlapping with the first light emitting part EP1, and the first emission connection part CE1 may be provided on the protruding portion.

[0171] For example, the first driver connection portion CD1, which is a position where the first pixel driver PDC1 (e.g., transistor TR) can be connected to the first connection line CN1, can be defined at a position that does not overlap with the first light emitting portion EP1 in a plan view. According to an embodiment, since the first connection line CN1 is provided in the first light emitting portion EP1, the separated first cathode EL2_1 and the first pixel driver PDC1 can be easily connected.

[0172] For example, the third driver connection portion CD3, which is the position where the third pixel driver PDC3 (for example, the transistor TR) is connected to the third connection line CN3, may be limited to a position that does not overlap with the third emission connection portion CE3 in a plan view, and may be provided at a position that overlaps with the third light emitting portion EP3. According to an embodiment, since the third cathode EL2_3 and the third pixel driver PDC3 are connected through the third connection line CN3, in the design of the third pixel driver PDC3, restrictions according to the position or shape of the third light emitting portion EP3 may be reduced, so that the degree of freedom of design may be improved.

[0173] Return to reference Fig. 6A, the light emitting portion of the second row Rk+1 may be composed of a light emitting portion having a shape and arrangement that is symmetrical with the shape and arrangement axis of the light emitting portions of the first row light emitting cells UT11 and UT12 about an axis parallel to the first direction DR1. Due to the characteristics of the shape and arrangement of the first row light emitting cells UT11 and UT12, the second row light emitting cells UT21 and UT22 may be basically composed of light emitting portions formed by shifting the first row light emitting cells UT11 and UT12 in the first direction DR1 and the second direction DR2. For example, the second row first column light emitting cell UT21 may be composed of a light emitting portion having the same shape as the shape of the light emitting portion of the first row second column light emitting cell UT12, and the second row second column light emitting cell UT22 may be composed of a light emitting portion having the same shape as the shape of the light emitting portion of the first row first column light emitting cell UT11.

[0174] Accordingly, the shape and arrangement of the connection wire CN-c disposed in the second row and first column light emitting unit UT21 may be the same as the shape and arrangement of the connection wires CN1b, CN2b, and CN3b disposed in the first row and second column light emitting unit UT12. For example, the shape and arrangement of the connection wire CN-d disposed in the second row and second column light emitting unit UT22 may be the same as the shape and arrangement of the connection wires CN1a, CN2a, and CN3a disposed in the first row and first column light emitting unit UT11.

[0175] refer to Figure 6C , the first electrode EL1 (hereinafter, referred to as an anode) of the emission element LD according to the embodiment may be provided in common to the light emitting parts EP1, EP2, and EP3. For example, the anode EL1 may be formed as a single layer throughout the entire display area DP-A, and accordingly, the anode EL1 layer may overlap with the partition SPR. In another example, the anode EL1 of each of the emission elements LD may be formed as independent conductive patterns spaced apart from each other and may be connected to each other (e.g., electrically connected) through another conductive layer, and accordingly, the pattern of the anode EL1 may be set so as not to overlap with the partition SPR.

[0176] As described above, the first power supply voltage VDD may be applied to the anode EL1, and a common voltage may be provided to all the light emitting parts EP1, EP2, and EP3. The anode EL1 may be connected to the peripheral area DP-NA (see Figure 4A ) in which a first power supply line VDL (see Figure 2A ), or may be connected to the first power line VDL in the display area DP-A, but the embodiment is not limited thereto.

[0177] For example, according to an embodiment, the opening OP-EL1 may be defined / formed in the anode EL1, and the opening OP-EL1 may pass through the anode EL1 layer. The opening OP-EL1 of the anode EL1 layer may be disposed at a position that does not overlap with the light emitting portion EP, and may generally be defined / formed at a position that overlaps with the partition SPR. The opening OP-EL1 may facilitate the removal of light from an organic layer disposed below the anode EL1 (e.g., the sixth insulating layer 60 described below (see Figure 7 Accordingly, the gas generated in the organic layer provided under the emission element LD can be sufficiently released during the manufacturing process of the display panel and the gas released from the organic layer after manufacturing is reduced, and thus the rate at which the emission element LD deteriorates can be reduced.

[0178] According to the embodiment, by including a connection line between the emission element and the pixel driver, the emission element can be easily connected to the pixel driver without changing the arrangement or shape of the light-emitting portion by only changing the shape of the cathode. Accordingly, the design freedom of the arrangement of the pixel driver can be improved, and the area or resolution of the light-emitting portion of the display panel can be easily increased.

[0179] Figure 7 is a schematic cross-sectional view of a display panel DP according to an embodiment. Fig. 8A is an enlarged schematic cross-sectional view of a partial area of ​​the display panel DP according to the embodiment. Figure 8B is an enlarged schematic cross-sectional view of a partial area of ​​the display panel DP according to the embodiment. Figure 7 It is shown along Figure 6B Schematic cross-sectional view of a portion taken along line II'. Fig. 8A Shows Figure 7 An enlarged schematic cross-sectional view of region AA of FIG. Figure 8B Shows Figure 7 Hereinafter, reference will be made to Figures 7 to 8B Embodiments are described.

[0180] refer to Figure 7 , the display panel DP according to the embodiment may include a base layer BS, a driving element layer DDL, an emission element layer LDL, an encapsulation layer ECL, and a detection layer ISL. The driving element layer DDL may include insulating layers 10, 20, 30, 40, and 50 disposed on the base layer BS and conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, and 50. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, and 50 to form a pixel driver PDC. For convenience of description, Figure 7A cross section of a region (eg, a single region) among regions where light emitting portions (eg, a single light emitting portion) are provided is shown.

[0181] The base layer BS may be a member that provides a base surface on which the pixel driver PDC is disposed. The base layer BS may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The base layer BS may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiment is not limited thereto, and the base layer BS may include an inorganic layer, an organic layer, or a composite material layer.

[0182] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0183] The polymer resin layer may include polyimide resins. For example, the polymer resin layer may include at least one of acrylic resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. In the description, "~~" resins mean functional groups including "~~".

[0184] Each of the insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS may be formed by a coating process or a deposition process. Through multiple photolithography processes, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned to form holes in the insulating layer, or semiconductor patterns, conductive patterns, and signal lines may be formed.

[0185] The driving element layer DDL may include first to fifth insulating layers 10 , 20 , 30 , 40 , and 50 and a pixel driver PDC sequentially stacked on the base layer BS. Figure 7 1 and 2. A transistor TR and two capacitors C1 and C2 of the pixel driver PDC are shown. The transistor TR can be connected to a transistor of the emission element LD via a connection line CN (eg, connected to a node corresponding to the cathode of the emission element LD). Figure 2A The fourth node N4 in Figure 2B The second node N2 in the connection transistor) corresponds to the connection transistor) and can be connected to Figure 2A The sixth transistor T6 or Figure 2B For example, the other transistors forming the pixel driver PDC may have the same Figure 7However, this is described as an example, and other transistors forming the pixel driver PDC may have a structure different from that of the connection transistor TR, but the embodiment is not limited thereto.

[0186] The first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 is shown as a single-layer silicon oxide layer. For example, other insulating layers as described below may be inorganic layers and / or organic layers, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the embodiment is not limited thereto.

[0187] For example, the first insulating layer 10 may cover the lower conductive layer BCL. For example, the display panel DP may further include a lower conductive layer BCL disposed to overlap the connection transistor TR. The lower conductive layer BCL may prevent the potential caused by the polarization phenomenon of the base layer BS from affecting the connection transistor TR. For example, the lower conductive layer BCL may prevent light from being incident on the connection transistor TR from the lower side. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BCL and the base layer BS.

[0188] The lower conductive layer BCL may include a reflective metal. For example, the lower conductive layer BCL may include titanium (Ti), molybdenum (Mo), an alloy including Mo, aluminum (Al), an alloy including Al, aluminum nitride (Al2O3), or a plurality of other metals. x N y ), tungsten (W), tungsten nitride (W x N y ) and / or copper (Cu).

[0189] In an embodiment, the lower conductive layer BCL may be connected to other semiconductor patterns (e.g., a source electrode connecting a transistor TR), a gate electrode connecting a transistor TR, etc. For example, the lower conductive layer BCL may be electrically connected to the source electrode connecting the transistor TR. Or, for example, the lower conductive layer BCL may be connected to and synchronized with the gate electrode connecting the transistor TR. In another example, the lower conductive layer BCL may be connected to another electrode to independently receive a constant voltage or a pulse signal. In another example, the lower conductive layer BCL may be provided in a form isolated from other conductive patterns. The lower conductive layer BCL according to an embodiment may be provided in various forms, but the embodiment is not limited thereto.

[0190] The connection transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include an indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) of a transparent conductive oxide (TCO). However, the embodiment is not limited thereto, and the semiconductor pattern SP may include amorphous silicon, low temperature polysilicon, or polycrystalline silicon.

[0191] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR defined according to conductivity. The channel region CR may be a portion overlapping the gate electrode GE in a plan view. The source region SR and the drain region DR may be spaced apart, wherein the channel region CR is between the source region SR and the drain region DR. In the case where the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduction region. Accordingly, the source region SR and the drain region DR have a relatively high reduction metal content compared to the channel region CR. In another example, in the case where the semiconductor pattern SP is polycrystalline silicon, each of the source region SR and the drain region DR may be a region doped with a high concentration.

[0192] The source region SR and the drain region DR may have a conductivity relatively higher than that of the channel region CR. The source region SR may correspond to a source electrode of the connection transistor TR, and the drain region DR may correspond to a drain electrode of the connection transistor TR. Figure 7 As shown in FIG. 1 , separate source electrode patterns W1 and drain electrode patterns W2 connected to the source region SR and the drain region DR, respectively, may be further provided. For example, the separate source electrode patterns W1 and drain electrode patterns W2 may be connected to the pixel drivers PDC and PDC-1, respectively (see FIG. 1 ). Figure 2A and 2B ) is formed integrally with one of the lines, and the embodiment is not limited thereto.

[0193] The second insulating layer 20 may overlap with a plurality of pixels in common and may cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0194] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate electrode of the connection transistor TR. For example, the gate electrode GE may be disposed above the semiconductor pattern SP. However, this is shown as an example, and the gate electrode GE may be disposed below the semiconductor pattern SP, but the embodiment is not limited thereto.

[0195] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (Al x N y ), tungsten (W), tungsten nitride (W x N y ), copper (Cu), or an alloy thereof, but the embodiment is not limited thereto.

[0196] The third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single layer structure or a multilayer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0197] Among the conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first and second capacitor electrodes CPE1 and CPE2 may form a first capacitor C1. The first and second capacitor electrodes CPE1 and CPE2 may be spaced apart with the first and second insulating layers 10 and 20 therebetween.

[0198] In an embodiment, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape. For example, the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0199] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2, wherein the third insulating layer 30 is between the second capacitor electrode CPE2 and the third capacitor electrode CPE3, and the second capacitor electrode CPE2 and the third capacitor electrode CPE3 may overlap in a plan view. The second capacitor electrode CPE2 and the third capacitor electrode CPE3 may form a second capacitor C2.

[0200] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0201] The source electrode pattern W1 and the drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to the source region SR of the connection transistor TR through the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP may serve as the source electrode of the connection transistor TR. The drain electrode pattern W2 may be connected to the drain region DR of the connection transistor TR through the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may serve as the drain electrode of the connection transistor TR. The fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0202] The connection line CN may be disposed on the fifth insulating layer 50. The connection line CN may connect (e.g., electrically connect) the pixel driver PDC and the emission element LD. For example, the connection line CN may connect (e.g., electrically connect) the connection transistor TR and the emission element LD. The connection line CN may be a connection node connecting the pixel driver PDC and the emission element LD. For example, the connection line CN may be connected to Figure 2A The fourth node N4 shown in Figure 2A )or Figure 2B The second node N2 shown in Figure 2B This is illustratively described, and in the case where the connection line CN is connected to the emission element LD, according to the design of the pixel driver PDC, the connection line CN may be defined as a connection node connected to various elements among the elements forming the pixel driver PDC, but the embodiment is not limited thereto.

[0203] The sixth insulating layer 60 may be disposed on the connection line CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the connection line CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer and / or a mixture thereof, etc.

[0204] An opening exposing at least a portion of the connection cloth CN may be provided in the sixth insulating layer 60. The connection line CN may be connected (e.g., electrically connected) to the emission element LD through the portion exposed from the sixth insulating layer 60. For example, the connection line CN may connect (e.g., electrically connect) the connection transistor TR and the emission element LD. A detailed description thereof will be given below. For example, in the display panel DP according to the embodiment, the sixth insulating layer 60 may be omitted or may be provided in plurality, but the embodiment is not limited thereto.

[0205] The emission element layer LDL may be disposed on the sixth insulating layer 60. The emission element layer LDL may include a pixel defining film PDL, an emission element LD, and a spacer SPR. The pixel defining film PDL may be an organic layer. For example, the pixel defining film PDL may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and / or a mixture thereof.

[0206] In an embodiment, the pixel defining film PDL may have a property of absorbing light and may have, for example, a black color. For example, the pixel defining film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining film PDL may correspond to a light blocking pattern having a light blocking property.

[0207] An opening OP-PDL (hereinafter, referred to as a light emitting opening) exposing at least a portion of the first electrode EL1 as described below may be defined in the pixel defining film PDL. A plurality of light emitting openings OP-PDL may be provided and arranged to correspond to a plurality of emission elements LD, respectively. In the light emitting opening OP-PDL, all components of the emission element LD may be overlapped and arranged, and the light emitting opening OP-PDL may be an area in which light emitted by the emission element LD is substantially emitted. Accordingly, the shape of the light emitting portion EP (see FIG. 6 ) may substantially correspond to the shape of the light emitting opening OP-PDL in a plan view.

[0208] The emission element LD may include a first electrode EL1, an intermediate layer IML, and a second electrode EL2. The first electrode EL1 may be a semi-transmissive, transmissive, or reflective electrode. According to an embodiment, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include a layer selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may include a stack structure of ITO / Ag / ITO.

[0209] In an embodiment, the first electrode EL1 may be an anode of the emission element LD. For example, the first electrode EL1 may be connected to a first power line VDL (see Figure 2A ), and the first power supply voltage VDD (see Figure 2A ) may be applied. The first electrode EL1 may be connected to the display region DP-A (see Figure 4A ) or connected to the first power line VDL in the peripheral area DP-NA (see Figure 4A In the latter case, the first power line VDL may be disposed in the peripheral area DP-NA, and the first electrode EL1 may have a shape extending to the peripheral area DP-NA.

[0210] exist Figure 7 In the cross-sectional view of FIG. 1 , the first electrode EL1 may overlap with the light emitting opening OP-PDL and may not overlap with the partition SPR, but as described above with reference to FIG. Figure 6C As described above, the first electrode EL1 of each emission element LD may have an integral shape and may have a mesh or lattice shape in which openings are defined in some areas. For example, in the case where the same first power supply voltage VDD is applied to the first electrode EL1 of each of the emission elements LD, the shape of the first electrode EL1 may be provided in various ways, but the embodiment is not limited thereto.

[0211] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include an emission layer EML and a functional layer FNL. The emission element LD may include an intermediate layer IML of various structures, but the embodiment is not limited thereto. For example, the functional layer FNL may be formed as a plurality of layers or two or more layers spaced apart (with the emission layer EML between the layers). In another example, the functional layer FNL may be omitted.

[0212] The emission layer EML may include an organic light emitting material. For example, the emission layer EML may include an inorganic light emitting material, or may be formed as a mixed layer of an organic light emitting material and an inorganic light emitting material. Figure 6C ) may include luminescent materials that display different colors. For example, the emitting layer EML included in each luminescent portion EP may provide any one of blue light, red light, and green light. However, the embodiment is not limited thereto, and the emitting layer EML provided in all luminescent portions EP may include luminescent materials that emit the same color light. For example, the emitting layer EML may emit blue light or white light. For example, in Figure 7 , the emission layer EML and the functional layer FNL are illustrated as different shapes as an embodiment, but the embodiment is not limited thereto, and the emission layer EML and the functional layer FNL may be provided in the same shape in a plan view.

[0213] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. For example, the functional layer FNL may be disposed between the first electrode EL1 and the emission layer EML or between the second electrode EL2 and the emission layer EML. In another example, the functional layer FNL may be disposed between the first electrode EL1 and the emission layer EML and between the second electrode EL2 and the emission layer EML. In an embodiment, the emission layer EML is shown as being inserted into the functional layer FNL. However, this is shown as an example, and the functional layer FNL may include a layer disposed between the emission layer EML and the first electrode EL1 and / or a layer disposed between the emission layer EML and the second electrode EL2 and the functional layer FNL may be provided in plurality, but the embodiment is not limited thereto.

[0214] The functional layer FNL may control the movement of charges between the first electrode EL1 and the second electrode EL2. The functional layer FNL may include a hole injection / transport material and / or an electron injection / transport material. The functional layer FNL may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0215] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be connected to the connection line CN and connected (eg, electrically connected) to the pixel driver PDC. For example, the second electrode EL2 may be connected (eg, electrically connected) to the connection transistor TR via the connection line CN.

[0216] As described above, the connection line CN may include a driver connection portion CD and an emission connection portion CE. The driver connection portion CD may be a portion of the connection line CN that is connected to the pixel driver PDC and is substantially connected to the connection transistor TR. In an embodiment, the driver connection portion CD may pass through the fifth insulating layer 50 and may be connected (e.g., electrically connected) to the drain region DR of the semiconductor pattern SP through the drain electrode pattern W2. The emission connection portion CE may be a portion of the connection line CN that is connected to the emission element LD. The emission connection portion CE may be defined in an area exposed from the sixth insulating layer 60 and may be a portion to which the second electrode EL2 is connected. For example, the tip portion TP may be defined in the emission connection portion CE.

[0217] Reference Figure 7 and Fig. 8A Describe the emission connection part CE of the connection line CN. Figure 7 and Fig. 8A As shown in , the connection line CN may have a three-layer structure. For example, the connection line CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along a third direction DR3. The second layer L2 may include a material different from that of the first layer L1. For example, the second layer L2 may include a material different from that of the third layer L3. Compared with the first layer L1, the second layer L2 may have a relatively thick thickness. For example, compared with the third layer L3, the second layer L2 may have a relatively thick thickness. The second layer L2 may include a highly conductive material. In an embodiment, the second layer L2 may include aluminum (Al).

[0218] For example, the first layer L1 may include a material having an etching rate lower than that of the second layer L2. For example, the second layer L2 may be composed of a material having a high etching selectivity to the first layer L1. In an embodiment, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). For example, the side surface L1_W of the first layer L1 may be defined outside the side surface L2_W of the second layer L2. For example, the emission connection portion CE of the connection line CN may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. For example, the emission connection portion CE of the connection line CN may have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0219] For example, the third layer L3 may include a material having an etching rate lower than that of the second layer L2. For example, the second layer L2 may be composed of a material having a high etching selectivity for the third layer L3. In an embodiment, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). For example, the side surface L3_W of the third layer L3 may be defined outside the side surface L2_W of the second layer L2. For example, the emission connection portion CE of the connection line CN may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. For example, the emission connection portion CE of the connection line CN may have an undercut shape or an overhang structure, and the tip portion TP of the emission connection portion CE may be defined by a protruding portion of the third layer L3 compared to the second layer L2.

[0220] The sixth insulating layer 60 and the pixel defining film PDL may expose at least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2. For example, a first opening OP1 exposing one end of the connection line CN may be defined in the sixth insulating layer 60, and a second opening OP2 overlapping the first opening OP1 may be defined in the pixel defining film PDL. The plane area / size of the second opening OP2 may be larger than the plane area / size of the first opening OP1. However, the embodiment is not limited thereto, and in the case where at least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2 are exposed, the plane area / size of the second opening OP2 may be less than or equal to the plane area / size of the first opening OP1.

[0221] The intermediate layer IML may be disposed on the pixel definition film PDL. The intermediate layer IML may be disposed on a portion of the sixth insulating layer 60 exposed by the second opening OP2 of the pixel definition film PDL. For example, the intermediate layer IML may be disposed on a portion of the connection line CN exposed by the first opening OP1 of the sixth insulating layer 60. Fig. 8A As shown in , the intermediate layer IML may include one end IN1 provided along the upper surface of the fifth insulating layer 50 and the other end IN2 provided along the upper surface of the tip portion TP. For example, when viewed in a cross-sectional view, the intermediate layer IML may have a shape in which the emission connection portion CE is partially disconnected relative to the tip portion TP as a reference. However, when viewed in a plan view, the intermediate layer IML may have a region defined as a closed line by the partition SPR (see Fig. 6A ) as a one-piece shape connected as a whole.

[0222] For example, one end EN1 of the second electrode EL2 may be disposed along the side surface L2_W of the second layer L2 to contact the side surface L2_W of the second layer L2. For example, by the difference in deposition angles of the second electrode EL2 and the intermediate layer IML, the second electrode EL2 may contact the side surface L2_W of the second layer L2 exposed from the intermediate layer IML through the tip portion TP. For example, the intermediate layer IML may be spaced apart from the side surface L2_W of the second layer L2. For example, the second electrode EL2 may be connected to the connection line CN without a separate patterning process for the intermediate layer IML, and accordingly, the emission element LD may be connected (e.g., electrically connected) to the pixel driver PDC through the connection line CN.

[0223] In an embodiment, although the other end IN2 of the intermediate layer IML and the other end EN2 of the second electrode EL2 are shown as covering the side surface L3_W of the third layer L3, this is shown as an example, and at least a portion of the side surface L3_W of the third layer L3 may be exposed from the other end IN2 of the intermediate layer IML and / or the other end EN2 of the second electrode EL2.

[0224] As described above, the display panel DP may include a spacer SPR. The spacer SPR may be disposed on the pixel defining film PDL. In an embodiment, the second electrode EL2 and the intermediate layer IML may be formed by depositing a plurality of pixels in common by means of an open mask. For example, the second electrode EL2 and the intermediate layer IML may be divided by the spacer SPR. As described above, for each light emitting portion EP, the spacer SPR may have a closed line shape, and thus for each light emitting portion EP, the second electrode EL2 and the intermediate layer IML may have a separated shape. For example, the second electrode EL2 and the intermediate layer IML may be electrically independent of the second electrode EL2 and the intermediate layer IML of adjacent pixels.

[0225] Reference Figure 7 and Figure 8B Describe the separator SPR. Figure 8B As shown in , the spacer SPR may have an inverted tapered shape. For example, the angle θ (e.g., the cone angle below) formed by the side surface SPR_W of the spacer SPR relative to the upper surface of the pixel defining film PDL may be an obtuse angle. However, this is shown as an example, and in the case where the spacer SPR electrically disconnects the second electrode EL2 of each pixel, the cone angle θ may be set in various ways. For example, the spacer SPR may have the same structure as that of the tip portion TP, but the embodiment is not limited thereto.

[0226] In an embodiment, the spacer SPR may include an insulating material, and may include an organic insulating material. According to an embodiment, the spacer SPR may include an inorganic insulating material, may include a multilayer structure of an organic insulating material and an inorganic insulating material, or may include a conductive material. For example, as long as the second electrode EL2 is electrically disconnected for each pixel, the material type of the spacer SPR is not limited.

[0227] The dummy layer UP may be disposed on the spacer SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the spacer SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed by the same process as that of the intermediate layer IML and may include the same materials as each other. The second dummy layer UP2 may be formed by the same process as that of the second electrode EL2 and may include the same materials. For example, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the intermediate layer IML and the second electrode EL2. In another example, the display panel DP may not include the dummy layer UP.

[0228] like Figure 8B As shown in , in the embodiment, the second electrode EL2 may include a first end portion EN1a, and the second dummy layer UP2 may include a second end portion EN2a. The first end portion EN1a may be spaced apart from the spacer SPR and located on the pixel definition film PDL, and the second end portion EN2a may be separated from the first end portion EN1a and located on the side surface SPR_W of the spacer SPR. However, although in Figure 8B The first end EN1a is shown as being spaced apart from the side surface SPR_W of the spacer SPR by a certain distance, but the embodiment is not limited thereto, and in the case where the second end EN2a is electrically disconnected, the first end EN1a may contact the side surface SPR_W of the spacer SPR. For example, in the case where the first end EN1a and the second end EN2a are connected without being distinguished from each other, in the case where the thickness of the portion formed along the side surface SPR_W of the spacer SPR is thin and the resistance is high, in the case where the second electrode EL2 is electrically disconnected between adjacent pixels, the second electrode EL2 may be divided by the spacer SPR.

[0229] According to an embodiment, without a separate patterning process for the second electrode EL2 or the intermediate layer IML, by not forming the second electrode EL2 or the intermediate layer IML on the side surface SPR_W of the separator SPR or by thinly forming the second electrode EL2 or the intermediate layer IML on the side surface SPR_W of the separator SPR, the second electrode EL2 or the intermediate layer IML may be divided for each pixel. For example, in the case where the second electrode EL2 or the intermediate layer IML is electrically disconnected between adjacent pixels, the shape of the separator SPR may be modified variously, but the embodiment is not limited thereto.

[0230] Return to reference Figure 7 , the encapsulation layer ECL may be disposed on the emission element layer LDL. The encapsulation layer ECL may cover the emission element LD and may cover the spacer SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked sequentially. However, the embodiment is not limited thereto, and the encapsulation layer ECL may further include an inorganic layer and an organic layer. For example, the encapsulation layer ECL may be a glass substrate.

[0231] The first inorganic layer IL1 and the second inorganic layer IL2 may protect the emission element LD from moisture and oxygen outside the display panel DP, and the organic layer OL may protect the emission element LD from foreign matter such as particles remaining during the formation of the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer OL may include an acrylic organic layer, and the type of material is not limited thereto.

[0232] The detection layer ISL may detect external input. In an embodiment, the detection layer ISL may be formed on the encapsulation layer ECL by a continuous process. For example, it may be said that the detection layer ISL is directly disposed on the encapsulation layer ECL. "Directly disposed / placed" may mean that no other components are disposed / placed between the detection layer ISL and the encapsulation layer ECL. For example, a separate bonding member may not be disposed between the detection layer ISL and the encapsulation layer ECL. However, this is shown as an example, and in the display panel DP according to the embodiment, the detection layer ISL may be formed separately and connected to the display panel DP by a bonding member, but the embodiment is not limited thereto.

[0233] The detection layer ISL may include a conductive layer and an insulating layer. The conductive layer may include a first detection conductive layer MTL1 and a second detection conductive layer MTL2, and the insulating layer may include first to third detection insulating layers 71, 72, and 73. However, this is shown as an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0234] Each of the first to third detection insulating layers 71, 72 and 73 may have a single-layer structure or a multilayer structure stacked along the third direction DR3. The first to third detection insulating layers 71, 72 and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide. The first to third detection insulating layers 71, 72 and 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin and perylene resin.

[0235] The first detection conductive layer MTL1 may be disposed between the first detection insulating layer 71 and the second detection insulating layer 72, and the second detection conductive layer MTL2 may be disposed between the second detection insulating layer 72 and the third detection insulating layer 73. A portion of the second detection conductive layer MTL2 may be connected to the first detection conductive layer MTL1 through a contact hole CNT formed in the second detection insulating layer 72. Each of the first detection conductive layer MTL1 and the second detection conductive layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0236] The single-layer detection conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium zinc tin oxide (IZTO). In another example, the transparent conductive layer may include conductive polymers such as poly (3,4-ethylenedioxythiophene) (PEDOT), metal nanowires and graphene.

[0237] The detection conductive layer of the multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium (Ti) / aluminum (Al) / titanium (Ti). In another example, the detection conductive layer of the multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0238] In the detection layer ISL, the first detection conductive layer MTL1 and the second detection conductive layer MTL2 may form a sensor for detecting an external input. The sensor may be driven by a capacitive method, and may be driven by any one of a mutual capacitance method and a self-capacitive method. However, this is described as an example, and in addition to the capacitive method, the sensor may be driven by a resistive film method, an ultrasonic method, or an infrared method, but the embodiment is not limited thereto.

[0239] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide, or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and various shapes as long as visibility of an image displayed by the display panel DP may not be degraded, but the embodiment is not limited thereto.

[0240] Fig. 9A is a schematic plan view of a display panel according to an embodiment. Fig. 9B is a schematic cross-sectional view of a display panel according to an embodiment. Fig. 9A The display panel DP-1 is shown with Figure 6C The corresponding schematic diagram, and Fig. 9B The display panel DP-1 is shown with Figure 7 In the following, reference will be made to Fig. 9A and Fig. 9B The same reference numerals are assigned to the Figures 1 to 8B The configurations described are the same configurations, and for the convenience of description, redundant descriptions will be omitted.

[0241] like Fig. 9A and Fig. 9B As shown in Figure 7 , the display panel DP-1 may further include a cover pattern CPP. The cover pattern CPP may be disposed on the sixth insulating layer 60. For example, the cover pattern CPP may be disposed on a portion of the connection line CN that is exposed through the first opening OP1 of the sixth insulating layer 60. The cover pattern CPP may overlap the connection line CN, and may overlap the emission connection portion CE and / or the tip portion TP.

[0242] The cap pattern CPP may have a shape in which the connection based on the tip portion TP is partially disconnected in the region defining the emission connection portion CE, and may have a shape in the region defined as a closed line by the partition SPR when viewed in a plan view (see Fig. 6A ) as an integrated shape connected as a whole within the emission connection portion CE. For example, the cap pattern CPP may have an integrated shape but may include a portion that is disconnected at the emission connection portion CE. For example, one end of the partially disconnected cap pattern CPP may contact the side surface of the second layer L2 of the connection line CN, and the other end of the cap pattern CPP may be disposed on the third layer L3 of the connection line CN to cover the tip portion TP.

[0243] The cover pattern CPP may include a conductive material. Accordingly, the second electrode EL2 may be connected (e.g., electrically connected) to the connection line CN through the cover pattern CPP. For example, the cover pattern CPP may contact the side surface of the second layer L2 of the connection line CN, and the second electrode EL2 may contact the cover pattern CPP to connect all of them (e.g., electrically connected). The cover pattern CPP may be disposed on the relatively outer side of the second layer L2 of the connection line CN, and the second electrode EL2 may be connected (e.g., electrically connected) to the second layer L2 only by connecting to the cover pattern CPP instead of the side surface of the second layer L2, so that the connection between the connection line CN and the second electrode EL2 can be made more easily.

[0244] For example, the cap pattern CPP may include a material having relatively low reactivity compared to the second layer L2 of the connection line CN. For example, the cap pattern CPP may include copper (Cu), silver (Ag), or a transparent conductive oxide, etc. Since the side surface of the second layer L2 of the connection line CN is protected by the cap pattern CPP having relatively low reactivity, oxidation of the material included in the second layer L2 can be prevented. For example, during the etching process of patterning the first electrode EL1, the silver (Ag) component included in the first electrode EL1 layer may be reduced, and it can be prevented from remaining as particles causing defects.

[0245] In an embodiment, the capping pattern CPP and the first electrode EL1 may be formed by the same process and may include the same material. Fig. 9A As shown in , the cap pattern CPP and the first electrode EL1 may be disposed on the same layer (e.g., the sixth insulating layer 60) and may be formed of the same material. A plurality of cap patterns CPP may be provided, may be disposed on the corresponding emission connection portions CE, and may be spaced apart from the integrally formed first electrode EL1 in a plan view to be electrically separated from the first electrode EL1. However, this is described illustratively, and the cap pattern CPP may be formed by a process different from that of the first electrode EL1, or may include a material different from that of the first electrode EL1, but the embodiment is not limited thereto.

[0246] Fig. 10A yes Figure 5A An enlarged schematic plan view of a portion 10A. Fig. 10B yes Fig. 10A An enlarged schematic plan view of portion 200A. Fig. 10C is a schematic plan view of a display panel according to an embodiment.

[0247] refer to Fig. 10A, the first group of pixels PX-A may include a first region light emitting portion EP-A and a first region pixel driver PDC-A connected (e.g., electrically connected) to the first region light emitting portion EP-A. The second group of pixels PX-B may include a second region light emitting portion EP-B and a second region pixel driver PDC-B connected (e.g., electrically connected) to the second region light emitting portion EP-B, and the third group of pixels PX-C may include a third region light emitting portion EP-C and a third region pixel driver PDC-C connected (e.g., electrically connected) to the third region light emitting portion EP-C.

[0248] The first region light emitting part EP-A may be disposed in the first region DP-A1, and the first region pixel driver PDC-A may be disposed in the second region DP-A2. The second region light emitting part EP-B and the second region pixel driver PDC-B may be disposed in the second region DP-A2. The third region light emitting part EP-C and the third region pixel driver PDC-C may be disposed in the third region DP-A3.

[0249] According to an embodiment, by moving the first area pixel driver PDC-A from the first area DP-A1 to the second area DP-A2, the transmittance of the first area DP-A1 can be higher than the transmittance of the second area DP-A2. In the case of removing a light blocking structure such as a transistor, the occupancy rate of the transmission area can be increased, and as a result, the transmittance of the first area DP-A1 can be increased.

[0250] Fig. 10A Two types of first region pixels PX-A are shown as examples. The first region pixel PX-AH may include a first region light emitting portion EP-AH disposed to be spaced apart from the first region pixel driver PDC-AH in the first direction DR1. Another first region pixel PX-AV may include a first region light emitting portion EP-AV disposed to be spaced apart from the first region pixel driver PDC-AV in the second direction DR2. For example, like the first region pixel PX-AH disposed on the left side of the center of the first region DP-A1, the first region pixel PX-A disposed on the right side of the center of the first region DP-A1 may have an arrangement relationship between the first region light emitting portion EP-AH and the first region pixel driver PDC-AH. For example, like the first group of pixels PX-AV disposed on the upper side of the center of the first region DP-A1, the first region pixel PX-A disposed on the lower side of the center of the first region DP-A1 may have an arrangement relationship between the first region light emitting portion EP-AV and the first region pixel driver PDC-AV.

[0251] In order to ensure the area where the first area pixel driver PDC-A is disposed in the second area DP-A2, fewer second area light emitting parts EP-B may be disposed compared to the third area light emitting parts EP-C within the reference area. For example, the first area pixel driver PDC-A may be disposed in an area where the second area pixel driver PDC-B is not disposed in the second area DP-A2.

[0252] The first region light emitting part EP-A can be connected (e.g., electrically connected) to the first region pixel driver PDC-A through a connection line CN-A. The upper connection line CN-AV connecting the first region light emitting part EP-AV disposed on the upper side and the first region pixel driver PDC-AV and the left connection line CN-AH connecting the first region light emitting part EP-AH disposed on the left side and the first region pixel driver PDC-AH are shown as examples. The upper connection line CN-AV and the left connection line CN-AH can extend in different directions. However, this is shown by way of example, and in an embodiment, the connection line CN-A can extend to the inside of the first region DP-A1 and can be connected to the first region light emitting part EP-A. However, this is shown as an example, and the connection part with the first region light emitting part EP-A can be arranged along the boundary between the first region DP-A1 and the second region DP-A2, or can be arranged in the second region DP-A2, or can be arranged in the first region DP-A1 and the second region DP-A2 in a distributed manner. The connection position of the connection line CN-A and the first region light emitting part EP-A can be designed in various arrangement relationships, but the embodiment is not limited thereto.

[0253] exist Fig. 10B , the cathode (or second electrode) of the emission element, the light-emitting parts EP-A, EP-B and EP-C, the separators SPR-A, SPR-B and SPR-C, and the emission connection parts CE-A, CE-B and CE-C are shown. In order to improve the transmittance of the first region DP-A1, within the reference area, fewer first region light-emitting parts EP-A can be set compared with the third region light-emitting parts EP-C. For example, the resolution of the first region DP-A1 can be about 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9 or 1 / 16 of the resolution of the third region DP-A3. For example, the resolution of the third region DP-A3 can be about 400ppi or more, and the resolution of the first region DP-A1 can be about 200ppi or about 100ppi. However, this is only an example, and the embodiment is not limited thereto.

[0254] In an embodiment, the first region light emitting portion EP-A may have a planar shape different from that of the second region light emitting portion EP-B or the third region light emitting portion EP-C. Fig. 10B As shown in the figure, the first area light emitting portion EP-A may have a circular shape in a plan view, and the second area light emitting portion EP-B or the third area light emitting portion EP-C may have a rectangular shape (or a rectangular shape with rounded corners) in a plan view. However, this is shown as an example, and the first area light emitting portion EP-A may have the same shape as the second area light emitting portion EP-B or the third area light emitting portion EP-C, but the embodiment is not limited thereto.

[0255] For the convenience of description, Fig. 10B The reference symbols of six first area light emitting parts EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b and EP-A3b among the first area light emitting parts EP-A are shown. The six first area light emitting parts EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b and EP-A3b may be light emitting parts forming the same pixel row.

[0256] Among the six first area light-emitting parts EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b and EP-A3b, three first area light-emitting parts EP-A1a, EP-A2a and EP-A3a can form a light-emitting part (for example, a single light-emitting part), and the remaining three first area light-emitting parts EP-A1b, EP-A2b and EP-A3b can form another light-emitting part. For example, the first area light-emitting parts EP-A1a and EP-A1b in the first area DP-A1, the second area light-emitting part EP-B1 in the second area DP-A2, and the third area light-emitting part EP-C1 in the third area DP-A3 can emit lights of corresponding colors to each other, the first area light-emitting parts EP-A2a and EP-A2b in the first area DP-A1, the second area light-emitting part EP-B2 in the second area DP-A2, and the third area light-emitting part EP-C2 in the third area DP-A3 can emit lights of corresponding colors to each other, and the first area light-emitting parts EP-A3a and EP-A3b in the first area DP-A1, the second area light-emitting part EP-B3 in the second area DP-A2, and the third area light-emitting part EP-C3 in the third area DP-A3 can emit lights of corresponding colors to each other.

[0257] In an embodiment, the area occupied by the light-emitting portion in the first region DP-A1 may be smaller than the area occupied by the light-emitting portion in the second region DP-A2, and may be smaller than the area occupied by the light-emitting portion in the third region DP-A3. For example, the width in the second direction DR2 occupied by a pixel row in the first region DP-A1 in which six first region light-emitting portions EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b, and EP-A3b are arranged may correspond to the width in the second direction DR2 occupied by two pixel rows in the second region DP-A2. For example, the width in the first direction DR1 occupied by a light-emitting portion in the first region DP-A1 in which three first region light-emitting portions EP-A1a, EP-A2a, and EP-A3a or EP-A1b, EP-A2b, and EP-A3b are arranged may substantially correspond to the width in the first direction DR1 occupied by two light-emitting portions in the third region DP-A3. For example, an area in which the first region light-emitting parts EP-A are arranged in one row and two columns may correspond to an area in which the third region light-emitting parts EP-C are arranged in two rows and four columns. Accordingly, the area occupied by the light-emitting parts in the first region DP-A1 may be reduced compared to the second region DP-A2 or the third region DP-A3, so that the transmittance of the first region DP-A1 may be increased compared to the other regions DP-A2 and DP-A3. However, this is shown as an example and in the case where the transmittance of the first region DP-A1 is higher than the transmittance of the other regions DP-A2 and DP-A3, the shapes and arrangements of the first region light-emitting parts EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b and EP-A3b may be changed differently, and the embodiment is not limited thereto.

[0258] As described above, the second electrodes EL2-A, EL2-B, and EL2-C may be divided by separators SPR-A, SPR-B, and SPR-C, respectively. The first region second electrode EL2-A may be divided by the first region separator SPR-A, and may be arranged overlapping with each first region light emitting portion EP-A. The second region second electrode EL2-B may be divided by the second region separator SPR-B, and may be arranged overlapping with each second region light emitting portion EP-B. The third region second electrode EL2-C may be divided by the third region separator SPR-C, and may be arranged overlapping with each third region light emitting portion EP-C.

[0259] The first to third region separators SPR-A, SPR-B and SPR-C may have an integral shape connected to each other. However, the first to third region separators SPR-A, SPR-B and SPR-C may divide the second electrodes EL2-A, EL2-B and EL2-C of each region DP-A1, DP-A2 and DP-A3 into independent shapes in a plan view. For example, the first region separator SPR-A of the first region DP-A1 may have a shape different from the shape of the second region separator SPR-B of the second region DP-A2 or the shape of the third region separator SPR-C of the third region DP-A3. Accordingly, the first region second electrode EL2-A may be divided into a shape and arrangement different from the shape and arrangement of the second region second electrode EL2-B or the third region second electrode EL2-C. The second region separator SPR-B and the third region separator SPR-C may have the same shape. Accordingly, the second region second electrode EL2-B and the third region second electrode EL2-C may be divided into shapes and arrangements corresponding to each other. This is shown as an example and in the case where the second electrodes EL2-A, EL2-B and EL2-C of each region DP-A1, DP-A2 and DP-A3 are divided, the first to third region separators SPR-A, SPR-B and SPR-C can be independently designed for each region DP-A1, DP-A2 and DP-A3, and the embodiment is not limited thereto.

[0260] Fig. 10B 1 and 2 are respectively shown. As described above, the emission connection portions CE-A, CE-B and CE-C may be provided to the corresponding second electrodes EL2-A, EL2-B and EL2-C, respectively. Each of the emission connection portions CE-A, CE-B and CE-C may be an end of a connection line connecting the corresponding pixel driver and the second electrode. The arrangement of the emission connection portion CE-B of the second area DP-A2 may be the same as that of the second area DP-A2. Fig. 6A The arrangement of the emission connection parts CE-C of the third area DP-A3 may correspond to the arrangement of the emission connection parts CE1, CE2 and CE3. Fig. 6A The arrangement of the transmission connection parts CE1, CE2 and CE3 corresponds to the above.

[0261] The emission connection portion CE-A of the first region DP-A1 may have an arrangement different from the arrangement of the emission connection portion CE-B of the second region DP-A2 or the arrangement of the emission connection portion CE-C of the third region DP-A3. The emission connection portion CE-A of the first region DP-A1 may be arranged along a boundary between the first region DP-A1 and the second region DP-A2. Along the boundary between the first region DP-A1 and the second region DP-A2 defined by extending in a direction parallel to the second direction DR2, Fig. 10B It is shown in FIG. 1 that the emission connection portions CE-A of the first region DP-A1 are arranged in a direction parallel to the second direction DR2.

[0262] The emission connection portion CE-A of the first area DP-A1 can be formed by a connection line CN (see Fig. 6A ), and by arranging the emission connection part CE-A of the first area DP-A1 as close as possible to the second area DP-A2, the length of the connection line CN connected to the pixel driver provided in the second area DP-A2 of the first area DP-A1 can be minimized. Accordingly, the power consumption for driving the first area light emitting part EP-A in the first area DP-A1 can be reduced.

[0263] For example, by arranging the emission connection portion CE-A of the first region DP-A1 as close as possible to the second region DP-A2, the connection line CN can be prevented from being set in the first region DP-A1. Accordingly, interference between the light passing through the first region DP-A1 and the connection line CN can be prevented, and in the case where the connection line CN is opaque, the problem in which the transmittance in the first region DP-A1 is reduced due to the connection line CN can be prevented. This is shown as an example, and the emission connection portion CE-A of the first region DP-A1 can be formed in various positions as long as the emission connection portion CE-A can be provided to the first region second electrode EL2-A of the first region DP-A1, and the embodiment is not limited thereto.

[0264] refer to Fig. 10C , the first area pixel driver PDC-A may be disposed in the fourth area except the first area DP-A1, the second area DP-A2, and the third area DP-A3. For example, the first area pixel PX-AN may include the first area pixel driver PDC-AN and the first area light emitting portion EP-AN. Fig. 10CAs shown in , the first area pixel driver PDC-AN can be set in the peripheral area DP-NA. For example, the connection line CN-AN connecting the first area pixel driver PDC-AN and the first area light-emitting part EP-AN can overlap with the first area DP-A1, the second area DP-A2, the third area DP-A3 and the peripheral area DP-NA. In the display panel according to the embodiment, the first area light-emitting parts EP-A and EP-AN and the first area pixel drivers PDC-A and PDC-AN set in the area other than the first area DP-A1 can be connected by the connection lines CN-A and CN-AN. Accordingly, an optically opaque pixel driver can be prevented from being set in the first area DP-A1, thereby providing a display panel including the first area DP-A1 with high transmittance.

[0265] Fig.11A and Fig. 11B is a schematic plan view of a display panel according to an embodiment. Fig.11A and Fig. 11B Schematic plan views of different layers are shown. For example, Fig.11A is a schematic plan view of a layer on which the first electrodes EL1-A, EL1-B, and EL1-C are provided, and Fig. 11B is a schematic plan view of a layer on which the second electrodes EL2-A, EL2-B, and EL2-C are provided. For example, Fig.11A and Fig. 11B Shown with Fig. 10B The area corresponding to the area of ​​, and the corresponding light emitting parts EP-A, EP-B and EP-C are shown with dotted lines. In the following, for the convenience of description, redundant description will be omitted.

[0266] like Fig.11A As shown in FIG. 1 , the first electrode EL1-A of the first region DP-A1 disposed in the first region DP-A1, the first electrode EL1-B of the second region DP-A2 disposed in the second region DP-A2, and the first electrode EL1-C of the third region DP-A3 disposed in the third region DP-A3 may be provided in an integral shape connected to each other. The first electrode EL1-B of the second region DP-A2 and the first electrode EL1-C of the third region DP-A3 may have a shape similar to that of FIG. Figure 6C The shape of the first electrode EL1 shown in FIG.

[0267] The first electrode EL1-A of the first region DP-A1 disposed in the first region DP-A1 may include a first portion P1 and a second portion P2. The first portion P1 and the second portion P2 may have an integral shape connected to each other. The first portion P1 may be provided in plurality and may be arranged to overlap each of the first region light emitting portions EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b, and EP-A3b. The first portion P1 is shown in a circular shape identical to that of the corresponding light emitting portion, but the embodiment is not limited thereto, and the first portion P1 may be provided in various shapes as long as the first portion P1 may overlap the entire corresponding light emitting portion.

[0268] The second portion P2 may connect the adjacent first portion P1. For example, the second portion P2 may connect the adjacent first portion P1 and the first electrode EL1-B of the second region DP-A2. The second portion P2 may have a strip shape, but the embodiment is not limited thereto. According to an embodiment, since the first electrode EL1-A of the first region DP-A1 includes the first portion P1 and the second portion P2, the area occupied within the first region DP-A1 may be minimized. Accordingly, in the region other than the first region light emitting portions EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b, and EP-A3b in the first region DP-A1, since the area in which the optically opaque first electrode EL1-A is disposed is minimized, the light transmittance of the first region DP-A1 may be improved.

[0269] like Fig. 11B As shown in, each of the second electrodes EL2-A, EL2-B and EL2-C can be provided in a plurality of divided patterns. As described above, the second electrodes EL2-A, EL2-B and EL2-C can be divided by separators SPR-A, SPR-B and SPR-C. In another example, some of the second electrodes EL2-A, EL2-B and EL2-C can be patterned and formed by separate masks.

[0270] For the convenience of description, Fig. 11BConnection lines CN-A, CN-B and CN-C, emission connection parts CE-A, CE-B and CE-C, and driver connection parts CD-A, CD-B and CD-C are shown together. As described above, the emission connection parts CE-A, CE-B and CE-C may be parts of the connection lines CN-A, CN-B and CN-C connected to the second electrodes EL2-A, EL2-B and EL2-C, and the driver connection parts CD-A, CD-B and CD-C may be parts of the connection lines CN-A, CN-B and CN-C connected to the pixel drivers PDC-A, PDC-B and PDC-C. In order to distinguish from the emission connection parts CE-A, CE-B and CE-C, the driver connection parts CD-A, CD-B and CD-C are each shown in a circular shape.

[0271] The three third region second electrodes EL2-C1, EL2-C2, and EL2-C3 belonging to one light emitting portion among the third region second electrodes EL2-C disposed in the third region DP-A3 may overlap with the three third region pixel drivers PDC-C belonging to the corresponding light emitting portion in a plan view. Based on one light emitting portion, the third region second electrodes EL2-C1, EL2-C2, and EL2-C3 and the third region pixel driver PDC-C may be disposed within the boundary range of the light emitting portion and may overlap with each other.

[0272] The third area connection line CN-C may connect the corresponding third area second electrode EL2-C among the third area second electrodes EL2-C1, EL2-C2, and EL2-C3 to the third area pixel driver PDC-C. The third area connection lines CN-C may be spaced apart in a plan view so as not to interfere with each other. The average length of the third area connection lines CN-C in the third area DP-A3 may be relatively shorter than the average length of the first area connection lines CN-A in the first area DP-A1 or the second area connection lines CN-B in the second area DP-A2.

[0273] The three second region second electrodes EL2-B1, EL2-B2, and EL2-B3 belonging to the light emitting portion (e.g., a single light emitting portion) among the second region second electrodes EL2-B disposed in the second region DP-A2 may be spaced apart from the three second region pixel drivers PDC-B belonging to the corresponding light emitting portion in a plan view. For example, based on one light emitting portion, the second region second electrodes EL2-B1, EL2-B2, and EL2-B3 and the second region pixel driver PDC-B may be partially shifted in the first direction DR1.

[0274] The second area connection line CN-B may connect the corresponding second area second electrode EL2-B among the second area second electrodes EL2-B1, EL2-B2, and EL2-B3 to the second area pixel driver PDC-B. The second area connection lines CN-B may be spaced apart from each other in a plan view so as not to interfere with each other. The average length of the second area connection lines CN-B in the second area DP-A2 may be relatively longer than the average length of the third area connection lines CN-C in the third area DP-A3.

[0275] The first region second electrodes EL2-A1a, EL2-A2a, EL2-A3a, EL2-A1b, EL2-A2b and EL2-A3b disposed in the first region DP-A1 may be spaced apart from the corresponding first region pixel drivers PDC-A in a plan view. In an embodiment, among the pixel drivers PDC-A and PDC-B disposed along the first direction DR1 in the second region DP-A2, three first region pixel drivers PDC-A adjacent to the first region DP-A1 may be pixel drivers connected to the first region second electrodes EL2-A1a, EL2-A2a, EL2-A3a, EL2-A1b, EL2-A2b and EL2-A3b disposed in the first region DP-A1. For example, among the pixel drivers PDC-A and PDC-B set in the second area DP-A2, the first area pixel driver PDC-A of three columns adjacent to the first area DP-A1 can be connected to the first area second electrodes EL2-A1a, EL2-A2a, EL2-A3a, EL2-A1b, EL2-A2b and EL2-A3b of the first area DP-A1, and the second area pixel drivers PDC-B of the remaining columns can be connected to the second area second electrodes EL2-B1, EL2-B2 and EL2-B3 of the second area DP-A2.

[0276] In an embodiment, both the first area connection line CN-A and the second area connection line CN-B may be disposed in the second area DP-A2. The second area connection line CN-B may connect the corresponding second area second electrode EL2-B among the second area second electrodes EL2-B1, EL2-B2, and EL2-B3 to the second area pixel driver PDC-B. One end of the second area connection line CN-B may be the second area driver connection portion CD-B of the second area DP-A2, and the other end of the second area connection line CN-B may be the emission connection portion CE-B of the second area DP-A2. The second area connection lines CN-B may be spaced apart from each other in a plan view so as not to interfere with each other. The average length of the second area connection line CN-B in the second area DP-A2 may be relatively longer than the average length of the third area connection line CN-C in the third area DP-A3.

[0277] The first area connection line CN-A may connect the corresponding first area second electrode EL2-A among the first area second electrodes EL2-A1a, EL2-A2a, EL2-A3a, EL2-A1b, EL2-A2b, and EL2-A3b to the first area pixel driver PDC-A. One end of the first area connection line CN-A may be the first area driver connection part CD-A of the first area DP-A1, and the other end of the first area connection line CN-A may be the emission connection part CE-A of the first area DP-A1. The first area connection lines CN-A may be spaced apart from each other in a plan view so as not to interfere with each other. Accordingly, the order in which the first area driver connection part CD-A is arranged along the first direction DR1 and the order in which the second area driver connection part CD-B is arranged along the first direction DR1 may be different from each other. However, this is shown as an example, and the order in which the first area driver connection parts CD-A are arranged along the first direction DR1 and the order in which the second area driver connection parts CD-B are arranged along the first direction DR1 may be designed to be identical to each other according to the shapes of the first area second electrodes EL2-A1a, EL2-A2a, EL2-A3a, EL2-A1b, EL2-A2b and EL2-A3b, the position of the emission connection part CE-A in the first area DP-A1, or the interlayer position of the first area connection line CN-A, and the embodiment is not limited thereto.

[0278] For example, in an embodiment, the first area driver connection portion CD-A may be arranged relatively adjacent to the first area DP-A1 compared to the second area driver connection portion CD-B. Accordingly, the length of the first area connection line CN-A may be minimized, so that the electrical driving efficiency of the first area light emitting portion EP-A may be improved. However, this is shown as an example, and in the case where the first area driver connection portion CD-A is placed in an area other than the first area DP-A1, the first area driver connection portion CD-A may be disposed between the second area driver connection portions CD-B or may be disposed in the peripheral area DP-NA (see Fig. 10C ), but the embodiments are not limited thereto.

[0279] Fig.12 is a schematic plan view of a display panel according to an embodiment. Fig.12 The first electrode is shown, and the Fig.11A In the following, reference will be made to Fig.12 The embodiments are described, and for the convenience of description, redundant descriptions will be omitted.

[0280] refer to Fig.12, the first region first electrode EL1-A1 of the first region DP-A1 may include a first pattern P11 and a connection pattern BRC. The first pattern P11 and the connection pattern BRC may be provided at different layers. For convenience of description, the first pattern P11 and the connection pattern BRC provided at different layers are shown with different shadows.

[0281] The first pattern P11 may be disposed at the same layer as the second region first electrode EL1-B in the second region DP-A2 or the third region first electrode EL1-C in the third region DP-A3. The second region first electrode EL1-B in the second region DP-A2 and the third region first electrode EL1-C in the third region DP-A3 may have an integral shape. The first pattern P11 may be spaced apart from the second region first electrode EL1-B in the second region DP-A2 and the third region first electrode EL1-C in the third region DP-A3.

[0282] The connection pattern BRC may connect (e.g., electrically connect) the first pattern P11 and the second region first electrode EL1-B of the second region DP-A2. Accordingly, the first pattern P11 and the second region first electrode EL1-B of the second region DP-A2 may receive substantially the same voltage. The connection pattern BRC and the first pattern P11 may be disposed at different layers, respectively. For example, the connection pattern BRC may be disposed at a position corresponding to the connection line CN (see Figure 7 ), the first capacitor electrode CPE1 (see Figure 7 ), the second capacitor electrode CPE2 (see Figure 7 ), the third capacitor electrode CPE3 (see Figure 7 ), source electrode pattern W1 (see Figure 7 ), semiconductor pattern SP (see Figure 7 ) and the lower conductive layer BCL (see Figure 7 ). In another example, an additional insulating layer may be further provided and may be provided at a layer different from the layer of the above-mentioned conductive patterns W1, W2, CPE1, CPE2, CPE3, and BCL. The connection pattern BRC may be provided at various layers as long as the connection pattern BRC is provided at a layer different from the layer of the first pattern P11 or the second region first electrode EL1-B of the second region DP-A2, but the embodiment is not limited thereto.

[0283] The connection pattern BRC may have a mesh shape. For example, the connection pattern BRC may include a wire extending in the first direction DR1 and a wire extending in the second direction DR2. The wires may have an integral shape connected to each other. The first pattern P11 may be connected to or contact (e.g., directly contact) the connection pattern BRC through a contact hole. In a cross-sectional view, the connection pattern BRC may be disposed above or below the first pattern P11. In the case where the connection pattern BRC overlaps with the first pattern P11 in a plan view and electrically connects the first pattern P11 to the second region first electrode EL1-B of the second region DP-A2, the connection pattern BRC may have various shapes, but the embodiment is not limited thereto.

[0284] The connection pattern BRC may be optically transparent. Accordingly, in the case where the connection pattern BRC is disposed in the first area DP-A1, the optical influence on the first area DP-A1 may be small. In another example, the connection pattern BRC may be optically opaque. For example, by forming the connection pattern BRC in a grid shape, the actual area occupied in the first area DP-A1 may be minimized, and interference with respect to the degree of visibility to the user or the amount of light passing through the first area DP-A1 may be minimized.

[0285] According to an embodiment, the first pattern P11 may be disposed only at a position overlapping with the first region light emitting portions EP-A1a, EP-A2a, EP-A3a, EP-A1b, EP-A2b, and EP-A3b in the first region DP-A1, and a grid-shaped connection pattern BRC may be disposed in the remaining region, so that the area occupied by the first pattern P11 in the first region DP-A1 may be reduced. Accordingly, in the case where the first pattern P11 is optically opaque, the first region DP-A1 having improved light transmittance may be provided.

[0286] Fig.13A and Fig. 13B is an enlarged schematic plan view of a portion of a display panel according to an embodiment. Fig.13A and Fig. 13B Shown with Fig. 10A The area corresponding to the area where some components are added Fig.13A and Fig. 13B In the following, reference will be made to Fig.13A and Fig. 13B The embodiments are described, and for the convenience of description, redundant descriptions will be omitted.

[0287] like Fig.13AAs shown in, the two types of first region pixels PX-AH and PX-AV may include first region light emitting parts EP-AH and EP-AV connected by first region connecting lines CN-AH and CN-AV and first region pixel drivers PDC-AH and PDC-AV, respectively. The first region connecting lines CN-AH and CN-AV may be connected to the first region light emitting parts EP-AH and EP-AV through emission connecting parts CE-AH and CE-AV connected to the first region second electrodes EL2-AH and EL2-AV. For example, the emission connecting parts CE-AH and CE-AV may be arranged along the boundary between the first region DP-A1 and the second region DP-A2. The first region second electrodes EL2-AH and EL2-AV of the first region DP-A1 may be arranged in the first region DP-A1, and the first region connecting lines CN-AH and CN-AV may be arranged in the second region DP-A2. According to an embodiment, the first region connecting lines CN-AH and CN-AV may not overlap with the first region DP-A1.

[0288] like Fig. 13B As shown in, in each of the two types of first area pixels PX-AH1 and PX-AV1, the first area light emitting parts EP-AH1 and EP-AV1 can be connected to the first area pixel drivers PDC-AH and PDC-AV via the first area DP-A1 through the first area connecting lines CN-AH1 and CN-AV1. In an embodiment, the emission connection parts CE-AH1 and CE-AV1 can be arranged in the first area DP-A1. Accordingly, the first area connecting lines CN-AH1 and CN-AV1 can extend from the second area DP-A2 to the first area DP-A1. By providing the emission connection parts CE-AH1 and CE-AV1 in the first area DP-A1, the first area connecting lines CN-AH1 and CN-AV1 can overlap with the first area DP-A1, but the area occupied by the first area second electrodes EL2-AH1 and EL2-AV1 in the first area DP-A1 can be reduced.

[0289] According to an embodiment, the first region pixels PX-AH, PX-AV, PX-AH1, and PX-AV1 may be connected to the first region pixel drivers PDC-AH and PDC-AV disposed in the second region DP-A2 through the first region connection lines CN-AH, CN-AV, CN-AH1, and CN-AV1. Therefore, since the first region pixel drivers PDC-AH and PDC-AV corresponding to the light blocking structure are disposed in the first region DP-A1 in a non-overlapping manner, a display panel including the first region DP-A1 having a relatively high light transmittance may be provided.

[0290] According to the embodiment, the area of ​​the emitting element in the region where the electronic optical module is disposed can be reduced, and accordingly, the light transmittance of the region where the electronic optical module is disposed can be improved.

[0291] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without substantially departing from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display panel, comprising: a first pixel including a first light emitting portion disposed in a first region and a first pixel driver disposed in a second region different from the first region; a second pixel including a second light emitting portion disposed in the second region and a second pixel driver disposed in the second region; a first connecting line, connecting the first light emitting part and the first pixel driver; as well as A second connecting line connects the second light emitting part and the second pixel driver, wherein: Each of the first connection line and the second connection line includes: a driver connecting portion connected to a corresponding pixel driver of the first pixel driver and the second pixel driver; and an emission connection portion spaced apart from the driver connection portion and connected to the second electrode, and The first region has a light transmittance higher than that of the second region.

2. The display panel according to claim 1, wherein: In a plan view, the first pixel driver and the second pixel driver do not overlap with the first area, The emission connection portion of the first connection line is arranged along a boundary between the first area and the second area, The emission connection portion of the first connection line is arranged in the first region, and In the plan view, the first connection line overlaps with the first region.

3. The display panel according to claim 1, wherein: Each of the first light emitting portion and the second light emitting portion comprises: a first electrode; an intermediate layer, disposed on the first electrode; and A second electrode is disposed on the intermediate layer, The first electrode is an anode, The second electrode is a cathode, In a cross-sectional view, each of the first connection line and the second connection line has an undercut shape, The second electrode of the first light emitting portion contacts a side surface of the first connecting line, and The intermediate layer of the first light emitting portion is spaced apart from the side surface of the first connecting line.

4. The display panel according to claim 1, further comprising: A partition is provided between the first light emitting portion and the second light emitting portion, wherein: Each of the first light emitting portion and the second light emitting portion comprises: a first electrode; an intermediate layer, disposed on the first electrode; and A second electrode is disposed on the intermediate layer, The second electrode of the first light emitting portion and the second electrode of the second light emitting portion are separated from each other by the partition, The shape of the partition provided in the first region in a plan view and the shape of the partition provided in the second region in the plan view are different from each other, and The number of the second electrodes per unit area in the first region is smaller than the number of the second electrodes per unit area in the second region.

5. The display panel according to claim 1, wherein: Each of the first light emitting portion and the second light emitting portion comprises: a first electrode; an intermediate layer, disposed on the first electrode; and A second electrode is disposed on the intermediate layer, The first connection line is connected to a driving transistor of the first pixel driver, The second connection line is connected to a driving transistor of the second pixel driver, and The first electrode of the first light emitting portion is integral with the first electrode of the second light emitting portion.

6. The display panel according to claim 1, wherein: Each of the first light emitting portion and the second light emitting portion comprises: a first electrode; an intermediate layer, disposed on the first electrode; and A second electrode is disposed on the intermediate layer, The first electrode of the first light emitting portion includes: a plurality of patterns spaced apart from each other; and a connecting pattern connecting the plurality of patterns to each other, the connecting pattern and the plurality of patterns being arranged at different layers, and The first electrode of the second light emitting portion is connected to the connection pattern.

7. The display panel according to any one of claims 1 to 6, further comprising: a third pixel including a third light emitting portion disposed in the first region; as well as A third pixel driver is disposed in the peripheral area and connected to the third light emitting part.

8. An electronic device comprising: The display panel comprises a first area and a second area adjacent to the first area; as well as an electronic optical module overlapping the first region in a plan view, wherein The display panel comprises: a first pixel including a first light emitting portion disposed in the first region and a first pixel driver disposed in the second region; a second pixel including a second light emitting portion disposed in the second region and a second pixel driver disposed in the second region; a first connection line connecting the first light emitting part and the first pixel driver, the first connection line comprising a first emission connection part electrically connected to the first light emitting part; and a second connection line connecting the second light emitting part and the second pixel driver, the second connection line including a second emission connection part electrically connected to the second light emitting part, and In a cross-sectional view, each of the first emission connection portion and the second emission connection portion has an undercut shape.

9. The electronic device according to claim 8, wherein: The first emission connection portion is arranged along a boundary between the first region and the second region, and in the plan view, the first connection line and the second connection line do not overlap with the first region, or The first emission connection portion is disposed in the first region, and the first connection line overlaps the first region in the plan view.

10. The electronic device according to claim 8, wherein: The anode of the first light emitting portion and the anode of the second light emitting portion are integral with each other, The anode of the first light emitting portion comprises: a plurality of patterns spaced apart from each other; and a connecting pattern connecting the plurality of patterns to each other, the connecting pattern and the plurality of patterns being arranged at different layers, and The anode of the second light emitting portion is connected to the connection pattern.

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