Silicon carbide VDMOS capable of reducing body diode voltage drop

Abstract

The utility model provides a silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) capable of reducing the voltage drop of a body diode, which comprises a silicon carbide substrate and a drift layer, wherein the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate; a first well region and a second well region are arranged in the drift layer, and source regions are arranged in the first well region and the second well region; the lower side surface of the ohmic contact layer is connected to the upper side surface of the drift layer; the source electrode metal layer is respectively connected with the source region and the ohmic contact layer; the lower side surface of the insulating dielectric layer is respectively connected with the upper side surface of the first well region, the upper side surface of the second well region and the upper side surface of the source region, and a groove is formed in the insulating dielectric layer; a gate metal layer, wherein the gate metal layer is arranged in the groove; and the drain electrode metal layer is connected to the lower side surface of the silicon carbide substrate, so that the voltage drop from the source electrode to the drain electrode when the device is not conducted is reduced, the follow current loss is reduced, and the efficiency is improved.

Description

Technical Field

[0001] The utility model relates to a silicon carbide VDMOS capable of reducing the voltage drop of a body diode. Background Art

[0002] As a representative device among silicon carbide power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. Its advantages such as low on-resistance and low drive charge have attracted much attention. However, due to the large bandgap of SiC devices and the high pn junction barrier formed, a larger voltage is required to cross the pn junction barrier to achieve carrier transport during forward conduction. Therefore, the body diode conduction voltage drop is large, which leads to relatively large losses before turn-on. Therefore, reducing the body diode loss of silicon carbide VDMOS is of great significance to improving the efficiency of power electronic systems. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS with reduced body diode voltage drop, thereby reducing the voltage drop from the source to the drain when the device is not turned on, reducing the freewheeling loss and improving the efficiency.

[0004] The utility model is implemented as follows: a silicon carbide VDMOS with reduced body diode voltage drop, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a first well region and a second well region are provided in the drift layer, and a source region is provided in the first well region and the second well region;

[0007] An ohmic contact layer, wherein the lower side of the ohmic contact layer is connected to the upper side of the drift layer;

[0008] A source metal layer, the source metal layer is respectively connected to the source region and the ohmic contact layer;

[0009] an insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to the upper side of the first well region, the upper side of the second well region and the upper side of the source region, and a groove is provided on the insulating dielectric layer;

[0010] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0011] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0012] The advantages of the utility model are:

[0013] 1. The electrons at the drain of the device flow through the silicon carbide substrate and the drift layer. When passing through the space charge region formed by the first well region, the second well region and the drift layer, they are attracted by the positive voltage of the source region and the ohmic contact layer, realizing the electron transport from the drain to the source, and the current flows from the source to the drain. Since the depth of the space charge region is shallow, a smaller source voltage can realize the current flow, so the voltage drop from the source to the drain when the device is not turned on is reduced, the freewheeling loss is reduced, and the efficiency is improved.

[0014] Second, the body diode conduction channel of the device is turned off through the space charge region formed by the p-type well region and the n-type drift layer when the drain is subjected to high voltage. There is no additional turn-off structure, and the device structure is relatively simple;

[0015] 3. The device adopts a planar gate structure, which avoids the problem of slow etching speed during deep etching of the trench gate and improves the efficiency of device preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0017] Figure 1 The utility model is a schematic diagram of a silicon carbide VDMOS for reducing body diode voltage drop.

[0018] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide VDMOS for reducing a body diode voltage drop.

[0019] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 1 .

[0020] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 2 .

[0021] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 3 .

[0022] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 4 .

[0023] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 5 .

[0024] Figure 8This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 6 .

[0025] Fig. 9 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 7 .

[0026] Fig.10 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 8 .

[0027] Fig.11 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 9 .

[0028] Fig.12 This is a cross-sectional view of the process of a silicon carbide VDMOS with reduced body diode voltage drop in the utility model. Figure 10 . DETAILED DESCRIPTION

[0029] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0033] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide VDMOS with reduced body diode voltage drop, including:

[0035] Silicon carbide substrate 1,

[0036] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a first well region 21 and a second well region 22 are provided in the drift layer 2, and a source region 23 is provided in both the first well region 21 and the second well region 22;

[0037] An ohmic contact layer 3, wherein the lower side of the ohmic contact layer 3 is connected to the upper side of the drift layer 2;

[0038] A source metal layer 4, wherein the source metal layer 4 is respectively connected to the source region 23 and the ohmic contact layer 3;

[0039] An insulating dielectric layer 5, wherein the lower side of the insulating dielectric layer 5 is respectively connected to the upper side of the first well region 21, the upper side of the second well region 22 and the upper side of the source region 23, and a groove 51 is provided on the insulating dielectric layer 5;

[0040] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 51;

[0041] and, a drain metal layer 7, wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1;

[0042] The relationship between the width L1 of the ohmic contact layer 3 and the distance L2 between the first well region 21 and the second well region 22 is: 5L1≤L2≤8L1, the doping concentration of the first well region 21 and the second well region 22 is 10 times that of the n-type drift layer 2, and the depth of the space charge region formed to expand into the drift layer 2 is 10 times that of the first well region 21 and the second well region 22. Since the space charge region is expanded on both the left and right sides, the limit value is 10 times. Considering the process deviation, L2≤8L1 is set. In order to ensure that the ultra-low voltage (1.2V) of the body diode is turned on when the source is positively voltageed when the device is turned off, 5L1≤L2;

[0043] The device adopts a planar gate structure, which avoids the technical difficulties of deep etching of SiC materials at the current stage, and also avoids the problem of slow etching speed during deep etching of trench gates, thus improving the efficiency of device preparation;

[0044] The electrons at the drain of the device flow through the silicon carbide substrate 1 and the drift layer 2, and when passing through the space charge region formed by the first well region 21, the second well region 22 and the drift layer 2, they are attracted by the positive voltage of the source region 23 and the ohmic contact layer 3, so that the electrons are transported from the drain to the source, and the current flows from the source to the drain. Since the depth of the space charge region is shallow, a small source voltage can realize the flow of current, so the voltage drop from the source to the drain when the device is not turned on is reduced, the freewheeling loss is reduced, and the efficiency is improved;

[0045] The second source metal region 42 forms an ohmic contact with the ohmic contact layer 3, and there is no diode voltage drop. When the ohmic contact layer 3 of the device contacts the drift layer 2 and is not turned on and the drain is connected to a high voltage, the space charge region formed achieves reverse withstand voltage. When the source is positive and the device is not turned on, the positive source voltage injects electrons into the space charge region to achieve conduction. This part of the conduction voltage drop is achieved by controlling the doping concentration, L1 and L2.

[0046] like Figures 1 to 12 As shown, the method for preparing the above silicon carbide VDMOS comprises the following steps:

[0047] Step 1: depositing metal on one side of the silicon carbide substrate 1 to form a drain metal layer 7, and depositing and growing on the other side of the silicon carbide substrate 1 to form a drift layer 2;

[0048] Step 2: deposit a barrier layer a on the drift layer 2, etch the barrier layer a, and then perform ion implantation on the drift layer 2 to form a first well region 21 and a second well region 22. The ion implantation energy is 10-200kev, and the thickness is 600nm.

[0049] Step 3, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the first well region 21 and the second well region 22 to form a source region 23, the ion implantation energy is 10-100kev, and the thickness is 300nm;

[0050] Step 4, removing the barrier layer a, and then depositing to form an insulating dielectric layer 5, wherein the insulating dielectric layer 5 is made of silicon dioxide;

[0051] Step 5, depositing to form a barrier layer a, etching to form a through hole, and performing metal deposition through the through hole to form a first source metal region 41;

[0052] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, depositing the through hole to form an ohmic contact layer 3, wherein the material of the ohmic contact layer 3 is silicon carbide;

[0053] Step 7: depositing metal on the ohmic contact layer 3 to form a second source metal region 42, wherein the source metal layer 4 includes a first source metal region 41 and a second source metal region 42;

[0054] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a and the gate dielectric layer 5 to form a through hole and a groove 51, deposit metal on the groove 51 through the through hole to form a gate metal layer 6, remove the barrier layer a, and complete the manufacturing.

[0055] The silicon carbide substrate 1 , the drift layer 2 and the source region 23 are all N-type; the first well region 21 and the second well region 22 are both P-type.

[0056] The doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 3e16cm -3 The doping concentration of the ohmic contact layer 3 is 2e18cm -3 The doping concentration of the source region 23 is 2e18cm -3 The doping concentrations of the first well region 21 and the second well region 22 are both 3e17cm -3 ; The doping concentration of the silicon carbide substrate 1 can effectively reduce the drain contact resistance, the doping concentration of the drift layer 2 is a compromise between the withstand voltage and the on-resistance, the doping concentration of the source region 23 is to reduce the on-resistance, the doping concentration of the ohmic contact layer 3 is to reduce the on-resistance of the device and the compromise between the doping and width of the first well region 21 and the second well region 22 to form a space charge region, and the doping concentration of the first well region 21 and the second well region 22 is to achieve good gate control capability.

[0057] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide VDMOS with reduced body diode voltage drop, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A first well region and a second well region are provided in the drift layer, and a source region is provided in both the first well region and the second well region; An ohmic contact layer, wherein the lower side of the ohmic contact layer is connected to the upper side of the drift layer; A source metal layer, the source metal layer is respectively connected to the source region and the ohmic contact layer; an insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to the upper side of the first well region, the upper side of the second well region and the upper side of the source region, and a groove is provided on the insulating dielectric layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. A silicon carbide VDMOS with reduced body diode voltage drop according to claim 1, characterized in that: The relationship between the width L1 of the ohmic contact layer and the distance L2 between the first well region and the second well region is: 5L1≤L2≤8L1.

3. The silicon carbide VDMOS with reduced body diode voltage drop according to claim 1, characterized in that: The silicon carbide substrate, drift layer and source region are all N-type; the first well region and the second well region are both P-type.

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