Dormancy wake-up circuit
By designing a sleep wake-up circuit including a power supply module, a switch module and a clamp module, the problem of high power consumption of the sleep wake-up circuit in the prior art is solved, and a sleep state with low power consumption in the vehicle-machine communication system is realized.
Patent Information
- Application Number
- CN202421309565.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-02-21
- Estimated Expiration
- 2034-06-07
AI Technical Summary
The existing sleep wake-up circuit is not suitable for vehicle-machine communication systems with only LIN communication interfaces. In the sleep state, the motor control module of the vehicle-machine communication system cannot be powered off and the power consumption is still high.
A sleep wake-up circuit including a power supply module, a first switching module, a clamp module, a sleep control module, a second switching module and a control module are designed. By controlling the state of the switch module and the clamp module, the current path is disconnected and re-established to ensure that the circuit maintains a sleep state when the voltage of the power module drops below the operating voltage in the sleep state.
It effectively reduces power consumption in the sleep state, ensures that the vehicle-machine communication system operates in the low-power mode, and avoids the problem of excessive battery consumption.
Smart Images
Figure CN222512196U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic circuits, in particular to a sleep awakening circuit. Background Art
[0002] The on-board power supply can supply power to on-board electronic devices and is an indispensable part of the car. After the vehicle is turned off, some functions of some on-board electronic devices need to be in working state, which will consume the battery power on the vehicle. In order to avoid excessive and rapid consumption of battery power, resulting in battery power failure, the on-board electronic devices need to work in low power consumption mode after the vehicle is turned off to reduce power consumption.
[0003] The low power mode has a sleep wake-up mechanism, and the sleep wake-up function can be realized by a sleep wake-up circuit. However, the existing sleep wake-up circuit is not suitable for the vehicle communication system with only a LIN communication interface, and in the sleep state, the motor control module of the vehicle communication system cannot be powered off, and the power consumption is still high. Utility Model Content
[0004] The utility model aims to provide a sleep-wake-up circuit to solve the problem of high power consumption of the existing sleep-wake-up circuit.
[0005] In order to achieve the above-mentioned object, the utility model provides a sleep wake-up circuit, including a power module, a first switch module, a clamp module, a sleep control module, a second switch module and a control module;
[0006] The power module is connected to the first switch module, so that a current path is formed from the power module, the first switch module, the clamp module, the second switch module to the ground terminal;
[0007] The connection node between the first switch module and the clamp module is a first node, and the connection node between the clamp module and the second switch module is a second node;
[0008] The control module is connected to the first node, the control module is powered by the first node, and the sleep control module is connected between the second node and the ground terminal;
[0009] When the sleep control module receives the sleep signal output by the control module, the first switch module and the second switch module are turned off, and the first node starts to power off. When the voltage on the first node drops below the operating voltage of the control module, the clamping module maintains the second switch module turned off, so that the first node continues to power off to keep the control module in sleep mode.
[0010] Optionally, the connection node between the first switch module and the second switch module is a third node. When the third node receives a wake-up signal, the first switch module is turned on, the first node starts to power on, and the control module wakes up; when the voltage on the first node rises to above the operating voltage of the clamp module, the clamp module is turned on and the second switch module is turned on, so that the first switch module remains turned on and the control module remains awake.
[0011] Optionally, the wake-up signal is a low-level pulse signal.
[0012] Optionally, the connection node between the first switch module and the second switch module is a third node, and the third node is connected to the ground terminal via the second switch module; and,
[0013] When the second node receives a wake-up signal, the second switch module is turned on, the first switch module is turned on, the first node starts to power on, and the control module wakes up; when the voltage on the first node rises to above the operating voltage of the clamp module, the clamp module is turned on, and the second switch module remains turned on, so that the first switch module remains turned on and the control module remains awake.
[0014] Optionally, the wake-up signal is a high-level pulse signal.
[0015] Optionally, the operating voltage of the clamping module is smaller than the difference between the output voltage of the power module and the turn-on voltage of the second switch module, and is larger than the difference between the operating voltage of the control module and the turn-on voltage of the second switch module.
[0016] Optionally, the first switch module includes a first switch tube and a first resistor, and the second switch module includes a second switch tube and a fifth resistor;
[0017] The first end and the second end of the first switch tube are respectively connected to the output end of the power module and the first node, the control end of the first switch tube is connected to the third node, the control end of the first switch tube is also connected to one end of the first resistor, and the other end of the first resistor is connected to the output end of the power module, the first end of the second switch tube is connected to the third node, the second end of the second switch tube is connected to the ground end, the control end of the second switch tube is connected to the second node, the control end of the second switch tube is also connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the ground end.
[0018] Optionally, the sleep control module includes a third switch tube, a second resistor and a third resistor, the control end of the third switch tube is connected to one end of the second resistor and one end of the third resistor, the first end of the third switch tube is connected to the second node, the second end of the third switch tube is connected to the ground end, the other end of the second resistor is connected to the control module for receiving the sleep signal, and the other end of the third resistor is connected to the ground end.
[0019] Optionally, the sleep signal is a high level signal.
[0020] Optionally, the second switch tube and the third switch tube are NMOS tubes or NPN transistors, and the first switch tube is a PMOS tube or a PNP transistor.
[0021] Optionally, the clamping module includes a first voltage regulator tube and a fourth resistor, the cathode of the first voltage regulator tube is connected to the first node, the anode of the first voltage regulator tube is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the second node.
[0022] Optionally, a voltage stabilizing module is further included, and one end of the voltage stabilizing module is connected between the second node and the ground end.
[0023] Optionally, the voltage stabilizing module includes a second voltage stabilizing diode, and the second voltage stabilizing diode is connected in parallel with the fifth resistor.
[0024] Optionally, a first current limiting module is further included, one end of the first current limiting module is connected to the third node, and the other end of the first current limiting module is connected to the control end of the first switch tube and one end of the first resistor.
[0025] Optionally, a second current limiting module is further included, one end of the second current limiting module is used to receive the wake-up signal, and the other end of the second current limiting module is connected to the third node.
[0026] Optionally, the wake-up signal is a bus signal.
[0027] Optionally, the sleep wake-up circuit is applied to a vehicle-machine communication system, and the wake-up signal is a LIN bus signal in the vehicle-machine communication system.
[0028] In the sleep wake-up circuit provided by the utility model, the power supply module is connected to the first switch module, and a current path is formed from the power supply module, the first switch module, the clamp module, the second switch module to the ground terminal. The connection node between the first switch module and the clamp module is the first node, and the connection node between the clamp module and the second switch module is the second node; the control module is connected to the first node, and the control module is powered by the first node, and the sleep control module is connected between the second node and the ground terminal; when the sleep control module receives the sleep signal output by the control module, the first switch module and the second switch module are turned off, and the first node starts to power off. When the voltage on the first node drops below the operating voltage of the control module, the clamp module maintains the second switch module turned off, so that the first node continues to power off to keep the control module in sleep. Since the power supply voltage of the control module is supplied by the voltage on the first node, when the voltage on the first node drops, the control module cannot continue to output the sleep signal. At this time, the clamping module can keep the second switch module turned off to ensure that the first node continues to lose power and keep the control module in sleep. After entering the sleep state, the sleep wake-up circuit and the control module can be powered off, which reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is a structural block diagram of a sleep wake-up circuit provided in Embodiment 1 of the present utility model;
[0030] Figure 2 A circuit diagram of a sleep wake-up circuit provided in Embodiment 1 of the present utility model;
[0031] Figure 3 A timing diagram of various signals in the sleep and wake-up circuit provided in the first embodiment of the utility model;
[0032] Figure 4 A structural block diagram of a sleep wake-up circuit provided in Embodiment 2 of the present utility model;
[0033] Figure 5 A circuit diagram of a sleep wake-up circuit provided in Embodiment 2 of the present utility model;
[0034] Wherein, the accompanying drawings are marked as follows:
[0035] 10-power module; 20-first switch module; 30-second switch module; 40-clamp module; 50-sleep control module; 61-first current limiting module; 62-second current limiting module; 70-voltage stabilizing module; 80-control module;
[0036] Vin-power supply voltage; K1-first node; K2-second node; K3-third node; Vout-voltage on the first node; Wake_up-wake-up signal; Sleep_Ctrl-sleep signal; Q1-first switch tube; Q2-second switch tube; Q3-third switch tube; R1-first resistor; R2-second resistor; R3-third resistor; R4-fourth resistor; R5-fifth resistor; R6-sixth resistor; R7-seventh resistor; Z1-first voltage regulator tube; Z2-second voltage regulator tube. DETAILED DESCRIPTION
[0037] The following will describe the specific implementation of the utility model in more detail with reference to the schematic diagram. The advantages and features of the utility model will become clearer according to the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0038] Embodiment 1
[0039] Figure 1 This is a structural block diagram of the sleep wake-up circuit provided in this embodiment. Figure 1 As shown, the sleep wake-up circuit includes a power module 10 , a first switch module 20 , a clamp module 40 , a sleep control module 50 , a second switch module 30 and a control module 80 .
[0040] Specifically, the output end of the power module 10 outputs a power supply voltage Vin, and the power supply voltage Vin may be a voltage output after filtering and anti-reverse connection protection. The output end of the power module 10 is connected to the first switch module 20, and a current path is formed from the power module 10, the first switch module 20, the clamp module 40, the second switch module 30 to the ground end. The connection node between the first switch module 20 and the clamp module 40 is a first node K1, the first node K1 is connected to the power supply end of the control module 80, and the voltage Vout on the first node K1 is used to power the control module 80. The output end of the control module 80 is connected to the sleep control module 50 to provide the sleep signal Sleep_Ctrl to the sleep control module 50; the connection node between the clamp module 40 and the second switch module 30 is a second node K2, and the sleep control module 50 is connected between the second node K2 and the ground end.
[0041] Of course, the first node K1 may also be connected to other circuit structures or peripherals to supply power to these circuit structures or peripherals.
[0042] Further, when the sleep control module 50 receives the sleep signal Sleep_Ctrl output by the control module 80, the second switch module 30 is turned off, the first switch module 20 is interlocked with the second switch module 30, the first switch module 20 is also turned off, the path between the power module 10 and the control module 80 is disconnected, the first node K1 starts to lose power, and the voltage Vout on the first node K1 decreases rapidly. When the voltage Vout on the first node K1 drops below the operating voltage of the control module 80, the clamp module 40 will keep the second switch module 30 turned off. Since the first switch module 20 is interlocked with the second switch module 30, the first switch module 20 is also kept turned off, and the first node K1 can continue to lose power, thereby keeping the control module 80 in sleep.
[0043] In this embodiment, the operating voltage of the clamp module 40 is smaller than the difference between the power voltage Vin output by the power module 10 and the turn-on voltage of the second switch module 30 , and is larger than the difference between the operating voltage of the control module 80 and the turn-on voltage of the second switch module 30 . Since the power supply voltage of the control module 80 is supplied by the voltage Vout on the first node K1, when the voltage Vout on the first node K1 drops, the control module 80 cannot continue to maintain the output of the sleep signal Sleep_Ctrl. At this time, since the voltage Vout on the first node K1 drops to below the working voltage of the control module 80 and above the working voltage of the clamp module 40, the clamp module 40 is turned on. Although the voltage Vout on the first node K1 is higher than the turn-on voltage of the second switch module 30, after the voltage is divided by the clamp module 40, the voltage on the second node K2 is lower than the turn-on voltage of the second switch module 30, and the second switch module 30 will maintain the off state; when the voltage Vout on the first node K1 continues to drop and drops below the working voltage of the clamp module 40, the clamp module 40 is turned off, and the second switch module 30 maintains the off state. Therefore, the clamping module 40 can keep the second switch module 30 turned off (thereby keeping the first switch module 20 turned off), ensure that the first node K1 continues to be powered off, and keep the control module 80 in sleep mode. After entering the sleep state, the sleep wake-up circuit and the control module 80 can be powered off, with lower power consumption.
[0044] Further, when the third node K3 between the first switch module 20 and the second switch module 30 receives a wake-up signal Wake_up, the first switch module 20 is turned on, the first node K1 starts to power on, the control module 80 is awakened, and the voltage Vout on the first node K1 gradually increases. When the voltage Vout on the first node K1 increases to above the operating voltage of the clamp module 40, the clamp module 40 is turned on, and the second switch module 30 is also turned on, so that the first switch module 20 remains turned on and the control module 80 remains awake.
[0045] After the pulse of the wake-up signal Wake_up has passed, the clamping module 40 can keep the first switch module 20 turned on to ensure that the first node K1 continues to be powered on, and the control module 80 remains awake.
[0046] Figure 2 The circuit diagram of the sleep wake-up circuit provided in this embodiment. Figure 1 and Figure 2 As shown, the first switch module 20 includes a first switch tube Q1 and a first resistor R1, and the second switch module 30 includes a second switch tube Q2 and a fifth resistor R5. The first end of the first switch tube Q1 is connected to the output end of the power module 10, the second end of the first switch tube Q1 is connected to the first node K1, the control end of the first switch tube Q1 is connected to the third node K3, the control end of the first switch tube Q1 is also connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the output end of the power module 10. The first end of the second switch tube Q2 is connected to the third node K3, the second end of the second switch tube Q2 is connected to the ground end, the control end of the second switch tube Q2 is connected to the second node K2, the control end of the second switch tube Q2 is also connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the ground end.
[0047] Furthermore, the sleep control module 50 includes a third switch tube Q3, a second resistor R2 and a third resistor R3, the control end of the third switch tube Q3 is connected to one end of the second resistor R2 and one end of the third resistor R3, the first end of the third switch tube Q3 is connected to the second node K2, the second end of the third switch tube Q3 is grounded, the other end of the second resistor R2 is connected to the control module 80 for receiving the sleep signal Sleep_Ctrl, and the other end of the third resistor R3 is grounded.
[0048] Please continue reading Figure 2The clamping circuit includes a first voltage regulator tube Z1 and a fourth resistor R4 connected in series. Specifically, the cathode of the first voltage regulator tube Z1 is connected to the first node K1, the anode of the first voltage regulator tube Z1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the second node K2.
[0049] In this embodiment, the operating voltage of the clamping module 40 needs to be lower than the output voltage of the power module 10 (the power supply voltage of the control module 80). Specifically, the rated voltage of the first voltage regulator Z1 needs to be lower than the difference between the power supply voltage Vin and the turn-on voltage of the second switch tube Q2, and higher than the difference between the operating voltage of the control module 80 and the turn-on voltage of the second switch tube Q2. For example, the power supply voltage Vin can be 12V, the operating voltage of the control module 80 can be 5V, and the turn-on voltage of the second switch tube Q2 can be 3V. At this time, the rated voltage of the first voltage regulator Z1 needs to be lower than 9V and higher than 2V.
[0050] Figure 3 This is a timing diagram of each signal in the sleep wake-up circuit provided in this embodiment. Figure 3 As shown, in this embodiment, the sleep signal is a high-level signal, and the wake-up signal is a low-level pulse signal. Based on this, the second switch tube Q2 and the third switch tube Q3 are NMOS tubes or NPN-type transistors, and the first switch tube Q1 is a PMOS tube or a PNP-type transistor, wherein the first end of the NMOS tube and the PMOS tube is its drain, the second end is its source, and the control end is its gate, and the first end of the NPN-type transistor and the PNP-type transistor is its collector, the second end is its emitter, and the control end is its base.
[0051] Please continue reading Figure 2 and Figure 3 After the power module 10 is powered on, it continuously outputs the power voltage Vin, and the power voltage Vin is always in a high level state. During normal communication, the first switch tube Q1 and the second switch tube Q2 are turned on, and the first voltage regulator tube Z1 is turned on after being reversely broken down. At this time, the voltage Vout on the first node K1 is at a high level, and the control module 80 is powered.
[0052] When the control module 80 needs to sleep, it outputs the sleep signal Sleep_Ctrl of high level, and the control end of the third switch tube Q3 is turned on after receiving the sleep signal Sleep_Ctrl of high level; the voltage on the second node K2 is pulled to the ground, and since the second node K2 is connected to the control end of the second switch tube Q2, the second switch tube Q2 is turned off; the voltage on the control end of the first switch tube Q1 is pulled up through the first resistor R1, and the first switch tube Q1 is turned off. At this time, the path between the power module 10 and the control module 80 is disconnected, the first node K1 starts to lose power, and the voltage Vout on the first node K1 drops rapidly. After the voltage Vout on the first node K1 drops to the working voltage of the first voltage regulator tube Z1, the first voltage regulator tube Z1 will not be turned on, and the path between the first node K1 and the control end of the second switch tube Q2 is disconnected. It can be seen that even if the control module 80 cannot maintain the output of the high-level sleep signal Sleep_Ctrl, the first voltage regulator Z1 can also maintain the second switch tube Q2 turned off, and the first switch tube Q1 will also be turned off due to interlocking with the second switch tube Q2. The voltage Vout on the first node K1 (not yet dropped to 0V) will not turn on the second switch tube Q2 again. The first node K1 can continue to power off to maintain the control module 80 in sleep mode. After sleep mode, the control module 80 can be powered off to reduce power consumption, thereby achieving low power consumption of the entire machine in sleep mode, and the overall power consumption in sleep mode is less than 20uA.
[0053] Further, when the third node K3 receives the wake-up signal Wake_up (for example, a low-level pulse of 250us to 5ms), the first switch tube Q1 is turned on, the path between the power module 10 and the control module 80 is turned on, and the voltage Vout on the first node K1 begins to rise (until it reaches the power supply voltage Vin). When the voltage Vout on the first node K1 rises to a voltage greater than the working voltage of the first voltage regulator tube Z1, the first voltage regulator tube Z1 is reversely broken down and turned on, and the control end of the second switch tube Q2 receives a high level and turns on. It can be seen that after the low-level pulse of the wake-up signal Wake_up has passed, the first voltage regulator tube Z1 can keep the second switch tube Q2 turned on, and the first switch tube Q1 will also remain turned on due to interlocking with the second switch tube Q2, the first node K1 can continue to be powered on, and the control module 80 remains awake.
[0054] It should be noted that the wake-up signal Wake_up in this embodiment is directly input to the control end of the first switch tube Q1, so the signal delay is small and the wake-up is faster.
[0055] Please continue reading Figure 2 In this embodiment, the sleep wake-up circuit further includes a voltage stabilizing module 70, one end of which is connected between the second node K2 and the gate of the second switch tube Q2, and the other end of which is grounded. Specifically, the voltage stabilizing module 70 includes a second voltage stabilizing tube Z2, which is connected in parallel with the fifth resistor R5.
[0056] It should be understood that in some embodiments, the voltage stabilizing module 70 may be omitted; and the voltage stabilizing module 70 may also be composed of other circuit components, which will not be illustrated one by one here.
[0057] Furthermore, the sleep wake-up circuit also includes a first current limiting module 61 and a second current limiting module 62, one end of the second current limiting module 62 is used to receive the wake-up signal, the other end of the second current limiting module 62 is connected to the third node K3, one end of the first current limiting module 61 is connected to the third node K3, and the other end of the first current limiting module 61 is connected to the gate of the first switch tube Q1 and one end of the first resistor R1.
[0058] In this embodiment, the first current limiting module 61 includes a sixth resistor R6, and the second current limiting module 62 includes a seventh resistor R7, but the present invention is not limited thereto.
[0059] In this embodiment, the wake-up signal is a bus signal. For example, the sleep wake-up circuit can be applied to a vehicle communication system, and the wake-up signal is a LIN bus signal in the vehicle communication system. It should be understood that the sleep wake-up circuit is not limited to the vehicle communication system, and can also be applied to other communication methods (such as GPIO communication, etc.) or other communication systems.
[0060] Embodiment 2
[0061] Figure 4 The structure block diagram of the sleep wake-up circuit provided in this embodiment is as follows: Figure 5 The circuit diagram of the sleep wake-up circuit provided in this embodiment. Figure 4 and Figure 5 As shown, the difference from the first embodiment is that in this embodiment, the second current limiting module 62 is omitted, the wake-up signal Wake_up can be input into the second node K2, and the third node K3 is connected to the ground terminal via the second switch module.
[0062] When the second node K2 receives the wake-up signal Wake_up, the second switch module 30 is turned on, the first switch module 20 is also turned on, the first node K1 starts to power on, the control module 80 is awakened, and the voltage Vout on the first node K1 gradually increases. When the voltage Vout on the first node K1 increases to above the operating voltage of the clamp module 40, the clamp module 40 is turned on, and the second switch module 30 remains turned on, so that the first switch module 20 remains turned on, and the control module 80 remains awakened.
[0063] In this embodiment, the wake-up signal Wake_up is a high-level pulse signal.
[0064] In summary, in the sleep wake-up circuit provided in the embodiment of the utility model, the power supply module is connected to the first switch module, and a current path is formed from the power supply module, the first switch module, the clamp module, the second switch module to the ground terminal. The connection node between the first switch module and the clamp module is the first node, and the connection node between the clamp module and the second switch module is the second node; the control module is connected to the first node, and the control module is powered by the first node, and the sleep control module is connected between the second node and the ground terminal; when the sleep control module receives the sleep signal output by the control module, the first switch module and the second switch module are turned off, and the first node starts to power off. When the voltage on the first node drops below the operating voltage of the control module, the clamp module maintains the second switch module turned off, so that the first node continues to power off to keep the control module in sleep. Since the power supply voltage of the control module is supplied by the voltage on the first node, when the voltage on the first node drops, the control module cannot continue to output the sleep signal. At this time, the clamping module can keep the second switch module turned off to ensure that the first node continues to lose power and keep the control module in sleep. After entering the sleep state, the sleep wake-up circuit and the control module can be powered off, which reduces power consumption.
[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0066] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
[0067] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0068] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the utility model. It must be noted that the singular forms "one" and "a kind" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have a logical "or" definition, rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiment of the utility model may include performing the selected task manually, automatically, or in combination.
Claims
1. A sleep wake-up circuit, characterized in that: It includes a power module, a first switch module, a clamp module, a sleep control module, a second switch module and a control module; The power module is connected to the first switch module, so that a current path is formed from the power module, the first switch module, the clamp module, the second switch module to the ground terminal; The connection node between the first switch module and the clamp module is a first node, and the connection node between the clamp module and the second switch module is a second node; The control module is connected to the first node, the control module is powered by the first node, and the sleep control module is connected between the second node and the ground terminal; When the sleep control module receives the sleep signal output by the control module, the first switch module and the second switch module are turned off, and the first node starts to power off. When the voltage on the first node drops below the operating voltage of the control module, the clamping module maintains the second switch module turned off, so that the first node continues to power off to keep the control module in sleep mode.
2. The sleep wake-up circuit according to claim 1, characterized in that: The connection node between the first switch module and the second switch module is a third node. When the third node receives a wake-up signal, the first switch module is turned on, the first node starts to power on, and the control module wakes up; when the voltage on the first node rises to above the operating voltage of the clamp module, the clamp module is turned on and the second switch module is turned on, so that the first switch module remains turned on and the control module remains awake.
3. The sleep wake-up circuit according to claim 2, characterized in that: The wake-up signal is a low-level pulse signal.
4. The sleep wake-up circuit according to claim 1, characterized in that: The connection node between the first switch module and the second switch module is a third node, and the third node is connected to the ground terminal via the second switch module; and When the second node receives a wake-up signal, the second switch module is turned on, the first switch module is turned on, the first node starts to power on, and the control module wakes up; when the voltage on the first node rises to above the operating voltage of the clamp module, the clamp module is turned on, and the second switch module remains turned on, so that the first switch module remains turned on and the control module remains awake.
5. The sleep wake-up circuit according to claim 4, characterized in that: The wake-up signal is a high-level pulse signal.
6. The sleep wake-up circuit according to claim 1, characterized in that: The operating voltage of the clamping module is smaller than the difference between the output voltage of the power module and the turn-on voltage of the second switch module, and is larger than the difference between the operating voltage of the control module and the turn-on voltage of the second switch module.
7. The sleep / wake-up circuit according to any one of claims 2 to 5, characterized in that: The first switch module includes a first switch tube and a first resistor, the second switch module includes a second switch tube and a fifth resistor; and, The first end and the second end of the first switch tube are respectively connected to the output end of the power module and the first node, the control end of the first switch tube is connected to the third node, the control end of the first switch tube is also connected to one end of the first resistor, and the other end of the first resistor is connected to the output end of the power module, the first end of the second switch tube is connected to the third node, the second end of the second switch tube is connected to the ground end, the control end of the second switch tube is connected to the second node, the control end of the second switch tube is also connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the ground end.
8. The sleep wake-up circuit according to claim 7, characterized in that: The sleep control module includes a third switch tube, a second resistor and a third resistor, the control end of the third switch tube is connected to one end of the second resistor and one end of the third resistor, the first end of the third switch tube is connected to the second node, the second end of the third switch tube is connected to the ground end, the other end of the second resistor is connected to the control module for receiving the sleep signal, and the other end of the third resistor is connected to the ground end.
9. The sleep wake-up circuit according to claim 1 or 8, characterized in that: The sleep signal is a high level signal.
10. The sleep wake-up circuit according to claim 8, characterized in that: The second switch tube and the third switch tube are NMOS tubes or NPN transistors, and the first switch tube is a PMOS tube or a PNP transistor.
11. The sleep wake-up circuit according to claim 1, characterized in that: The clamping module includes a first voltage regulator tube and a fourth resistor, wherein the cathode of the first voltage regulator tube is connected to the first node, the anode of the first voltage regulator tube is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the second node.
12. The sleep wake-up circuit according to claim 7, characterized in that: It also includes a voltage stabilizing module, one end of which is connected between the second node and the ground terminal.
13. The sleep wake-up circuit according to claim 12, characterized in that: The voltage stabilizing module includes a second voltage stabilizing tube, and the second voltage stabilizing tube is connected in parallel with the fifth resistor.
14. The sleep wake-up circuit according to claim 7, characterized in that: It also includes a first current limiting module, one end of which is connected to the third node, and the other end of which is connected to the control end of the first switch tube and one end of the first resistor.
15. The sleep wake-up circuit according to claim 2 or 3, characterized in that: It also includes a second current limiting module, one end of which is used to receive the wake-up signal, and the other end of which is connected to the third node.
16. The sleep / wake-up circuit according to any one of claims 2 to 5, characterized in that: The wake-up signal is a bus signal.
17. The sleep / wake-up circuit according to any one of claims 2 to 5, characterized in that: The sleep wake-up circuit is applied to a vehicle-machine communication system, and the wake-up signal is a LIN bus signal in the vehicle-machine communication system.