Test structure layout
By setting the plug-in finger structure in the test structure layout, connecting the gate and source in parallel to the first test part, and connecting the drain in parallel to the second test part, the layout size is too large and the voltage distribution is not solved The problem of uniformity achieves the simultaneous turn-on of the MOS transistor and the reduction of parasitic resistance.
Patent Information
- Application Number
- CN202420985141.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2025-02-21
- Estimated Expiration
- 2034-05-08
AI Technical Summary
In TLP test, due to the need to design multiple plug-in structures, the layout size is too large, and the asymmetric design leads to uneven voltage distribution. The MOS transistors with multiple plug-in fingers cannot be turned on, which misleads the ESD capability judgment, and affects the test with parasitic resistance. result.
Design a test structure layout, wherein the device part includes a plurality of plug-in finger structures arranged symmetrically along the mid-perpendicular line, the gate and source are connected in parallel to the first test part, the drain is connected in parallel to the second test part, and the first test part Grounding, the second test part connects the working voltage to reduce parasitic resistance and improve the utilization rate of the layout area.
The multi-plug finger MOS transistor is enabled at the same time, which reduces the parasitic resistance of the test structure, improves the utilization rate of the layout area, and avoids misleading judgments of ESD capabilities.
Smart Images
Figure CN222514912U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor manufacturing, in particular to a test structure layout. Background Art
[0002] TLP (Transmission Line Pulse) testing is the primary means of evaluating the performance of independent ESD (Electro-Static discharge) devices on the wafer during the R&D phase.
[0003] Since the TLP test requires a current of 2 amperes or even higher, many finger structures need to be designed on the layout. At this time, the total width of all finger structures reaches 500μm to 1000μm. This special requirement makes the layout size of each test structure very large, which makes the layout design of the test structure face the following challenges:
[0004] 1. During the design, if an asymmetric layout is used, the voltage distribution will be uneven, causing the multi-finger MOS transistors to be unable to be fully turned on (i.e., turned on). As a result, the damage current of the MOS transistor obtained during the TLP test is only contributed by the turned-on MOS transistor, which leads to misleading judgment of the ESD capability of the test structure and hinders development;
[0005] 2. When designing the internal routing of the layout, since it is necessary to directly lead out from the first metal layer through the metal through-hole, the parasitic resistance is the sum of the first metal layer resistance and the metal through-hole resistance. The parasitic resistance plays a dominant role in affecting the test results of the damage current of the test structure, resulting in misleading judgment of the ESD capability of the test structure.
[0006] 3. Due to layout area considerations, more test structures need to be placed in a limited area. Utility Model Content
[0007] One of the purposes of the utility model is to provide a test structure layout, which can enable MOS transistors with multiple fingers to be turned on at the same time.
[0008] Another purpose of the utility model is to reduce the parasitic resistance of the test structure and improve the utilization rate of the layout area.
[0009] In order to solve the above problems, the utility model provides a test structure layout, including a device part, a first test part and a second test part, wherein the first test part and the second test part are arranged on both sides of the device part, and are symmetrically arranged along the midline of the device part in the first direction, the device part includes a plurality of interdigitated finger structures arranged at intervals along the second direction, and all the interdigitated finger structures are symmetrically arranged along the midline of the device part in the second direction, the gates and sources of all the interdigitated finger structures are connected in parallel to the first test part, and the drains of all the interdigitated finger structures are connected in parallel to the second test part, wherein the first direction and the second direction are perpendicular to each other, the first direction is parallel to the midline of the device part in the second direction, and the second direction is parallel to the midline of the device part in the first direction;
[0010] During testing, the first testing part is grounded, and the second testing part is connected to a working voltage.
[0011] Optionally, the device is partially disposed in an active area surrounded by a shallow trench isolation structure, the active area is rectangular, and the active area is provided with a first side and a second side, the first side is disposed along the first direction, and the second side is disposed along the second direction.
[0012] Furthermore, all the finger structures are symmetrically arranged along the perpendicular midline of the second side, and the first test part and the second test part are symmetrically arranged along the perpendicular midline of the first side.
[0013] Furthermore, the device part includes a connected device main body part and a device interconnection layer, the device main body part includes a source region, a drain region and a body region located in a substrate, and a gate structure located on the substrate; the device interconnection layer includes a first metal layer to an nth metal layer arranged in sequence from bottom to top, wherein n≥3 and is a positive integer.
[0014] Furthermore, the first metal layer to the nth metal layer each include a first sub-metal layer and a second sub-metal layer that are spaced apart, the first sub-metal layer of the first metal layer simultaneously connects the body region, the source region and the gate structure, the second sub-metal layer of the first metal layer connects the drain region, and the first sub-metal layer of the first metal layer to the first sub-metal layer of the nth metal layer are connected in sequence, the second sub-metal layer of the first metal layer to the second sub-metal layer of the nth metal layer are connected in sequence, all of the first sub-metal layers are connected to the first test portion, and all of the second sub-metal layers are connected to the second test portion.
[0015] Further, the first test part and the second test part both include a first test layer to an nth test layer arranged sequentially from bottom to top, the first test layer to the nth test layer of the first test part are connected sequentially, and the first test layer to the nth test layer of the second test part are connected sequentially;
[0016] The first test layer of the first test part, the first test layer of the second test part, and the first metal layer of the device interconnection layer are arranged in the same layer with intervals; the second test layer of the first test part, the second test layer of the second test part, and the second metal layer are arranged in the same layer, and the second test layer of the first test part is connected in parallel with the first sub-metal layer of the second metal layer, and the second test layer of the second test part is connected in parallel with the second sub-metal layer of the second metal layer; the nth test layer of the first test part, the nth test layer of the second test part, and the nth metal layer are arranged in the same layer, and the nth test layer of the first test part is connected in parallel with the first sub-metal layer of the n metal layer, and the nth test layer of the second test part is connected in parallel with the second sub-metal layer of the n metal layer.
[0017] Further, the nth test layer of the first test part includes a first connecting portion, a first TLP test pad and a first WAT test pad, and the nth test layer of the second test part includes a second connecting portion, a second TLP test pad and a second WAT test pad, the first connecting portion connects the first sub-metal layer of the nth metal layer, the first TLP test pad and the first WAT test pad are spaced apart and both are connected to the first connecting portion; the second connecting portion connects the second sub-metal layer of the nth metal layer, the second TLP test pad and the second WAT test pad are spaced apart and both are connected to the second connecting portion.
[0018] Furthermore, the first TLP test pad and the second TLP test pad are symmetrically arranged along the perpendicular midline of the first side, and are also symmetrically arranged along the perpendicular midline of the second side.
[0019] Furthermore, the first connecting portion and the second connecting portion are both in the shape of long strips, the first TLP test pad and the second TLP test pad are symmetrically arranged on the outside of the first connecting portion and the second connecting portion, the first WAT test pad is arranged at one end of the first connecting portion, the second WAT test pad is arranged at one end of the second connecting portion, and the first WAT test pad and the second WAT test pad are arranged on the same side.
[0020] Compared with the prior art, the utility model has the following beneficial effects:
[0021] The utility model provides a test structure layout, comprising a device part, a first test part and a second test part, wherein the first test part and the second test part are arranged on both sides of the device part and are symmetrically arranged along the perpendicular midline of the device part in the first direction, the device part comprises a plurality of interdigitated finger structures arranged at intervals along the second direction, and all the interdigitated finger structures are symmetrically arranged along the perpendicular midline of the device part in the second direction, the gates and sources of all the interdigitated finger structures are connected in parallel to the first test part, and the drains of all the interdigitated finger structures are connected in parallel to the second test part, wherein the first direction and the second direction are perpendicular to each other, the first direction is parallel to the perpendicular midline of the device part in the second direction, and the second direction is parallel to the perpendicular midline of the device part in the first direction; during testing, the first test part is grounded, and the second test part is connected to an operating voltage. In the utility model, the first test part and the second test part are symmetrically arranged on the perpendicular midline of the device part along the first direction, and all the finger structures are symmetrically arranged on the perpendicular midline of the device part along the second direction, so that the device part is a symmetrical structure, and the first test part and the second test part are symmetrical structures. Therefore, when the test structure layout is tested, the current can flow from the second test part through each finger structure to the first test structure evenly, so that the voltages at both ends of each finger structure are consistent, so that all MOS transistors (i.e., finger structures) can be turned on at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1-Figure 2 A schematic top view of a test structure layout provided in one embodiment of the utility model.
[0023] Figure 3 A schematic cross-sectional structure diagram of a test structure layout provided in one embodiment of the utility model.
[0024] Description of reference numerals:
[0025] 10-device part; 20-first test part; 21-first test layer of the first test part; 22-second test layer of the first test part; 2n-nth test layer of the first test part; 30-second test part; 31-first test layer of the second test part; 32-second test layer of the second test part; 3n-nth test layer of the second test part; 101-shallow trench isolation structure; 111-first sub-metal layer of the first metal layer; 112-second sub-metal layer of the first metal layer; 121-first sub-metal layer of the second metal layer; 122-second sub-metal layer of the second metal layer; 1n1-first sub-metal layer of the nth metal layer; 1n2-second sub-metal layer of the nth metal layer; 201-first connecting portion; 202-first TLP test pad; 203-first WAT test pad; 301-second connecting portion; 302-second TLP test pad; 303-second WAT test pad. DETAILED DESCRIPTION
[0026] A test structure diagram of the utility model will be further described in detail below. The utility model will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the utility model are shown. It should be understood that those skilled in the art can modify the utility model described herein and still achieve the beneficial effects of the utility model. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the utility model.
[0027] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would make the utility model confusing with unnecessary details. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just routine work for those skilled in the art.
[0028] In order to make the purpose and features of the utility model more obvious and easy to understand, the specific implementation of the utility model is further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0029] like Figure 1-Figure 2As shown, this embodiment provides a test structure layout, including a device part 10, a first test part 20 and a second test part 30, wherein the first test part 20 and the second test part 30 are arranged on both sides of the device part 10, and are symmetrically arranged along the midline of the device part 10 in the first direction, the device part 10 includes a plurality of interdigitated finger structures arranged at intervals along the second direction, and all the interdigitated finger structures are symmetrically arranged along the midline of the device part 10 in the second direction, the gates and sources of all the interdigitated finger structures are connected in parallel to the first test part 20, and the drains of all the interdigitated finger structures are connected in parallel to the second test part 30, wherein the first direction and the second direction are perpendicular to each other, the first direction is parallel to the midline of the device part 10 in the second direction, and the second direction is parallel to the midline of the device part 10 in the first direction;
[0030] During testing, the first testing part 20 is grounded, and the second testing part 30 is connected to a working voltage.
[0031] In this embodiment, the first test part 20 and the second test part 30 are symmetrically arranged on the midline of the device part 10 along the first direction, and all the finger structures are symmetrically arranged on the midline of the device part 10 along the second direction, so that the device part 10 is a symmetrical structure, and the first test part 20 and the second test part 30 are symmetrical structures. Therefore, when the test structure layout is tested, the current can flow uniformly from the second test part 30 through each finger structure to the first test structure 20, so that the voltage at both ends of each finger structure is consistent, so that all MOS transistors (i.e., finger structures) can be turned on at the same time.
[0032] Detailed, such as Figure 1-Figure 2 As shown, the device portion 10 is disposed in an active area surrounded by a shallow trench isolation structure 101, and the device structure 10 includes a plurality of interdigital finger structures, the gates and sources of all the interdigital finger structures are connected in parallel to the first test portion 20, and the drains of all the interdigital finger structures are connected in parallel to the second test portion 30.
[0033] The active area is rectangular, and the side of the active area in the first direction is defined as the first side, and the side of the active area in the second direction is defined as the second side. The device structure 10 is symmetrically arranged along the perpendicular bisector of the second side, that is, all the finger structures are symmetrically arranged along the perpendicular bisector of the second side, and the first test part 20 and the second test part 30 are symmetrically arranged along the perpendicular bisector of the first side.
[0034] It should be noted that the interdigital structure refers to a single MOS transistor in the shape of an interdigital finger. The reasons for making the MOS transistor into an interdigital finger structure are: on the one hand, based on the layout considerations, the aspect ratio of the transistor in the analog circuit design may be very large, so it is necessary to make an interdigital finger structure; on the other hand, based on the large aspect ratio of the MOS transistor, the interdigital finger structure can also reduce the gate parasitic resistance; on the other hand, based on the considerations at high frequencies, the noise of the gate resistance can also be reduced.
[0035] like Figure 3 As shown, the device part 10 includes a device main body part arranged in a substrate Sub and a device interconnection layer located above the device main body part, the device main body part includes a source region S, a drain region D and a body region B located in the substrate Sub, a gate structure G located on the substrate Sub, the source region S and the body region B are simultaneously arranged in the substrate Sub on one side of the gate structure G, and the drain region D is located in the substrate Sub on the other side of the gate structure G. In this embodiment, the source region S and the body region B are arranged in intervals by an isolation structure.
[0036] The device interconnection layer includes a first metal layer to an nth metal layer which are sequentially arranged from bottom to top, wherein n≥3 and is a positive integer. In the device interconnection layer, the first metal layer includes a first sub-metal layer 111 and a second sub-metal layer 112 which are arranged at intervals, the first sub-metal layer 111 is connected to the body region B, the source region S and the gate structure G through a conductive contact hole, and the second sub-metal layer 112 is connected to the drain region D through at least one conductive contact hole. The second metal layer to the nth metal layer include a first sub-metal layer and a second sub-metal layer that are spaced apart. The first sub-metal layer 121 of the second metal layer is connected to the first sub-metal layer 111 of the first metal layer through a conductive via, and the second sub-metal layer 122 of the second metal layer is connected to the second sub-metal layer 112 of the first metal layer through a conductive via. Similarly, the first sub-metal layer 1n1 of the nth metal layer is connected to the first sub-metal layer of the n-1th metal layer through a conductive via, and the second sub-metal layer 1n2 of the nth metal layer is connected to the second sub-metal layer of the n-1th metal layer through a conductive via. All of the first sub-metal layers are connected to the first test part 20, and all of the second sub-metal layers are connected to the second test part 30.
[0037] See also Figure 1-Figure 3The first test part 20 and the second test part 30 are arranged on both sides of the device part 10, and are symmetrically arranged along the perpendicular midline y of the first side. The first test part 20 and the second test part 30 both include a first test layer to an nth test layer arranged sequentially from bottom to top. In the first test part 20 and the second test part 30, the second test layer is connected to the first test layer through at least one conductive via, and the nth test layer is connected to the n-1th test layer through at least one conductive via. The first test layer 21 of the first test part 20, the first test layer 31 of the second test part 30, and the first metal layer of the device interconnection layer are arranged in the same layer with intervals; the second test layer 22 of the first test part 20, the second test layer 32 of the second test part 30, and the second metal layer of the device interconnection layer are arranged in the same layer, and the second test layer 22 of the first test part 20 is connected in parallel with the first sub-metal layer 121 of the second metal layer of the device interconnection layer, and the second test layer 32 of the second test part 30 is connected in parallel with the second sub-metal layer 122 of the second metal layer of the device interconnection layer; the n-1th test layer of the first test part 20, the n-1th test layer of the second test part 30, and the n-1th metal layer of the device interconnection layer are arranged in the same layer The n-1 test layer of the first test part 20 is connected to the first sub-metal layer of the n-1 metal layer of the device interconnect layer, and the n-1 test layer of the second test part 30 is connected in parallel to the second sub-metal layer of the n-1 metal layer of the device interconnect layer; the n-1 test layer 2n of the first test part 20, the n-1 test layer 3n of the second test part 30, and the n-1 metal layer of the device interconnect layer are arranged in the same layer, and the n-1 test layer 2n of the first test part 20 is connected in parallel to the first sub-metal layer 1n1 of the n-1 metal layer of the device interconnect layer, and the n-1 test layer 3n of the second test part 30 is connected in parallel to the second sub-metal layer 1n2 of the n-1 metal layer of the device interconnect layer, so that the interconnection wiring resistance (parasitic resistance) R of this embodiment satisfies:
[0038] R=R2*R3*……*Rn / (R2+R3+……+Rn);
[0039] Among them, R2 is the sum of the resistance of the second metal layer, the resistance of the second test layer 22 of the first test structure, and the resistance of the second test layer 32 of the second test part, R3 is the sum of the resistance of the third metal layer, the resistance of the third test layer of the first test structure, and the resistance of the third test layer of the second test part, and Rn is the sum of the resistance of the nth metal layer, the resistance of the nth test layer 2n of the first test structure, and the resistance of the nth test layer 3n of the second test part. The interconnection wiring resistance is smaller than the parasitic resistance in the prior art, which reduces the parasitic resistance, thereby reducing the influence of the parasitic resistance on the damage current test result of the test structure, and reducing the misleading judgment of the ESD capability of the test structure.
[0040] The nth test layer 2n of the first test part 20 includes a first connection part 201, a first TLP test pad 202 and a first WAT test pad 203, and the nth test layer 3n of the second test part 30 includes a second connection part 301, a second TLP test pad 302 and a second WAT test pad 303, the first connection part 201 connects the first sub-metal layer 1n1 of the nth metal layer, the first TLP test pad 202 and the first WAT test pad 203 are arranged at intervals and are both connected to the first connection part 201; the second connection part 301 connects the second sub-metal layer 1n2 of the nth metal layer, the second TLP test pad 302 and the second WAT test pad 303 are arranged at intervals and are both connected to the second connection part 301. The first connection portion 201 and the second connection portion 301 are symmetrically arranged along the perpendicular bisector of the first side, and the first WAT test pad 203 and the second WAT test pad 303 are symmetrically arranged along the perpendicular bisector of the first side; the first TLP test pad 202 and the second TLP test pad 302 are symmetrically arranged along the perpendicular bisector of the first side, and further, the first TLP test pad 202 and the second TLP test pad 302 are symmetrically arranged along the perpendicular bisector of the first side, and at the same time symmetrically arranged along the perpendicular bisector of the second side.
[0041] In this embodiment, since the first test part 20 and the second test part 30 both include TLP test pads and WAT test pads, the same test structure layout can realize automatic BV testing through WAT test pads and manual TLP testing through TLP test pads, that is, two tests can be realized through one test structure, which improves the test efficiency and requires only one test structure for the two tests, thus saving the number of test structures and allowing more test structure layouts to be placed in a limited area, thereby effectively improving the layout area utilization rate.
[0042] In this embodiment, the first connection part 201 and the second connection part 301 are both in the shape of long strips, the first TLP test pad 202 and the second TLP test pad 302 are symmetrically arranged on the outside of the first connection part 201 and the second connection part 301, the first WAT test pad 203 is arranged at one end of the first connection part 201, the second WAT test pad 303 is arranged at one end of the second connection part 301, and the first WAT test pad 203 and the second WAT test pad 303 are arranged on the same side.
[0043] In summary, the utility model provides a test structure layout, including a device part, a first test part and a second test part, the first test part and the second test part are arranged on both sides of the device part, and are symmetrically arranged along the perpendicular midline of the device part in the first direction, the device part includes a plurality of interdigitated finger structures arranged at intervals along the second direction, and all the interdigitated finger structures are symmetrically arranged along the perpendicular midline of the device part in the second direction, the gates and sources of all the interdigitated finger structures are connected in parallel to the first test part, and the drains of all the interdigitated finger structures are connected in parallel to the second test part, wherein the first direction and the second direction are perpendicular to each other, the first direction is parallel to the perpendicular midline of the device part in the second direction, and the second direction is parallel to the perpendicular midline of the device part in the first direction; during testing, the first test part is grounded and the second test part is connected to the working voltage. In the utility model, the first test part and the second test part are symmetrically arranged on the perpendicular midline of the device part along the first direction, and all the finger structures are symmetrically arranged on the perpendicular midline of the device part along the second direction, so that the device part is a symmetrical structure, and the first test part and the second test part are symmetrical structures. Therefore, when the test structure layout is tested, the current can flow from the second test part through each finger structure to the first test structure evenly, so that the voltages at both ends of each finger structure are consistent, so that all MOS transistors (i.e., finger structures) can be turned on at the same time.
[0044] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0045] It is understandable that, although the utility model has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the utility model. For any technician familiar with the art, without departing from the scope of the technical solution of the utility model, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still falls within the scope of protection of the technical solution of the utility model.
Claims
1. A test structure layout, characterized in that: The device comprises a device part, a first test part and a second test part, wherein the first test part and the second test part are arranged on both sides of the device part and are symmetrically arranged along the perpendicular midline of the device part in the first direction, the device part comprises a plurality of interdigitated finger structures arranged at intervals along the second direction, and all the interdigitated finger structures are symmetrically arranged along the perpendicular midline of the device part in the second direction, the gates and sources of all the interdigitated finger structures are connected in parallel to the first test part, and the drains of all the interdigitated finger structures are connected in parallel to the second test part, wherein the first direction and the second direction are perpendicular to each other, the first direction is parallel to the perpendicular midline of the device part in the second direction, and the second direction is parallel to the perpendicular midline of the device part in the first direction; During testing, the first testing part is grounded, and the second testing part is connected to a working voltage.
2. The test structure layout according to claim 1, characterized in that: The device part is arranged in an active area surrounded by a shallow trench isolation structure, the active area is rectangular, and the active area is provided with a first side and a second side, the first side is arranged along the first direction, and the second side is arranged along the second direction.
3. The test structure layout as claimed in claim 2, characterized in that: All the finger structures are symmetrically arranged along the perpendicular midline of the second side, and the first test portion and the second test portion are symmetrically arranged along the perpendicular midline of the first side.
4. The test structure layout as claimed in claim 2, characterized in that: The device part includes a connected device main body part and a device interconnection layer, the device main body part includes a source region, a drain region and a body region located in a substrate, and a gate structure located on the substrate; the device interconnection layer includes a first metal layer to an nth metal layer arranged in sequence from bottom to top, wherein n≥3 and is a positive integer.
5. The test structure layout as claimed in claim 4, characterized in that: The first metal layer to the nth metal layer all include a first sub-metal layer and a second sub-metal layer that are spaced apart, the first sub-metal layer of the first metal layer simultaneously connects the body region, the source region and the gate structure, the second sub-metal layer of the first metal layer is connected to the drain region, and the first sub-metal layer of the first metal layer to the first sub-metal layer of the nth metal layer are connected in sequence, the second sub-metal layer of the first metal layer to the second sub-metal layer of the nth metal layer are connected in sequence, all of the first sub-metal layers are connected to the first test portion, and all of the second sub-metal layers are connected to the second test portion.
6. The test structure layout according to claim 5, characterized in that: The first test section and the second test section both include a first test layer to an nth test layer sequentially arranged from bottom to top, the first test layer to the nth test layer of the first test section are sequentially connected, and the first test layer to the nth test layer of the second test section are sequentially connected; The first test layer of the first test part, the first test layer of the second test part, and the first metal layer of the device interconnection layer are arranged in the same layer with intervals; the second test layer of the first test part, the second test layer of the second test part, and the second metal layer are arranged in the same layer, and the second test layer of the first test part is connected in parallel with the first sub-metal layer of the second metal layer, and the second test layer of the second test part is connected in parallel with the second sub-metal layer of the second metal layer; the nth test layer of the first test part, the nth test layer of the second test part, and the nth metal layer are arranged in the same layer, and the nth test layer of the first test part is connected in parallel with the first sub-metal layer of the n metal layer, and the nth test layer of the second test part is connected in parallel with the second sub-metal layer of the n metal layer.
7. The test structure layout according to claim 6, characterized in that: The nth test layer of the first test part includes a first connection portion, a first TLP test pad and a first WAT test pad, and the nth test layer of the second test part includes a second connection portion, a second TLP test pad and a second WAT test pad, the first connection portion connects the first sub-metal layer of the nth metal layer, the first TLP test pad and the first WAT test pad are spaced apart and both are connected to the first connection portion; the second connection portion connects the second sub-metal layer of the nth metal layer, the second TLP test pad and the second WAT test pad are spaced apart and both are connected to the second connection portion.
8. The test structure layout according to claim 7, characterized in that: The first TLP test pad and the second TLP test pad are symmetrically arranged along the perpendicular midline of the first side, and are also symmetrically arranged along the perpendicular midline of the second side.
9. The test structure layout according to claim 7, characterized in that: The first connection part and the second connection part are both in the shape of long strips, the first TLP test pad and the second TLP test pad are symmetrically arranged on the outside of the first connection part and the second connection part, the first WAT test pad is arranged at one end of the first connection part, the second WAT test pad is arranged at one end of the second connection part, and the first WAT test pad and the second WAT test pad are arranged on the same side.
Citation Information
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