Sub-controller of super capacitor

Abstract

The utility model discloses a super capacitor sub-controller comprising a control circuit board, and a super capacitor management unit, a super capacitor monomer input unit, a temperature acquisition unit, a balance execution unit, an ISOSPI communication unit, a DC-DC boost unit, an encryption and decryption unit, an acquisition terminal and a power supply communication terminal which are integrated on the control circuit board. According to the utility model, the super-capacitor sub-controller is effectively prevented from being cracked, the safe and reliable operation is improved, the normal operation of the whole system is not influenced by the single-point fault of the sub-controller, the problem of power supply limitation is solved, and the wire harness is easy to process, install and maintain.

Description

Technical Field

[0001] The utility model relates to the technical field of supercapacitor management equipment, and in particular to a supercapacitor sub-controller. Background Art

[0002] With the rapid development of new energy vehicles, rail transit, power storage and other fields, higher requirements are placed on energy storage devices with high power density and high cycle life. As a new type of energy storage device, supercapacitors have the advantages of fast charging and discharging speed and long cycle life, and have been widely used in the above fields. In order to meet the application requirements of high power and large capacity, it is usually necessary to use multiple series-parallel supercapacitors to form a module. This multi-series series-parallel structure puts higher requirements on the control system, requiring reliable collection, communication, power supply and other functions, and also requires a reasonable terminal layout to meet the compact design. In actual applications, existing supercapacitor sub-controllers have single point failure risks or face various failures in communication, power supply and data security, which may affect the performance and reliability of the entire system.

[0003] Existing supercapacitor sub-controllers face information security threats. If the supercapacitor sub-controller is damaged or manipulated, the supercapacitor module can be maliciously operated through the supercapacitor sub-controller to charge, discharge, balance or shut down the protection function, which will directly affect the safety of vehicle and energy operation and cause serious security threats. In addition, existing supercapacitor sub-controllers usually adopt an ISOSPI unidirectional series structure. When one of the supercapacitor sub-controllers fails, the subsequent supercapacitor sub-controllers can no longer communicate. Moreover, power is usually taken from the supercapacitor cells in series, and there are certain restrictions on the minimum number of supercapacitor cells connected and the discharge of supercapacitors.

[0004] Therefore, the applicant has found a solution to the above-mentioned problem through beneficial exploration and research, and the technical solution to be introduced below is produced in this context. Utility Model Content

[0005] The technical problem to be solved by the utility model is: to provide a supercapacitor sub-controller with two-way communication encryption, dual power supply, compact layout, and effective guarantee of safe operation of control system and energy system in view of the deficiencies of the prior art.

[0006] The technical problem to be solved by the present invention can be achieved by adopting the following technical solutions:

[0007] A supercapacitor sub-controller, comprising:

[0008] Control circuit board;

[0009] A supercapacitor management unit integrated on the control circuit board for collecting data such as supercapacitor cell voltage and temperature and performing supercapacitor cell balancing actions, encrypting data and communicating with a main controller;

[0010] A supercapacitor cell input unit integrated on the control circuit board and connected to the supercapacitor management unit for collecting voltage signals of supercapacitor cells and supplying power to the supercapacitor management unit;

[0011] A temperature acquisition unit integrated on the control circuit board and connected to the supercapacitor management unit for acquiring temperature signals of supercapacitor cells and temperature signals of the control circuit board;

[0012] A balancing execution unit integrated on the control circuit board and connected to the supercapacitor management unit for performing balancing control on supercapacitor cells according to a control instruction sent by the supercapacitor management unit;

[0013] An ISOSPI communication unit integrated on the control circuit board and connected to the supercapacitor management unit for realizing sub-controller cascading and external data interaction;

[0014] A DC-DC boost unit integrated on the control circuit board and connected to the supercapacitor management unit for performing boost and isolation processing on an input external power source and supplying power to the supercapacitor management unit;

[0015] An encryption and decryption unit integrated on the control circuit board and connected to the supercapacitor management unit for encrypting and decrypting data;

[0016] A collection terminal integrated on the control circuit board and connected to the supercapacitor monomer input unit and the temperature collection unit respectively; and

[0017] A power communication terminal is integrated on the control circuit board and is respectively connected to the ISOSPI communication unit and the DC-DC boost unit.

[0018] In a preferred embodiment of the present utility model, the supercapacitor monomer input unit includes a resistor-capacitor filter circuit and a first overvoltage protection circuit, the input end of the resistor-capacitor filter circuit is connected to the acquisition terminal, the output end thereof is connected to the input end of the first overvoltage protection circuit, and the output end of the first overvoltage protection circuit is connected to the supercapacitor management unit.

[0019] In a preferred embodiment of the utility model, the temperature acquisition unit includes several NTC thermistors, a temperature signal filtering circuit and a second overvoltage protection circuit, wherein one end of several NTC thermistors are respectively connected to the acquisition terminal, and the other end thereof is respectively connected to the input end of the temperature signal filtering circuit, and one end of several other NTC thermistors are respectively connected to the control circuit board, and the other end thereof is respectively connected to the input end of the temperature signal filtering circuit, the output end of the temperature signal filtering circuit is connected to the input end of the second overvoltage protection circuit, and the output end of the second overvoltage protection circuit is connected to the supercapacitor management unit.

[0020] In a preferred embodiment of the utility model, the balancing execution unit includes a plurality of discharge resistors and a plurality of MOS tubes, each discharge resistor is connected in parallel to a corresponding supercapacitor cell, and each MOS tube is connected to the corresponding discharge resistor on one hand to control the conduction of the discharge resistor, and is connected to the supercapacitor management unit on the other hand to control its on-off state.

[0021] In a preferred embodiment of the present utility model, the ISOSPI communication unit adopts a bidirectional ISOSPI communication structure.

[0022] In a preferred embodiment of the utility model, the DC-DC boost unit includes a flyback boost circuit, a protection device, an isolation transformer and a DC-DC chip. The input 12V / 24V power supply is boosted to 50V through the flyback boost circuit, the protection device, the isolation transformer and the DC-DC chip in sequence to power the supercapacitor management unit.

[0023] In a preferred embodiment of the present utility model, the encryption and decryption unit uses an STC8G1K08A single-chip microcomputer to perform encryption and decryption operations, and is connected to the supercapacitor management unit via an IIC / SPI internal bus.

[0024] In a preferred embodiment of the present utility model, the acquisition terminal and the power communication terminal are located on both sides of the control circuit board.

[0025] In a preferred embodiment of the present invention, the acquisition terminal is a 32-port serial acquisition terminal.

[0026] In a preferred embodiment of the present invention, the power communication terminal adopts a double-terminal design.

[0027] Due to the adoption of the above technical solution, the beneficial effects of the utility model are:

[0028] 1. The utility model uses an encryption and decryption unit to encrypt and decrypt data, which can effectively prevent the supercapacitor controller from being cracked and ensure the safe and reliable operation of the controller in electric vehicles, rail transportation, and energy storage systems;

[0029] 2. The utility model adopts bidirectional ISOSPI for communication to avoid single point failure causing stagnation of the entire control system and ensure that single point failure of the sub-controller does not affect the normal operation of the entire system;

[0030] 3. The utility model adopts dual power management of taking power from the supercapacitor module and DC-DC boost isolation power supply, which solves some existing limiting problems, such as the minimum limit on the number of supercapacitor monomers, the limit on the discharge depth, and the impact of taking power from the supercapacitor module on the module energy consumption. It is widely applicable to supercapacitors such as double-layer supercapacitors (EDLC), Faraday pseudo-supercapacitors, and lithium-ion supercapacitors (LIC);

[0031] 4. The utility model adopts acquisition terminals and power communication terminals distributed on both sides of the control circuit board. The power communication terminals adopt double terminal form. The reasonable terminal layout not only meets the compact design, but also strengthens the electromagnetic isolation and heat dissipation design of the product, which is easy for wiring harness processing, installation and maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is a structural schematic diagram of the utility model.

[0034] Figure 2 It is a power supply schematic diagram of the utility model.

[0035] Figure 3 It is a cascade schematic diagram of the utility model.

[0036] Figure 4 It is a schematic diagram of the terminal layout of the utility model. DETAILED DESCRIPTION

[0037] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below with reference to specific illustrations.

[0038] See also Figure 1The figure shows a supercapacitor sub-controller, including a control circuit board 100, a supercapacitor management unit 200, a supercapacitor monomer input unit 300, a temperature acquisition unit 400, a balancing execution unit 500, an ISOSPI communication unit 600, a DC-DC boost unit 700, an encryption and decryption unit 800, an acquisition terminal 910 and a power communication terminal 920.

[0039] The control circuit board 100 serves as a carrier of various components of the supercapacitor sub-controller, and can be a single-layer hard circuit board.

[0040] The supercapacitor management unit 200 is integrated on the control circuit board 100, which can be powered by the supercapacitor monomer input unit 300 or the DC-DC boost unit 700, is responsible for data exchange with the main controller through the ISOSPI communication unit 600, is responsible for processing supercapacitor signals such as voltage and temperature, controls the balancing execution unit 500 to achieve monomer voltage balancing processing through the received control command, and the encryption and decryption unit 800 communicates through the internal bus IIC / SPI to verify data security. In this embodiment, the supercapacitor management unit 200 uses the LTC6813 supercapacitor group monitor.

[0041] The supercapacitor cell input unit 300 is integrated on the control circuit board 100 and connected to the supercapacitor management unit 200, and is used to collect the voltage signal of the supercapacitor cell and supply power to the supercapacitor management unit 200. In this embodiment, the supercapacitor cell input unit 300 includes a resistor-capacitor filter circuit and a first overvoltage protection circuit, the input end of the resistor-capacitor filter circuit is connected to the collection terminal 910, and the output end thereof is connected to the input end of the first overvoltage protection circuit, and the output end of the first overvoltage protection circuit is connected to the supercapacitor management unit 200. The supercapacitor cell input unit 300 processes the cell voltage using the resistor-capacitor filter circuit and the first overvoltage protection circuit, and outputs it to the supercapacitor management unit 200, so that the measurement of the supercapacitor management unit 200 is more accurate.

[0042] The temperature acquisition unit 400 is integrated on the control circuit board 100 and connected to the supercapacitor management unit 200, and is used to collect the temperature signal of the supercapacitor monomer and the temperature signal of the control circuit board 100. In this embodiment, the temperature acquisition unit 400 includes a plurality of NTC thermistors, a temperature signal filter circuit and a second overvoltage protection circuit, wherein one end of the plurality of NTC thermistors is respectively connected to the acquisition terminal 910, and the other end thereof is respectively connected to the input end of the temperature signal filter circuit, and one end of the plurality of NTC thermistors is respectively connected to the control circuit board 100, and the other end thereof is respectively connected to the input end of the temperature signal filter circuit, and the output end of the temperature signal filter circuit is connected to the input end of the second overvoltage protection circuit, and the output end of the second overvoltage protection circuit is connected to the supercapacitor management unit 200. The temperature acquisition unit 400 is connected to 4 external 100k, 4250B value type NTC thermistors through the acquisition terminal 910, and is connected to 2 internal 100k, 4250B value type NTC thermistors, for detecting the temperature of the control circuit board 100 itself. The main controller performs some actions through the balancing execution unit 500 according to the temperature data provided by the temperature acquisition unit 400 to protect the supercapacitor monomer.

[0043] The balancing execution unit 500 is integrated on the control circuit board 100 and connected to the supercapacitor management unit 200, and is used to balance the supercapacitor cells according to the control instructions sent by the supercapacitor management unit 200. In this embodiment, the balancing execution unit 500 includes a plurality of discharge resistors and a plurality of MOS tubes, each discharge resistor is connected in parallel to the corresponding supercapacitor cell, each MOS tube is connected to the corresponding discharge resistor on one hand, for controlling the conduction of the discharge resistor, and is connected to the supercapacitor management unit 200 on the other hand, and its on-off state is controlled by the supercapacitor management unit 200. The balancing execution unit 500 adopts a passive balancing method, by connecting a discharge resistor whose conduction is controlled by the MOS tube in parallel to each supercapacitor cell, and the on-state of the MOS tube is controlled by the supercapacitor management unit 200. The supercapacitor management unit 200 receives the control instructions of the main controller through the ISOSPI communication unit 600, and controls the on-off of the MOS tube according to the control instructions, thereby realizing the balanced control of the supercapacitor cells.

[0044] The ISOSPI communication unit 600 is integrated on the control circuit board 100 and connected to the supercapacitor management unit 200, and is used to realize sub-controller cascading and external data interaction. The ISOSPI communication unit 600 adopts a bidirectional ISOSPI design, that is, a bidirectional ISOSPI communication structure is used for supercapacitor sub-controller cascading and supercapacitor management unit 200 communicating with the main controller, to avoid the failure of a supercapacitor sub-controller in the unidirectional ISOSPI, and the subsequent supercapacitor sub-controllers cannot communicate. The connection method is as follows Figure 3 shown.

[0045] The DC-DC boost unit 700 is integrated on the control circuit board 100 and connected to the supercapacitor management unit 200, and is used to boost and isolate the input external power supply and supply power to the supercapacitor management unit 200. In this embodiment, the DC-DC boost unit 700 includes a flyback boost circuit, a protection device, an isolation transformer and a DC-DC chip. The input 12V / 24V power supply is boosted to 50V by the flyback boost circuit, the protection device, the isolation transformer and the DC-DC chip in turn to supply power to the supercapacitor management unit. Figure 2 When the voltage of the cascaded supercapacitor monomer is higher than 50V, the supercapacitor management unit 200 is powered by the supercapacitor monomer input unit 300, and when the voltage of the cascaded monomer is lower than 50V, the DC-DC boost unit 700 provides power. At this time, the supercapacitor sub-controller is free from the influence of the minimum number of connected monomers, the discharge depth limit, and the influence of power consumption from the supercapacitor monomer on the supercapacitor energy consumption, and can be applied to supercapacitors such as EDLC that can be discharged to zero volts.

[0046] The encryption and decryption unit 800 is integrated on the control circuit board 100 and connected to the supercapacitor management unit 200, and is used to perform encryption and decryption processing on the data. In this embodiment, the encryption and decryption unit 800 uses the STC8G1K08A single-chip microcomputer to perform encryption and decryption operations, is connected to the supercapacitor management unit 200 through the IIC / SPI internal bus, receives the encrypted message from the main controller, and performs decryption verification on the encrypted message. When the decryption verification fails, the supercapacitor management unit 200 is controlled to stop supercapacitor information collection, balancing and other operations to provide information security.

[0047] The acquisition terminal 910 is integrated on the control circuit board 100 and is respectively connected to the super capacitor cell input unit 300 and the temperature acquisition unit 400. The power communication terminal 920 is integrated on the control circuit board 100 and is respectively connected to the ISOSPI communication unit 600 and the DC-DC boost unit 700. Figure 4 The acquisition terminal 910 and the power communication terminal 920 are located on both sides of the control circuit board 100, which can improve the electromagnetic isolation of the sub-controller and the heat dissipation capacity of the circuit board. The acquisition terminal 910 adopts a 32-port acquisition terminal, and the power communication terminal 920 adopts a double-terminal design, which is easy to process, install and maintain the wiring harness of the terminal.

[0048] The working principle of the supercapacitor sub-controller of the utility model is as follows:

[0049] The acquisition terminal 910 distributed on one side of the control circuit board 100 supports 32 strings of supercapacitor cells to be connected to the supercapacitor management unit 200 through the supercapacitor cell input unit 300, and supports 4-way temperature acquisition to be connected to the supercapacitor management unit 200 through the temperature acquisition unit 400. The power communication terminal 920 adopts a dual-terminal design, supports 12 / 24V external power supply to be connected to the DC-DC boost unit 700 and ISOSPI communication line to be connected to the ISOSPI communication unit 600, and uses the DC-DC boost unit 700 or the supercapacitor cell input unit 300 to provide working power for the supercapacitor management unit 200. The main controller controls the supercapacitor management unit 200 to sample the voltage and temperature of the supercapacitor cell through the bidirectional redundant ISOSPI communication unit 5. The main controller allows the supercapacitor management unit 200 to control the balancing execution unit 500 according to the sampling value, and the balancing execution unit 500 controls the MOS tube switch for single-cell voltage balancing to realize the power discharge of the high-voltage single cell; the data transmitted through the ISOSPI communication unit 600 is encrypted and decrypted and verified by the encryption and decryption unit 800. If the encryption and decryption pairing is successful, the supercapacitor voltage, temperature and other data of the current supercapacitor sub-controller are collected once. If it fails, the supercapacitor management unit 200 stops the supercapacitor single cell information collection, balancing and other operations to prevent the sensitive information of the supercapacitor from being stolen.

[0050] The above shows and describes the basic principle and main features of the utility model and the advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only for explaining the principle of the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection claimed by the utility model is defined by the attached claims and their equivalents.

Claims

1. A supercapacitor sub-controller, characterized in that: include: Control circuit board; A supercapacitor management unit integrated on the control circuit board for collecting supercapacitor cell voltage and temperature data and performing supercapacitor cell balancing actions, encrypting data and communicating with a main controller; A supercapacitor cell input unit integrated on the control circuit board and connected to the supercapacitor management unit for collecting voltage signals of supercapacitor cells and supplying power to the supercapacitor management unit; A temperature acquisition unit integrated on the control circuit board and connected to the supercapacitor management unit for acquiring temperature signals of supercapacitor cells and temperature signals of the control circuit board; A balancing execution unit integrated on the control circuit board and connected to the supercapacitor management unit for performing balancing control on supercapacitor cells according to a control instruction sent by the supercapacitor management unit; An ISOSPI communication unit integrated on the control circuit board and connected to the supercapacitor management unit for realizing sub-controller cascading and external data interaction; A DC-DC boost unit integrated on the control circuit board and connected to the supercapacitor management unit for performing boost and isolation processing on an input external power source and supplying power to the supercapacitor management unit; An encryption and decryption unit integrated on the control circuit board and connected to the supercapacitor management unit for encrypting and decrypting data; A collection terminal integrated on the control circuit board and connected to the supercapacitor monomer input unit and the temperature collection unit respectively; as well as A power communication terminal is integrated on the control circuit board and is respectively connected to the ISOSPI communication unit and the DC-DC boost unit.

2. The supercapacitor sub-controller according to claim 1, characterized in that: The supercapacitor monomer input unit includes a resistor-capacitor filter circuit and a first overvoltage protection circuit, the input end of the resistor-capacitor filter circuit is connected to the acquisition terminal, the output end of the resistor-capacitor filter circuit is connected to the input end of the first overvoltage protection circuit, and the output end of the first overvoltage protection circuit is connected to the supercapacitor management unit.

3. The supercapacitor sub-controller according to claim 1, characterized in that: The temperature acquisition unit includes a plurality of NTC thermistors, a temperature signal filtering circuit and a second overvoltage protection circuit, wherein one end of the plurality of NTC thermistors is respectively connected to the acquisition terminal, and the other end thereof is respectively connected to the input end of the temperature signal filtering circuit, and one end of another plurality of NTC thermistors is respectively connected to the control circuit board, and the other end thereof is respectively connected to the input end of the temperature signal filtering circuit, the output end of the temperature signal filtering circuit is connected to the input end of the second overvoltage protection circuit, and the output end of the second overvoltage protection circuit is connected to the supercapacitor management unit.

4. The supercapacitor sub-controller according to claim 1, characterized in that: The balancing execution unit includes a plurality of discharge resistors and a plurality of MOS tubes, each discharge resistor is connected in parallel to a corresponding supercapacitor monomer, each MOS tube is connected to the corresponding discharge resistor on one hand to control the conduction of the discharge resistor, and is connected to the supercapacitor management unit on the other hand to control its on-off state.

5. The supercapacitor sub-controller according to claim 1, characterized in that: The ISOSPI communication unit adopts a bidirectional ISOSPI communication structure.

6. The supercapacitor sub-controller according to claim 1, characterized in that: The DC-DC boost unit includes a flyback boost circuit, a protection device, an isolation transformer and a DC-DC chip. The input 12V / 24V power supply is boosted to 50V through the flyback boost circuit, the protection device, the isolation transformer and the DC-DC chip in sequence to power the supercapacitor management unit.

7. The supercapacitor sub-controller according to claim 1, characterized in that: The encryption and decryption unit uses an STC8G1K08A single-chip microcomputer to perform encryption and decryption operations, and is connected to the supercapacitor management unit via an IIC / SPI internal bus.

8. The supercapacitor sub-controller according to claim 1, characterized in that: The acquisition terminal and the power communication terminal are located on both sides of the control circuit board.

9. The supercapacitor sub-controller according to claim 8, characterized in that: The acquisition terminal adopts a 32 serial port acquisition terminal.

10. The supercapacitor sub-controller according to claim 8, characterized in that: The power communication terminal adopts a double-terminal design.

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