Buffer circuit for driving GaN power switch and corresponding driver circuit

Abstract

The utility model relates to a buffer circuit for driving a GaN power switch and a corresponding driver circuit. A buffer circuit for driving a GaN power switch includes an input node that receives an input signal and an output node that generates a gated signal for the GaN power switch. The buffer includes a push-pull stage including a first transistor coupled between a supply voltage node and an output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive an input signal and generate respective drive signals for a first transistor, a second transistor, a third transistor, and a fourth transistor to generate a gating signal at an output node in four successive stages.

Description

Technical Field

[0001] The present disclosure relates to a buffer circuit and a corresponding driver circuit for driving a GaN power switch. The present disclosure relates to a gate driver device for high voltage (HV) applications, and more particularly to a gate driver device implemented in monolithic gallium nitride (GaN) technology.

[0002] Such devices may be applied, for example, to power converters (eg, chargers, adapters, etc.) used in various applications (eg, automotive, industrial, consumer applications). Background Art

[0003] As global energy demand continues to increase, improving power conversion efficiency is a desired feature. In addition, portable devices are becoming smaller and lighter, making heat dissipation more difficult. Therefore, recent research focuses on overcoming the limitations of conventional silicon-based devices to improve the performance of integrated electronic systems, with the trend toward smaller size, higher switching frequency and lower power consumption of power systems.

[0004] The first step towards improved power conversion systems is represented by System-in-Package (SiP) solutions such as Figure 1 , which shows a half-bridge power stage in a SiP including a high voltage gate driver and a GaN high electron mobility transistor (HEMT) totem pole output stage (e.g., designed for a 650V output voltage). Examples of such SiP solutions include devices provided by companies of the ST Microelectronics group under the trade name “MASTERGAN” (e.g., as described in data sheets DS13417-Rev3-October 2020, DS13597-Rev2-June 2021, DS13686-Rev1-April 2021, DS13724-Rev 1-May 2021, and DS13775-Rev 1-July 2021, all of which are available on st.com). These SiP solutions, which embed gate drivers in silicon (Si) semiconductor technology and GaN power switches, improve power conversion performance in limited spaces due to improved interconnection between the gate driver Si die and the GaN power transistor. This results in reduced parasitic inductance of the gate loop, reduced critical ringing and associated overvoltage, higher switching frequencies, and reduced system size, weight, and cost.

[0005] like Figure 1As illustrated in FIG. 1 , a conventional power conversion SiP 10 includes: a first (silicon-based) die 12 in which a driver circuit is implemented in Si-BCD (silicon bipolar, CMOS and DMOS) technology, a second (GaN-on-Si based) die 14 in which a high-side GaN HEMT is implemented, and a third (GaN-on-Si based) die 16 in which a low-side GaN HEMT is implemented. The driver circuit 12 has: an input power supply node coupled to an input power supply pad of the SiP 10 to receive a power supply voltage VCC, an input ground node coupled to an input ground pad of the SiP 10 to receive a ground (or reference) voltage GND, an input high-side control node coupled to an input high-side control pad of the SiP 10 to receive a high-side control signal VINH, and an input low-side control node coupled to an input low-side control pad of the SiP 10 to receive a low-side control signal VINL. Signals VINH and VINL are buffered by corresponding buffers 120 and 121, and the buffered signals are passed to an interlock and protection circuit system 122 arranged between a power line VCC and a ground line GND. A level shifter 123 shifts a high-side control signal and passes it to a high-side output buffer 124, and a buffer 125 passes a low-side control signal to a low-side output buffer 126. The bootstrap diode BD has an anode terminal coupled to an input power supply node VCC and a cathode terminal coupled to an output power supply node to generate a bootstrap voltage VBOOT. An electrostatic discharge protection circuit 127 (ESD protection) has a first terminal coupled to an input ground node GND and a second terminal coupled to a power ground node PGND to protect two ground rails (GND and PGND) from electrostatic discharge (ESD) from each other. For example, the ESD circuit 127 may include a pair of anti-parallel diodes coupled between its terminals. Note that the ground nodes GND and PGND, which are independent and mutually protected by the ESD protection circuit 127, represent respective reference terminals for the two portions of the circuit, namely, the signal portion (referenced to GND) and the power portion (referenced to PGND). The high-side output buffer 124 drives a high-side push-pull split-output stage 128, which generates a pair of drive signals (e.g., a turn-on signal and a turn-off signal) for the high-side HEMT 14. The low-side output buffer 126 drives a low-side push-pull split-output stage 129, which generates a pair of drive signals (e.g., a turn-on signal and a turn-off signal) for the low-side HEMT 16. The control (e.g., gate) terminal of the high-side HEMT 14 is coupled (e.g., via a bond wire or conductive track and a resistor R embedded in the package of the SiP 10). GON , R GOFF) to the output node of the push-pull stage 128. The control (eg, gate) terminal of the low-side HEMT 16 is coupled (eg, via a bond wire or conductive track and resistor R embedded in the package of the SiP 10) GON , R GOFF ) to the output node of the push-pull stage 129. The high-side HEMT 14 is coupled between the high voltage power pad VS of the SiP 10 and the output pad VOUT of the SiP 10, and the low-side HEMT 16 is coupled between the output pad VOUT of the SiP 10 and the power ground pad PGND, so that an output drive signal is generated at the output pad VOUT. The high-side output buffer 124 and the high-side push-pull stage 128 are supplied between the bootstrap voltage VBOOT and the output voltage VOUT (e.g., floating ground). The low-side output buffer 126 and the low-side push-pull stage 129 are supplied between the supply voltage PVCC and the power ground voltage PGND.

[0006] In addition to discrete power switch GaN devices, low-voltage transistor manufacturing processes have been developed in GaN technology to allow the realization of monolithic power integrated circuits, with both gate drivers and power switches embedded in the same substrate. The side structure of GaN technology provides the possibility of integrating multiple devices and additional functional blocks on one die, which are usually designed with comparable side technologies (such as Si-BCD). Therefore, compared with silicon-based independent gate drivers, the integrated driver significantly reduces parasitic inductance, which can effectively suppress ringing in the gate loop and enhance the reliability of GaN power switches.

[0007] However, there are some limitations in the design of monolithic GaN integrated circuits because early technology currently provides only n-channel enhancement (e-type) and depletion (d-type) transistors in addition to pn junction diodes and does not provide their complementary p-channel transistors. The lack of complementary p-channel transistors is a challenge for the implementation of push-pull stages, which are simple in CMOS semiconductor technology with symmetrical rise and fall times. Moreover, the lack of complementary transistors can lead to an undesirable increase in static power consumption, especially in digital circuits.

[0008] As a result, high-speed logic circuits in current GaN technology are very power hungry, and the technology is inefficient for implementing complex digital functions. In addition, the design of integrated gate drivers for very high-frequency switching power converters relies on design techniques such as bootstrapping and active pull-ups, which also increase circuit complexity and static power consumption.

[0009] Within this framework, several monolithic gate drivers have been described in the literature [1] to [9]:

[0010] ]

[0011] [2] M. Cui et al., “Monolithic GaN Half-Bridge Stages with Integrated GateDrivers for High Temperature DC-DC Buck Converters,” IEEE Access, 2019, Vol. 7, pp. 184375-184384, doi: 10.1109 / ACCESS.2019.2958059;

[0012] [3] R. Sun et al., “All-GaN Power Integration: Devices to Functional Subcircuits and Converter ICs,” IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 8, No. 1, March 2020, pp. 31–41. doi: 10.1109 / JESTPE.2019.2946418.

[0013] [4] M. Kaufmann and B. Wicht, “A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency,” IEEE Journal of Solid-State Circuits, Vol. 55, No. 12, December 2020, pp. 3169-3178, doi: 10.1109 / JSSC.2020.3018404;

[0014] [5]D. Y. Zhang and M. Rodríguez, "Monolithic Very High Frequency GaN Switched-Mode Power Converters", Proc. of the 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, September 2015, pp. 1-4, doi:10.1109 / CICC.2015.7338386;

[0015] [6] Y. Zhang, M. Rodríguez and D. “Very High Frequency PWM Buck Converters Using Monolithic GaN Half-Bridge Power Stages with Integrated Gate Drivers,” IEEE Transactions on Power Electronics, Vol. 31, No. 11, November 2016, pp. 7926-7942, doi: 10.1109 / TPEL.2015.2513058;

[0016] [7] Y.-Y.Kao et al., "Fully Integrated GaN-on-Silicon Gate Driver and GaNSwitch with Temperature-Compensated Fast Turn-on Technique for AchievingSwitching Frequency of 50MHz and Slew Rate of 118.3V / Ns", IEEE Journal ofSolid-State Circuits, Volume 56, Issue 12, December 2021, Pages 3619-3627, doi: 10.1109 / JSSC.2021.3103875;

[0017] [8] D. Kinzer, "GaN Power IC Technology: Past, Present and Future", Proc. of the 29th International Symposium on Power Semiconductor Devices&ICs (ISPSD), Sapporo, Japan, 2017, pp. 19-24, doi: 10.23919 / ISPSD.2017.7988981;

[0018] [9] H. Xu et al., “Monolithic Integration of Gate Driver and Protection Modules With P-GaN Gate Power HEMTs,” IEEE Transactions on Industrial Electronics, Vol. 69, No. 7, July 2022, pp. 6784–6793, doi: 10.1109 / TIE.2021.3102387.

[0019] However, these gate drivers have certain disadvantages, such as:

[0020] The drivers disclosed in the literature [1], [2], and [3] do not provide rail-to-rail driving;

[0021] The driver disclosed in [4] is affected by the voltage drop across the bootstrap diode;

[0022] The driver disclosed in [5] relies on multiple power supplies and utilizes negative voltages;

[0023] The driver disclosed in [6] utilizes negative voltage; and

[0024] The driver disclosed in [7] is complex because it includes three bootstrap stages.

[0025] Furthermore, comparators in GaN technology are described in

[10] to

[12] :

[0026]

[10] KJ Chen, “GaN Smart Power Chip Technology”, 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, 2009, pp. 403-407, doi:10.1109 / EDSSC.2009.5394230;

[0027]

[11] H. Wang, A. M. H. Wan, Q. Jiang, and K. J. Chen, “A GaN Pulse Width Modulation Integrated Circuit for GaN Power Converters,” IEEE Transactions on Electron Devices, vol. 62, no. 4, pp. 1143–1149, April 2015, doi: 10.1109 / TED.2015.2396649;

[0028]

[12] S.Pennisi, F.Pulvirenti and K.Samperi, "Frequency Compensation Scheme for a Full GaN OpAmp driving 1-nF load", 2022IEEE International Symposium onCircuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2042-2046, doi: 10.1109 / ISCAS48785.2022.9938006.

[0029] However, the comparator disclosed in

[10] has a limited output voltage range (not rail-to-rail), the comparator disclosed in

[11] has a limited supply voltage range, and the comparator disclosed in

[12] has a different architecture (operational amplifier).

[0030] Therefore, there is a need in the art to provide a fully integrated GaN driver circuit that improves reliability, reduces area and packaging cost, and / or reduces (eg, suppresses) parasitic inductance between the driver circuit and the power switch. Utility Model Content

[0031] One or more embodiments facilitate providing such a fully integrated GaN driver circuit, providing a high speed and low power gate driver and power transistor(s) implemented in monolithic GaN technology on the same substrate.

[0032] One or more embodiments include a buffer circuit configured to drive a GaN power switch having the features set out in the accompanying claims.

[0033] One or more embodiments may relate to a corresponding driver circuit.

[0034] The claims form an integral part of the technical teaching provided herein in conjunction with the embodiments.

[0035] In one embodiment, a buffer circuit is configured to drive a GaN power switch. The buffer circuit includes an input node configured to receive an input signal and an output node configured to generate a gate signal for the GaN power switch. The buffer circuit includes a push-pull stage, the push-pull stage including a first transistor and a second transistor whose conduction channel is coupled between a power supply voltage node and an output node, and a third transistor and a fourth transistor whose conduction channel is coupled between the output node and a reference voltage node. The buffer circuit includes a pre-buffer stage, the pre-buffer stage is configured to receive an input signal and generate corresponding drive signals for the first, second, third and fourth transistors to generate a gate signal at the output node in four consecutive stages. In the first stage, the first transistor is turned on, while the second, third and fourth transistors are not turned on. In the second stage, the first and second transistors are turned on, while the third and fourth transistors are not turned on. In the third stage, the third transistor is turned on, while the first, second and fourth transistors are not turned on. In the fourth stage, the third transistor and the fourth transistor are turned on, while the first transistor and the second transistor are not turned on.

[0036] Thus, one or more embodiments may provide a high speed and low power gate driver configured to drive a power transistor implemented in monolithic GaN technology with rail-to-rail drive and reduced power consumption.

[0037] In some embodiments, the push-pull stage further includes: a first resistor arranged in series with the conduction channel of the first transistor; a second resistor coupled between the third transistor and a reference voltage; and a fifth transistor coupled in parallel to the second resistor and controlled by the gate signal.

[0038] In some embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are enhancement mode GaN transistors.

[0039] In some embodiments, the pre-buffer stage includes: a first pre-buffer for driving a first transistor according to an input signal; a first delay and logic circuit for generating a copy of the input signal, the copy having a rising edge delayed relative to a rising edge of the input signal; a second pre-buffer for driving a second transistor according to the copy of the input signal; a third pre-buffer for driving a third transistor according to a complement of the input signal; a second delay and logic circuit for generating a copy of the complement of the input signal, the copy having a rising edge delayed relative to a rising edge of the complement of the input signal; and a fourth pre-buffer for driving a fourth transistor according to a copy of the complement of the input signal.

[0040] In some embodiments, the first pre-buffer includes: a corresponding input node for receiving a corresponding input signal and a corresponding output node for generating a corresponding drive signal; a first depletion-mode transistor and a first enhancement-mode transistor, whose conduction channels are arranged in series between a power supply voltage node and a reference voltage node, wherein a gate terminal of the first enhancement-mode transistor is coupled to the corresponding input node; a second depletion-mode transistor and a second enhancement-mode transistor, whose conduction channels are arranged in series between the power supply voltage node and the reference voltage node, wherein a gate terminal of the second depletion-mode transistor is coupled to a gate terminal of the first depletion-mode transistor, and a gate terminal of the second enhancement-mode transistor is coupled to a node between the first depletion-mode transistor and the first enhancement-mode transistor; a first bootstrap capacitor, coupled between a source terminal of the second depletion-mode transistor and a bootstrap node; a third enhancement-mode transistor, whose conduction channel is arranged between the power supply voltage node and the bootstrap node, and whose gate terminal a first terminal of the bootstrap transistor coupled to the drain terminal of the second enhancement mode transistor; a fourth enhancement mode transistor, whose conduction channel is arranged between the bootstrap node and the reference voltage node, and whose gate terminal is coupled to the gate terminal of the second enhancement mode transistor; a third depletion mode transistor and a second bootstrap capacitor, arranged in series between the power supply voltage node and the bootstrap node, wherein the gate terminal of the third depletion mode transistor is coupled to the gate terminal of the first depletion mode transistor, and the first terminal of the second bootstrap transistor is coupled to the bootstrap node; and a fifth enhancement mode transistor and a sixth enhancement mode transistor, whose conduction channels are arranged in series between the second terminal of the second bootstrap transistor and the reference voltage node, wherein the gate terminal of the fifth enhancement mode transistor is coupled to the gate terminal of the third enhancement mode transistor, and the gate terminal of the sixth enhancement mode transistor is coupled to the gate terminal of the fourth enhancement transistor, wherein the corresponding output node is located between the fifth enhancement transistor and the sixth enhancement transistor.

[0041] In some embodiments, the third pre-buffer includes: a corresponding input node for receiving a corresponding input signal and a corresponding output node for generating a corresponding drive signal; a first depletion-mode transistor and a first enhancement-mode transistor, whose conduction channels are arranged in series between a power supply voltage node and a reference voltage node, wherein a gate terminal of the first enhancement-mode transistor is coupled to the corresponding input node; a second depletion-mode transistor and a second enhancement-mode transistor, whose conduction channels are arranged in series between the power supply voltage node and the reference voltage node, wherein a gate terminal of the second depletion-mode transistor is coupled to a gate terminal of the first depletion-mode transistor, and a gate terminal of the second enhancement-mode transistor is coupled to a node between the first depletion-mode transistor and the first enhancement-mode transistor; a bootstrap capacitor coupled between a source terminal of the second depletion-mode transistor and a corresponding output node; a third enhancement-mode transistor, whose conduction channel is arranged between the power supply voltage node and the corresponding output node, and whose gate terminal is coupled to a drain terminal of the second enhancement-mode transistor; and a fourth enhancement-mode transistor, whose conduction channel is arranged between the corresponding output node and the reference voltage node, and whose gate terminal is coupled to the gate terminal of the second enhancement-mode transistor.

[0042] In some embodiments, the third pre-buffer includes a third depletion-mode transistor having a conduction channel arranged between the power supply voltage node and the corresponding output node and having a gate terminal coupled to a source terminal thereof.

[0043] In one embodiment, a driver circuit includes: an input power pad configured to receive a power supply voltage, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to generate an output drive signal. According to one or more embodiments, the level shifter is configured to shift and pass the high-side control signal to the high-side output buffer circuit. According to one or more embodiments, the low-side intermediate buffer circuit is configured to pass the low-side control signal to the low-side output buffer circuit. The high-side GaN power transistor is arranged between the high-voltage power pad and the output pad, and is driven by the high-side output buffer circuit. The low-side GaN power transistor is arranged between the output pad and the protected ground pad, and is driven by the low-side output buffer circuit.

[0044] In some embodiments, the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor, and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.

[0045] In some embodiments, the GaN semiconductor substrate is a GaN-on-Si semiconductor substrate.

[0046] In some embodiments, the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.

[0047] In some embodiments, the first GaN semiconductor substrate and the second GaN semiconductor substrate are GaN semiconductor substrates.

[0048] In some embodiments, the driver circuit also includes: a first voltage regulator for generating a first regulated voltage based on a power supply voltage; a bootstrap circuit system for generating a bootstrap voltage based on the power supply voltage; and a second voltage regulator for generating a second regulated voltage based on the bootstrap voltage, wherein the low-side output buffer circuit is supplied with the first regulated voltage and the high-side output buffer circuit is supplied with the second regulated voltage.

[0049] In some embodiments, a low-side intermediate buffer circuit includes an input stage, a differential-to-single-ended stage, and an output stage, wherein the input stage includes: an input differential transistor pair, a first transistor of the pair for receiving an input signal at a control terminal thereof, and a second transistor of the pair for receiving a reference signal at a control terminal thereof; a first current generator load coupled between the first transistor and a power supply node of the low-side intermediate buffer circuit; a second current generator load coupled between the second transistor and the power supply node of the low-side intermediate buffer circuit; and a tail current generator coupled between a tail node of the input differential transistor pair and a ground node of the low-side intermediate buffer circuit; and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to a first output node and a second output node of the input differential transistor pair; and wherein the output stage includes a pair of cascaded inverter circuits, a first inverter circuit for receiving a single-ended signal from an output node of the differential-to-single-ended stage, and a second inverter circuit for receiving a complementary signal from an output node of the first inverter circuit to generate an output signal of the low-side intermediate buffer circuit.

[0050] In one embodiment, a method includes receiving an input signal at an input node of a buffer circuit of a driver circuit and generating a gating signal at an output node of the buffer circuit. Generating the gating signal includes: in a first stage, turning on a first transistor of the buffer circuit and making a second transistor, a third transistor, and a fourth transistor of the buffer circuit non-conductive. A channel of the first transistor and a channel of the second transistor are each coupled between a power supply voltage node and an output node, wherein a channel of the third transistor and a channel of the fourth transistor are each coupled between the output node and a reference voltage node. Generating the gating signal includes: in a second stage, turning on the first transistor and the second transistor and making the third transistor and the fourth transistor non-conductive; and in a third stage, turning on the third transistor and making the first transistor, the second transistor, and the fourth transistor non-conductive. Generating the gating signal includes: in a fourth stage, turning on the third transistor and the fourth transistor and making the first transistor and the second transistor non-conductive. The method includes driving a GaN power switch with a gating signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0052] Figure 1 is a circuit block diagram of the system in package as described above;

[0053] Figure 2 is an exemplary circuit block diagram of a monolithic half-bridge power stage in GaN technology according to one or more embodiments of the present specification;

[0054] Figure 3 is an exemplary circuit block diagram of a driver stage using GaN technology according to one or more embodiments of the present specification;

[0055] Figure 4 is an exemplary circuit block diagram of a low-side pre-buffer stage in GaN technology according to one or more embodiments of the present specification;

[0056] Figure 5 is an exemplary circuit block diagram of a high-side pre-buffer stage in GaN technology according to one or more embodiments of the present specification; and

[0057] Figure 6 is an exemplary circuit block diagram of a comparator circuit in GaN technology according to one or more embodiments of the present description. DETAILED DESCRIPTION

[0058] In the following description, one or more specific details will be explained to provide a deeper understanding of the examples of the embodiments of the present specification. The embodiments can be obtained without one or more of these specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments are not obscured.

[0059] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in connection with that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to one and the same embodiment. Moreover, specific configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0060] The headings / reference numbers used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0061] In all the drawings attached hereto, similar parts or elements are indicated by similar reference numerals / labels, unless the context indicates otherwise, and the corresponding description will not be repeated for the sake of brevity.

[0062] As contemplated, one or more embodiments relate to fully integrated GaN driver circuits, for example, incorporating a monolithic half-bridge power stage and associated driver circuitry in GaN technology (particularly GaN on Si technology), as in Figure 2 As illustrated in the circuit block diagram. Figure 2 The functionality of the circuit illustrated in Figure 1 The functionality of the SiP 10 illustrated in FIG. 1 is similar, but it is implemented entirely in GaN technology (on a silicon substrate).

[0063] The fully integrated GaN driver circuit 20 has: an input power node coupled to an input power pad to receive a power supply voltage VCC, an input ground node coupled to an input ground pad to receive a ground (or reference) voltage GND, an input high voltage side control node coupled to an input high side control pad to receive a high side control signal VINH, and an input low side control node coupled to an input low side control pad to receive a low side control signal VINL (e.g., signals VINH and VINL are PWM signals from an external microcontroller). Signals VINH and VINL are cached by corresponding input buffers (e.g., comparators) 220 and 221, and the cached signals are passed to an interlock and protection circuit 222. Buffers 220 and 221 can implement hysteresis to improve the stability of voltage transitions. Interlock and protection circuit 222 is configured to shut down the power stage in the event of undervoltage and / or overtemperature, and if the two input signals VINH, VINL are inadvertently asserted at the same time (e.g., set to a high logic value), then prevent the two power switches of the half bridge from being turned on at the same time. The voltage regulator REG1 (e.g., a low dropout linear regulator) is arranged between the power line VCC and the ground line GND and generates a regulated voltage VREG (e.g., stable and unchanged with respect to temperature and the power supply voltage VCC). The interlock and protection circuit 222 is supplied between the regulated voltage VREG and the ground voltage GND. The (e.g., high interference resistance) level shifter 223 shifts the high-side control signal from the circuit 222 and passes it to the trigger FF. The output from the trigger FF is passed to the high-side output buffer circuit 224. The (e.g., high interference resistance) low-side intermediate buffer (e.g., comparator) 225 passes the low-side control signal from the circuit 222 to the low-side output buffer circuit 226. The buffer 225 can implement hysteresis to improve the stability of the voltage transition. The anode terminal of the bootstrap diode BD is coupled to the input power node VCC, and its cathode terminal is coupled to the output power node to generate the bootstrap voltage VBOOT. Electrostatic discharge protection circuit 227 (ESD protection) has a first terminal coupled to input ground node GND and a second terminal coupled to power ground node GNDL to mutually protect the two ground rails (GND and GNDL) from electrostatic discharge (ESD). In addition to protecting from discharge, ESD protection circuit 227 also decouples node GND from GNDL to protect node GND from voltage spikes caused by commutation of the power stage. High-side output buffer circuit 224 drives high-side GaN HEMT 24 (e.g., its gate terminal). Low-side output buffer circuit 226 drives low-side GaN HEMT 26 (e.g., its gate terminal).The high-side HEMT 24 is coupled between the high voltage power pad VS and the output pad VOUT, and the low-side HEMT 26 is coupled between the output pad VOUT and the power ground pad GNDL, so that an output drive signal is generated at the output pad VOUT. The voltage regulator REGH (e.g., a low dropout linear regulator) is arranged between the bootstrap line VBOOT and the output line VOUT (e.g., floating ground) and generates a regulated voltage VREGH (e.g., stable and unchanged with respect to temperature and the power supply voltage VBOOT). The trigger FF and the high-side output buffer circuit 224 are supplied between the regulated voltage VREGH and the output voltage VOUT (e.g., floating ground). The voltage regulator REGL (e.g., a low dropout linear regulator) is arranged between the power supply line VCC and the power ground line GNDL and generates a regulated voltage VREGL (e.g., stable and unchanged with respect to temperature and the power supply voltage VCC). The low-side intermediate buffer 225 and the low-side output buffer circuit 226 are supplied between the regulated voltage VREGL and the power supply ground voltage GNDL.

[0064] In one or more embodiments, the driver circuit 20 may be implemented as a fully monolithic GaN (eg, GaN on Si) solution, i.e., all components are implemented in a single GaN (eg, GaN on Si) semiconductor chip. Figure 2 As illustrated, the driver circuit 20 may include a first GaN (e.g., GaN on Si) die 22 in which low-side components (e.g., buffers 220 and 221, regulator REG1, interlock and protection circuit 222, level shifter 223, bootstrap diode BD, regulator REGL, ESD protection circuit 227, intermediate buffer 225, low-side output buffer 226, and low-side power switch 26) are implemented, and a second (e.g., GaN on Si) die 23 in which high-side components (e.g., regulator REGH, flip-flop FF, high-side output buffer 224, and high-side power switch 24) are implemented. Using two separate dies for low-side and high-side components, respectively, facilitates reducing body effects on the high-side power switch 24 and preventing common-mode noise from the substrate on the high-side gate driver during switching of the power stage.

[0065] Figure 3 It is used in Figure 2 Schematic circuit block diagram of a possible implementation of output buffers 224 and 226 in a circuit of .

[0066] Each output buffer 224, 226 includes a pre-buffer section and a push-pull buffer stage. The pre-buffer section contains four pre-buffer circuits, each of which drives an enhancement mode transistor of a push-pull buffer stage, as discussed further below.

[0067] In particular, the output buffer has: an input node 300 configured to receive a corresponding input signal in (e.g., a signal from a flip-flop FF for buffer 224 or a signal from an intermediate buffer 225 for buffer 226); and an output node 302 configured to generate an output gate drive signal gate (e.g., a signal applied to a gate terminal of a power transistor 24 or 26, in Figure 3 denoted generally as transistor QPE).

[0068] The pre-buffer portion includes: a first high-side pre-buffer 31H coupled to the node 300 to receive the signal in, a high-side delay circuit 32H coupled to the output of the pre-buffer 31H and configured to generate a delayed copy of the output signal from the circuit 31H, a high-side AND logic gate 33H coupled to the node 300 and coupled to the delay circuit 32H to apply AND logic processing to the delayed signal from the circuit 32H, and a second high-side pre-buffer 34H coupled to the gate 33H to receive the output signal therefrom. The pre-buffer portion also includes: a high-side delay circuit 32H coupled to the output of the pre-buffer 31H and configured to generate a delayed copy of the output signal from the circuit 31H, and a high-side AND logic gate 33H coupled to the node 300 and coupled to the delay circuit 32H to generate the signal in and the delayed signal from the circuit 32H. in The inverter logic gate 301 is coupled to the gate 301 to receive the signal in A first low-side pre-buffer 31L is coupled to the output of the pre-buffer 31L and is configured to generate a delayed copy of the output signal from the circuit 31L, and a low-side delay circuit 32L is coupled to the output of the inverter 301 and coupled to the delay circuit 32L to delay the signal in A low-side AND logic gate 33L to which the delayed signal from circuit 32L is subjected to AND logic processing, and a second low-side pre-buffer 34L coupled to gate 33L to receive the output signal therefrom. Note that if delay circuit 32H receives signal in instead of the output from circuit 31H, and if delay circuit 32L receives signal in Instead of the output from circuit 31L, the same or similar operation can be obtained. However, Figure 3 The embodiment illustrated in , in which delay circuit 32H is coupled to the output of circuit 31H and delay circuit 32L is coupled to the output of circuit 31L, allows a shorter delay to be introduced by circuits 32H and 32L if the delays of circuits 32H, 32L are added to the delay introduced by circuits 31H and 31L.

[0069] The push-pull buffer stage of each output buffer 224, 226 includes a first switch QE1 (e.g., an enhancement mode GaN transistor) whose current path is arranged between a high power supply node at a voltage V+ (e.g., corresponding to a voltage VREGH or VREGL) and an output node 302, and whose control terminal is coupled to the output of the pre-buffer 31H to be driven thereby. For example, transistor QE1 may have a source terminal coupled to node 302, a drain terminal coupled to the power supply node V+, and a gate terminal coupled to the buffer 31H. Resistor R1 may be coupled in series to transistor QE1, for example, between the drain of transistor QE1 and the power supply node V+. The push-pull buffer stage includes a second switch QE2 (e.g., an enhancement mode GaN transistor) whose current path is arranged between the power supply node V+ and the output node 302, and whose control terminal is coupled to the output of the pre-buffer 34H to be driven thereby. For example, transistor QE2 may have a source terminal coupled to node 302, a drain terminal coupled to power supply node V+, and a gate terminal coupled to buffer 34H. The push-pull buffer stage includes a third switch QE3 (e.g., an enhancement mode GaN transistor) whose current path is arranged between output node 302 and a low power supply node at voltage V- (e.g., corresponding to voltage VOUT or GNDL), and whose control terminal is coupled to the output of pre-buffer 31L to be driven thereby. For example, transistor QE3 may have a drain terminal coupled to node 302, a source terminal coupled to power supply node V- (e.g., via another switch), and a gate terminal coupled to buffer 31L. Another switch QSE (e.g., an enhancement mode GaN transistor) may be coupled in series to transistor QE3, for example, between the source of transistor QE3 and power supply node V-. For example, transistor QSE may have a drain terminal coupled to the source terminal of transistor QE3, a source terminal coupled to power supply node V-, and a gate terminal coupled to output node 302. Thus, the gate terminal of transistor QSE is coupled to the gate terminal of power transistor QPE, and its source terminal is coupled to the source terminal of power transistor QPE, so that transistor QSR reaches the turn-off threshold at the same time as transistor QPE. Resistor R3 may be coupled in parallel to the conduction channel of transistor QSE, for example, coupled between the drain terminal and the source terminal of transistor QSE. The push-pull buffer stage includes a fourth switch QE4 (e.g., an enhancement mode GaN transistor), whose current path is arranged between power supply node V- and output node 302, and whose control terminal is coupled to the output of pre-buffer 34L to be driven thereby. For example, transistor QE4 may have a drain terminal coupled to node 302, a source terminal coupled to power supply node V-, and a gate terminal coupled to buffer 34L.

[0070] Figure 3The architecture illustrated in is envisioned to drive the respective power transistor QPE (i.e., transistor 24 or 26) rail-to-rail in four different time steps or phases. In the on phase, the gate terminal of the power transistor QPE is charged via transistor QE1 with a current limited by resistor R1 to control the switching of transistor QPE with soft edges and reduced electromagnetic emission. After a certain delay time (set by delay circuit 32H), the on state is asserted by transistor QE2, which holds the gate of the power transistor QPE to a high voltage (V+) with a lower impedance. During the off phase, the gate terminal of the power transistor QPE is discharged via transistor QE3 with a peak current in the signal transistor QSE and a controlled current limited by resistor R3. Transistor QSE is configured to quickly discharge the gate of the power transistor QPE to a turn-off threshold voltage value and, if it matches the power transistor, its contribution disappears before such threshold is reached. Therefore, the operation of transistor QSE does not affect the switching edge of the power transistor QPE, which is controlled (only) by resistor R3. After a certain delay time (set by delay circuit 32L), the off state is asserted by transistor QE4, which holds the gate of power transistor QPE to a low voltage (V-) at a relatively low impedance.

[0071] The pre-buffers 31H, 34H and 31L, 34L included in the gate driver are different in whether they drive transistors QE1 and QE2 or QE3 and QE4, but the functionality is similar.

[0072] Figure 4 31L and 34L. The pre-buffer has a circuit configured to receive an input signal v in (For example, the signal in or the output signal from gate 33L, see Figure 3 ) and an output node 404 configured to generate a drive signal for one of the transistors of the push-pull stage (e.g., transistor QE3 or QE4). The conductive channels of the depletion mode transistor QD1 and the enhancement mode transistor QE5 are arranged in series between a high power supply voltage V+ (e.g., VREGH or VREGL) and a low power supply voltage V- (e.g., VOUT or GNDL). For example, transistor QE5 has a source terminal coupled to the voltage V-, a drain terminal coupled to the source terminal of transistor QD1 at node 402, and an output terminal coupled to node 400 to receive a signal v in404. The gate terminal of transistor QD1 is coupled to a voltage V+, and transistor QD2 has a drain terminal coupled to a voltage V+ and a gate terminal coupled to its source terminal at node 402. The conductive channels of depletion mode transistor QD2 and enhancement mode transistor QE6 are arranged in series between a high power supply voltage V+ and a low power supply voltage V-. For example, transistor QE6 has a source terminal coupled to voltage V-, a drain terminal coupled to a first terminal of resistor R2, and a gate terminal coupled to a node 402 (e.g., the drain of QE5 or the source of QD1) intermediate transistors QE5 and QD1, while transistor QD2 has a first (e.g., alternatively, drain or source) terminal coupled to voltage V+, a second (e.g., alternatively, source or drain) terminal coupled to a second terminal of resistor R2, and a gate terminal coupled to the gate terminal of transistor QD1 to receive the same control signal. Bootstrap capacitor CB1 is coupled between the second terminal of transistor QD2 and output node 404. The conduction channel of enhancement transistor QE8 is arranged between the high power supply voltage V+ and the output node 404. For example, transistor QE8 has a drain terminal coupled to the voltage V+, a source terminal coupled to the node 404, and a gate terminal coupled to a node 406 (e.g., the drain of QE6) intermediate transistor QE6 and resistor R2. The conduction channel of enhancement transistor QE7 is arranged between the output node 404 and the low power supply voltage V-. For example, transistor QE7 has a source terminal coupled to the voltage V-, a drain terminal coupled to the node 404, and a gate terminal coupled to the gate terminal of transistor QE6 to receive the same control signal. Optionally, the conduction channel of depletion transistor QD4 is arranged between the high power supply voltage V+ and the output node 404. For example, transistor QD4 has a drain terminal coupled to the voltage V+, a source terminal coupled to the node 404, and a gate terminal coupled to its source terminal (e.g., coupled to the node 404).

[0073] exist Figure 4 In the circuit, when the input signal v at node 400 in When is low, transistors QE5 and QE8 are turned off, while transistors QE6 and QE7 are turned on. Transistor QD1 has a pull-up function, which is complementary to transistor QE5. The bootstrap capacitor CB1 is charged to the voltage V+ via transistor QD2, while resistor R2 prevents capacitor CB1 from discharging via transistor QE6. For better matching, resistor R2 can be replaced by a depletion mode transistor. Under this condition, the output signal v out When the input signal v at node 400 is in When becomes high, transistor QE5 is turned on, while transistors QE6 and QE7 are turned off. Transistor QE8 is boosted by capacitor CB1, and the voltage v at node 404 is outis pulled up to V+. Additionally, transistor QD4 holds output node 404 at a high voltage even when capacitor CB1 is discharging, thereby turning off transistor QE6.

[0074] Figure 5 is an exemplary circuit diagram of a possible implementation of the pre-buffers 31H and 34H, which includes Figure 4 For the sake of brevity, the description of the components shown in FIG. 1 and FIG. 2 will not be repeated. Figure 5 The pre-cache and Figure 4 The difference of the pre-buffer of is that the second terminal of the capacitor CB1, the source terminal of the transistor QE8 and the drain terminal of the transistor QE7 are not connected to the output node 404, but to the intermediate node 501. In addition, Figure 5 The circuit does not include transistor QD4. In addition, Figure 5 The circuit includes a depletion transistor QD3 and a bootstrap capacitor CB2 arranged between a power supply voltage V+ and an intermediate node 501. For example, transistor QD3 has a first (e.g., alternatively, drain or source) terminal coupled to voltage V+, a second (e.g., alternatively, source or drain) terminal coupled to a first terminal of capacitor CB2 at node 502, and a gate terminal coupled to gate terminals of transistors QD1 and QD2 to receive the same control signal, while capacitor CB2 has a second terminal coupled to node 501 (e.g., source of QE8 or drain of QE7). In addition, Figure 5 The circuit includes an enhancement mode transistor QE10 and an enhancement mode transistor QE9, whose conducting channels are arranged in series between a node 502 (e.g., a terminal of a capacitor CB2) and a low power supply voltage V-, and have an output node 404 therebetween. For example, transistor QE10 has a drain terminal coupled to the node 502, a source terminal coupled to the output node 404, and a gate terminal coupled to the gate terminal of transistor QE8 to receive the same control signal, while transistor QE9 has a drain terminal coupled to the node 404, a source terminal coupled to the voltage V-, and a gate terminal coupled to the gate terminals of transistors QE6 and QE7 to receive the same control voltage.

[0075] exist Figure 5 In the circuit, when the input signal v at node 400 in When is low, transistors QE5, QE8, and QE10 are turned off, while transistors QE6, QE7, and QE9 are turned on. Transistor QD1 has a pull-up function, complementary to transistor QE5. Bootstrap capacitors CB1 and CB2 are charged to voltage V+ via transistors QD2 and QD3, respectively, while resistor R2 prevents capacitor CB1 from discharging via transistor QE6. For better matching, resistor R2 can be replaced by a depletion mode transistor. Under this condition, the output signal vout When the input signal v at node 400 is in When becomes high, transistor QE5 is turned on, while transistors QE6, QE7, and QE9 are turned off. Transistors QE8 and QE10 boost the voltage through capacitor CB1, and the charge accumulated on capacitor CB2 is transferred to node 404 through transistor QE10, so that the voltage v at node 404 is out is pulled up to 2·V+.

[0076] Figure 6 It is used in Figure 2 0 is an exemplary circuit block diagram of a possible implementation of buffers 220, 221 and 225 (eg, a high-speed three-stage comparator with hysteresis) in GaN technology in a circuit of FIG.

[0077] Each comparator 220 , 221 , 225 includes an input stage, a differential to single-ended stage, and an output stage.

[0078] In particular, the comparator has: a comparator configured to receive a corresponding input signal v s (For example, the signal VINH for comparator 220, the signal VINL for comparator 221, or the signal output by circuit 222 for comparator 225, see Figure 2 ) is configured to receive a reference voltage v ref The reference node 604 is configured to generate a corresponding output signal v b (For example, the two signals applied to circuit 222 by comparators 220 and 221, or the signal applied to low-side output buffer 226 by comparator 225, see Figure 2 )'s output node 602.

[0079] The input stage of the comparator includes: a differential source coupled pair of (well matched) enhancement mode transistors QE61 and QE62, a tail current generator including a depletion mode transistor QD65 and an optional resistor R65, and a pair of current generator loads including depletion mode transistors QD61, QD62 and optional resistors R61, R62. In particular, the e-mode (enhancement mode) transistor QE61 has a gate terminal coupled to the input node 600 (e.g., the first input node of the differential pair), a source terminal coupled to the node 606 (e.g., the tail node of the differential pair), and a drain terminal coupled to the node 608 (e.g., the first output node of the differential pair). In particular, the enhancement mode transistor QE62 has: a gate terminal coupled to the reference node 604 (e.g., the second input node of the differential pair) (optionally via the resistor R67), a source terminal coupled to the node 606, and a drain terminal coupled to the node 610 (e.g., the second output node of the differential pair). In particular, depletion mode transistor QD61 has a voltage coupled to power supply node VR (eg, regulated voltage VREG for comparators 220 and 221, or regulated voltage VREGL for comparator 225, see Figure 2 ), a source terminal coupled to node 608 (optionally via resistor R61), and a gate terminal coupled to node 608. In particular, depletion mode (d-mode) transistor QD62 has a drain terminal coupled to power supply node VR, a source terminal coupled to node 610 (optionally via resistor R62), and a gate terminal coupled to node 610. In particular, depletion mode transistor QD65 has a drain terminal coupled to node 606, a source terminal coupled to ground node VG (e.g., ground node GND for comparators 220 and 221, or ground node GNDL for comparator 225, see (optionally via resistor R65)). Figure 2 ) and a gate terminal coupled to a ground node VG. The three current generators QD61, QD62, QD65 may be identical. Resistors R61, R62, and R65 are arranged between the source and gate terminals of the respective depletion mode transistors QD61, QD62, and QD65, increasing the output resistance and reducing the current flowing through the differential pair (e.g., through the tail current generator) to a suitable value, e.g., about 20 μA.

[0080] The differential-to-single-ended stage of the comparator includes a current mirror including a pair of enhancement mode transistors QE63, QE64 coupled to nodes 608, 610 (optionally via resistors R63, R64). In particular, enhancement mode transistor QE63 has a drain terminal coupled to node 608 (optionally via resistor R63), a source terminal coupled to ground node VG, and a gate terminal coupled to its drain terminal. In particular, enhancement mode transistor QE64 has a drain terminal coupled to node 610 (optionally via resistor R64), a source terminal coupled to ground node VG, and a gate terminal coupled to the gate terminal of transistor QE63. Thus, the current flowing through transistor QE63 is mirrored (optionally, scaled) by transistor QE64. Current mirrors QE63, QE64 fold and scale down the DC level of the differential signal taken at nodes 608, 610 and produce a single-ended signal at the drain terminal of transistor QE64, referred to as node 612.

[0081] The output stage of the comparator includes a pair of cascaded (identical) inverter circuits. The first inverter circuit receives the single-ended signal from node 612 and generates its complement at node 614, and the second inverter circuit receives the complement signal from node 614 and generates its complement again at output node 602 as output signal v b . In particular, the first inverter circuit includes a depletion mode transistor QD63 and an enhancement mode transistor QE65, whose conductive channels are arranged in series between the power supply node VR and the ground node VG. The enhancement mode transistor QE65 has: a source terminal coupled to the ground node VG, a gate terminal coupled to the node 612, and a drain terminal coupled to the node 614. The depletion mode transistor QD63 has: a source terminal coupled to the node 614, a drain terminal coupled to the power supply node VR, and a gate terminal coupled to its source terminal. In addition, the node 614 between the transistors QE65 and QD63 can be coupled to the gate terminal of the transistor QE62, optionally via a resistor R66, to receive a reference voltage v ref . In particular, the second inverter circuit includes a depletion mode transistor QD64 and an enhancement mode transistor QE66, whose conductive channels are arranged in series between the power supply node VR and the ground node VG. The enhancement mode transistor QE66 has: a source terminal coupled to the ground node VG, a gate terminal coupled to the node 614, and a drain terminal coupled to the output node 602. The depletion mode transistor QD64 has: a source terminal coupled to the node 602, a drain terminal coupled to the power supply node VR, and a gate terminal coupled to its source terminal. The output signal v b A voltage is generated at node 602 between transistors QE66 and QD64. Note that resistors R66 and R67 can be used to connect to a reference voltage vref Positive feedback is used to generate voltage hysteresis.

[0082] Note that although this document has been described in the context of a fully integrated GaN driver circuit 20, as described in reference Figure 6 The discussed embodiments of the comparator implemented in GaN technology are novel in themselves and can be applied to other GaN integrated circuits and can be, independently of their use in Figure 2 The contents included in the gate driver device illustrated in the figure form the subject of one or more embodiments.

[0083] Therefore, one or more embodiments illustrated herein may provide one or more of the following advantages:

[0084] High-speed and low-power gate drivers implemented in monolithic smart power GaN technology that can drive power transistors, both fully integrated on the same substrate;

[0085] The ability to control switch switching edges and reduce electromagnetic emissions;

[0086] The ability to drive the gates of power transistors rail-to-rail; and

[0087] Reduce power consumption during high-speed switching.

[0088] A buffer circuit (224, 226) for driving a gallium nitride (GaN) power switch (QPE), the buffer circuit (224, 226) can be summarized as comprising: an input node (300) configured to receive an input signal (in); an output node (302) configured to generate a gate signal (gate) for the GaN power switch (QPE); a push-pull stage, comprising: a first transistor (QE1) having a conductive channel coupled between a power supply voltage node (V+) and the output node (302); an output node (302); a second transistor (QE2) whose conductive channel is coupled between the power supply voltage node (V+) and the output node (302); a third transistor (QE3) whose conductive channel is coupled between the output node (302) and a reference voltage node (V-); and a fourth transistor (QE4) whose conductive channel is coupled between the output node (302) and the reference voltage node (V-); and a pre-buffer stage configured to receive the input signal (in ) and generates corresponding drive signals for the first transistor (QE1), the second transistor (QE2), the third transistor (QE3) and the fourth transistor (QE4) to generate the gate signal (gate) at the output node (302) in four consecutive stages, wherein: in a first stage, the first transistor (QE1) is turned on, while the second transistor (QE2), the third transistor (QE3) and the fourth transistor (QE4) are not turned on; in a second stage, the first transistor (QE1) and the second transistor (QE2) are turned on, while the third transistor (QE3) and the fourth transistor (QE4) are not turned on; in a third stage, the third transistor (QE3) is turned on, while the first transistor (QE1), the second transistor (QE2) and the fourth transistor (QE4) are not turned on; and in a fourth stage, the third transistor (QE3) and the fourth transistor (QE4) are turned on, while the first transistor (QE1) and the second transistor (QE2) are not turned on.

[0089] The push-pull stage may further include: a first resistor (R1) arranged in series with the conduction channel of the first transistor (QE1); and a fifth transistor (QSE) coupled in parallel to the second resistor (R3), the fifth transistor (QSE) and the second resistor (R3) being arranged in series to the conduction channel of the third transistor (QE3), wherein the fifth transistor (QSE) is controlled by the gate signal (gate).

[0090] The first transistor (QE1), the second transistor (QE2), the third transistor (QE3), the fourth transistor (QE4) and the fifth transistor (QSE) may be enhancement mode GaN transistors.

[0091] The pre-buffer stage may include: a first pre-buffer (31H) configured to drive the first transistor (QE1) according to the input signal (in); a first delay and logic circuit (32H, 33H) configured to generate a copy of the input signal (in), the copy having a rising edge delayed relative to a rising edge of the input signal (in); a second pre-buffer (34H) configured to drive the second transistor (QE2) according to the copy of the input signal (in); a third pre-buffer (31L) configured to generate a second pre-buffer (32H, 33H) according to a complement of the input signal (in); in ) drives the third transistor (QE3); a second delay and logic circuit (32L, 33L) configured to generate a complement ( in ) having a complement ( in ) of the rising edge of the delay rising edge; and a fourth pre-buffer (34L), configured to complement the input signal (in) according to ( in ) drives the fourth transistor (QE4).

[0092] The first pre-buffer (31H) and / or the second pre-buffer (34H) may include: a device configured to receive a corresponding input signal (v in ) and is configured to generate a corresponding drive signal (v out) of the corresponding output node (404); a first depletion-mode transistor (QD1) and a first enhancement-mode transistor (QE5), whose conduction channels are arranged in series between the power supply voltage node (V+) and the reference voltage node (V-), wherein the gate terminal of the first enhancement-mode transistor (QE5) is coupled to the corresponding input node (400); a second depletion-mode transistor (QD2) and a second enhancement-mode transistor (QE6), whose conduction channels are arranged in series between the power supply voltage node (V+) and the reference voltage node (V-), wherein the gate terminal (QD2) of the second depletion-mode transistor (QE6) is coupled to the gate terminal (QD2) of the first enhancement-mode transistor (QE5). a first depletion mode transistor (QD2) connected to a gate terminal of the first depletion mode transistor (QD1) and a gate terminal of the second enhancement mode transistor (QE6) coupled to a node (402) between the first depletion mode transistor (QD1) and the first enhancement mode transistor (QE5); a first bootstrap capacitor (CB1) coupled between a source terminal of the second depletion mode transistor (QD2) and a bootstrap node (501); a third enhancement mode transistor (QE8) having a conductive channel arranged between the power supply voltage node (V+) and the bootstrap node (501) and having a gate terminal coupled to a drain terminal of the second enhancement mode transistor (QE6); a fourth enhancement mode transistor a first depletion-mode transistor (QE7) having a conductive channel arranged between the bootstrap node (501) and the reference voltage node (V-), and having a gate terminal coupled to the gate terminal of the second enhancement transistor (QE6); a third depletion-mode transistor (QD3) and a second bootstrap capacitor (CB1) arranged in series between the power supply voltage node (V+) and the bootstrap node (501), wherein the gate terminal of the third depletion-mode transistor (QD3) is coupled to the gate terminal of the first depletion-mode transistor (QD1), and the first terminal of the second bootstrap transistor (CB2) is coupled to the bootstrap node (501); and a fifth enhancement transistor (QE6) having a conductive channel arranged between the bootstrap node (501) and the reference voltage node (V-), and having a gate terminal coupled to the gate terminal of the second enhancement transistor (QE6); a third depletion-mode transistor (QD3) and a second bootstrap capacitor (CB1) arranged in series between the power supply voltage node (V+) and the bootstrap node (501), wherein the gate terminal of the third depletion-mode transistor (QD3) is coupled to the gate terminal of the first depletion-mode transistor (QD1), and the first terminal of the second bootstrap transistor (CB2) is coupled to the bootstrap node (501); A fifth enhancement mode transistor (QE10) and a sixth enhancement mode transistor (QE9) whose conducting channels are arranged in series between the second terminal (502) of the second bootstrap transistor (CB2) and the reference voltage node (V-), wherein the gate terminal of the fifth enhancement mode transistor (QE10) is coupled to the gate terminal of the third enhancement mode transistor (QE8), and the gate terminal of the sixth enhancement mode transistor (QE9) is coupled to the gate terminal of the fourth enhancement mode transistor (QE7), wherein the corresponding output node (404) is located between the fifth enhancement mode transistor (QE10) and the sixth enhancement mode transistor (QE9).

[0093] The third pre-buffer (31L) and / or the fourth pre-buffer (34L) may include: a pre-buffer configured to receive a corresponding input signal (v in ) of a corresponding input node (400), and is configured to generate a corresponding drive signal (vout ) of the corresponding output node (404); a first depletion-mode transistor (QD1) and a first enhancement-mode transistor (QE5), whose conduction channels are arranged in series between the power supply voltage node (V+) and the reference voltage node (V-), wherein the gate terminal (QE5) of the first enhancement-mode transistor (QE5) is coupled to the corresponding input node (400); a second depletion-mode transistor (QD2) and a second enhancement-mode transistor (QE6), whose conduction channels are arranged in series between the power supply voltage node (V+) and the reference voltage node (V-), wherein the gate terminal of the second depletion-mode transistor (QD2) is coupled to the gate terminal of the first depletion-mode transistor (QD1), and the gate terminal of the second enhancement-mode transistor (QE6) is coupled to the gate terminal of the first depletion-mode transistor (QD1). a bootstrap capacitor (CB1) coupled between the source terminal of the second depletion-mode transistor (QD2) and the corresponding output node (404); a third enhancement-mode transistor (QE8) whose conduction channel is arranged between the power supply voltage node (V+) and the corresponding output node (404), and whose gate terminal is coupled to the drain terminal of the second enhancement-mode transistor (QE6); and a fourth enhancement-mode transistor (QE7) whose conduction channel is arranged between the corresponding output node (404) and the reference voltage node (V-), and whose gate terminal is coupled to the gate terminal of the second enhancement-mode transistor (QE6).

[0094] The third pre-buffer (31L) and / or the fourth pre-buffer (34L) may include a third depletion-mode transistor (QD4) having a conductive channel arranged between the power supply voltage node (V+) and the corresponding output node (404) and having a gate terminal coupled to a source terminal thereof.

[0095] A driver circuit (20) can be summarized as comprising: an input power pad configured to receive a power supply voltage (VCC), an input ground pad configured to receive a ground voltage (GND), an input high-side control pad configured to receive a high-side control signal (VINH), an input low-side control pad configured to receive a low-side control signal (VINL), and an output pad configured to generate an output drive signal (VOUT); a level shifter (223) configured to shift and transfer the high-side control signal (VINH) to a high-side output buffer circuit according to any one of the aforementioned embodiments. (224); a low-side intermediate buffer circuit (225) configured to pass the low-side control signal (VINL) to the low-side output buffer circuit (226) according to any one of the aforementioned embodiments; a high-side GaN power transistor (24) arranged between a high voltage power supply pad (VS) and the output pad (VOUT) and driven by the high-side output buffer circuit (224); and a low-side GaN power transistor (26) arranged between the output pad (VOUT) and a protected ground pad (GNDL) and driven by the low-side output buffer circuit (226).

[0096] The level shifter (223), the high-side output buffer circuit (224), the low-side intermediate buffer circuit (225), the low-side output buffer circuit (226), the high-side GaN power transistor (24) and the low-side GaN power transistor (26) can be implemented in a single GaN semiconductor substrate, preferably in a GaN-on-Si semiconductor substrate.

[0097] The level shifter (223), the low-side intermediate buffer circuit (225), the low-side output buffer circuit (226) and the low-side GaN power transistor (26) can be implemented in a first GaN semiconductor substrate, preferably in a GaN semiconductor substrate on Si; and the high-side output buffer circuit (224) and the high-side GaN power transistor (24) can be implemented in a second GaN semiconductor substrate, preferably in a GaN semiconductor substrate on Si.

[0098] The driver circuit (20) may further include: a first voltage regulator (REGL) configured to generate a first regulated voltage (VREGL) based on the power supply voltage (VCC); a bootstrap circuit system (BD) configured to generate a bootstrap voltage (VBOOT) based on the power supply voltage (VCC); and a second voltage regulator (REGH) configured to generate a second regulated voltage (VREGH) based on the bootstrap voltage (VBOOT), wherein the low-side output buffer circuit (226) can be supplied by the first regulated voltage (VREGL) and the high-side output buffer circuit (224) can be supplied by the second regulated voltage (VREGH).

[0099] The low-side intermediate buffer circuit (225) may include an input stage, a differential to single-ended stage, and an output stage, wherein the input stage may include: an input differential transistor pair (QE61, QE62), a first transistor (QE61) of the pair being configured to receive an input signal (v s ), and the second transistor (QE62) of the pair is configured to receive a reference signal (v ref ); a first current generator load (QD61, R61) coupled between the first transistor (QE61) and a power supply node (VR) of a low-side intermediate buffer circuit (225); a second current generator load (QD62, R62) coupled between the second transistor (QE62) and the power supply node (VR) of the low-side intermediate buffer circuit (225); and a tail current generator (QD65, R65) coupled between a tail node (606) of the input differential transistor pair (QE61, QE62) and a ground node (VG) of the low-side intermediate buffer circuit (225); and wherein The differential to single-ended stage may include a current mirror arrangement (QE63, QE64) coupled to a first output node (608) and a second output node (610) of the input differential transistor pair (QE61, QE62); and wherein the output stage may include a pair of cascaded inverter circuits, a first inverter circuit (QE65, QD63) configured to receive a single-ended signal from the output node of the differential to single-ended stage, and a second inverter circuit (QE66, QD64) configured to receive a complementary signal from the output node of the first inverter circuit to generate an output signal (v b ).

[0100] Without prejudice to the underlying principle, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection.

[0101] The various embodiments described above can be combined to provide other embodiments. All non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If it is necessary to adopt the concepts of various patents, applications and publications to provide other embodiments, the various aspects of the embodiments can be modified.

[0102] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which the claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A buffer circuit for driving a GaN power switch, characterized in that: The buffer circuit comprises: An input node, used for receiving an input signal; an output node for generating a gating signal for a GaN power switch; Push-pull stage, including: a first transistor having a conductive channel coupled between a power supply voltage node and an output node; a second transistor having a conductive channel coupled between the power supply voltage node and the output node; a third transistor having a conductive channel coupled between the output node and a reference voltage node; and a fourth transistor having a conductive channel coupled between the output node and a reference voltage node; and a pre-buffer stage for receiving an input signal and generating respective drive signals for the first transistor, the second transistor, the third transistor and the fourth transistor to generate a gating signal at an output node in four successive phases, wherein: In the first phase, the first transistor is turned on, while the second transistor, the third transistor and the fourth transistor are not turned on; In the second phase, the first transistor and the second transistor are turned on, while the third transistor and the fourth transistor are not turned on; In the third phase, the third transistor is turned on, while the first transistor, the second transistor and the fourth transistor are not turned on; and In the fourth phase, the third transistor and the fourth transistor are turned on, while the first transistor and the second transistor are not turned on.

2. The buffer circuit according to claim 1, wherein: The push-pull stage also includes: a first resistor arranged in series with the conduction channel of the first transistor; a second resistor coupled between the third transistor and the reference voltage; and A fifth transistor is coupled in parallel to the second resistor and is controlled by the gate signal.

3. The buffer circuit according to claim 1, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are enhancement mode GaN transistors.

4. The buffer circuit as claimed in claim 1, wherein: The pre-buffer stages include: A first pre-buffer, configured to drive a first transistor according to an input signal; a first delay and logic circuit for generating a replica of an input signal having a rising edge that is delayed relative to a rising edge of the input signal; a second pre-buffer for driving a second transistor based on a copy of the input signal; a third pre-buffer, for driving a third transistor according to a complement of an input signal; a second delay and logic circuit for generating a copy of the complement of the input signal having a rising edge that is delayed relative to a rising edge of the complement of the input signal; and A fourth pre-buffer is used to drive a fourth transistor according to a complementary copy of the input signal.

5. The buffer circuit as claimed in claim 4, wherein: The first pre-buffer comprises: a corresponding input node for receiving a corresponding input signal and a corresponding output node for generating a corresponding drive signal; a first depletion mode transistor and a first enhancement mode transistor, whose conductive channels are arranged in series between a power supply voltage node and a reference voltage node, wherein a gate terminal of the first enhancement mode transistor is coupled to a respective input node; a second depletion-mode transistor and a second enhancement-mode transistor, whose conducting channels are arranged in series between a power supply voltage node and a reference voltage node, wherein a gate terminal of the second depletion-mode transistor is coupled to a gate terminal of the first depletion-mode transistor, and a gate terminal of the second enhancement-mode transistor is coupled to a node intermediate the first depletion-mode transistor and the first enhancement-mode transistor; a first bootstrap capacitor coupled between a source terminal of the second depletion-mode transistor and a bootstrap node; a third enhancement mode transistor having a conductive channel arranged between the power supply voltage node and the bootstrap node and having a gate terminal coupled to the drain terminal of the second enhancement mode transistor; a fourth enhancement mode transistor having a conductive channel arranged between the bootstrap node and the reference voltage node and having a gate terminal coupled to the gate terminal of the second enhancement mode transistor; a third depletion-mode transistor and a second bootstrap capacitor arranged in series between the supply voltage node and the bootstrap node, wherein a gate terminal of the third depletion-mode transistor is coupled to the gate terminal of the first depletion-mode transistor and a first terminal of the second bootstrap transistor is coupled to the bootstrap node; and A fifth enhancement mode transistor and a sixth enhancement mode transistor, whose conduction channels are arranged in series between the second terminal of the second bootstrap transistor and a reference voltage node, wherein a gate terminal of the fifth enhancement mode transistor is coupled to a gate terminal of the third enhancement mode transistor, and a gate terminal of the sixth enhancement mode transistor is coupled to a gate terminal of the fourth enhancement mode transistor, wherein a corresponding output node is located between the fifth enhancement mode transistor and the sixth enhancement mode transistor.

6. The buffer circuit as claimed in claim 4, wherein: The third pre-buffer comprises: a corresponding input node for receiving a corresponding input signal and a corresponding output node for generating a corresponding drive signal; a first depletion mode transistor and a first enhancement mode transistor, whose conductive channels are arranged in series between a power supply voltage node and a reference voltage node, wherein a gate terminal of the first enhancement mode transistor is coupled to a respective input node; a second depletion-mode transistor and a second enhancement-mode transistor, whose conducting channels are arranged in series between a power supply voltage node and a reference voltage node, wherein a gate terminal of the second depletion-mode transistor is coupled to a gate terminal of the first depletion-mode transistor, and a gate terminal of the second enhancement-mode transistor is coupled to a node intermediate the first depletion-mode transistor and the first enhancement-mode transistor; a bootstrap capacitor coupled between a source terminal of the second depletion-mode transistor and the corresponding output node; a third enhancement mode transistor having a conductive channel arranged between the power supply voltage node and the corresponding output node and having a gate terminal coupled to the drain terminal of the second enhancement mode transistor; and A fourth enhancement mode transistor has a conductive channel arranged between the corresponding output node and the reference voltage node and a gate terminal coupled to the gate terminal of the second enhancement mode transistor.

7. The buffer circuit as claimed in claim 6, wherein: The third pre-buffer includes a third depletion-mode transistor, a conduction channel of the third depletion-mode transistor is arranged between the power supply voltage node and the corresponding output node, and a gate terminal thereof is coupled to a source terminal thereof.

8. A driver circuit, characterized in that: include: An input power pad for receiving a power supply voltage, an input ground pad for receiving a ground voltage, an input high-side control pad for receiving a high-side control signal, an input low-side control pad for receiving a low-side control signal, and an output pad for generating an output drive signal; High-side output buffer circuit; Low-side output buffer circuit; a level shifter for shifting and transferring the high-side control signal to the high-side output buffer circuit; a low-side intermediate buffer circuit for transmitting the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor disposed between the high voltage power pad and the output pad and driven by the high-side output buffer circuit; and The low-side GaN power transistor is placed between the output pad and the protected ground pad and driven by the low-side output buffer circuit.

9. The driver circuit according to claim 8, characterized in that The level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.

10. The driver circuit according to claim 9, characterized in that The GaN semiconductor substrate is a GaN semiconductor substrate on Si.

11. The driver circuit according to claim 8, wherein: in: The level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit, and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and A high-side output buffer circuit and a high-side GaN power transistor are implemented in the second GaN semiconductor substrate.

12. The driver circuit according to claim 11, wherein: The first GaN semiconductor substrate and the second GaN semiconductor substrate are GaN semiconductor substrates.

13. The driver circuit according to claim 8, wherein: Also includes: a first voltage regulator for generating a first regulated voltage based on a power supply voltage; A bootstrap circuit system, used for generating a bootstrap voltage according to a power supply voltage; as well as A second voltage regulator is configured to generate a second regulated voltage based on the bootstrap voltage, wherein the low-side output buffer circuit is supplied with the first regulated voltage and the high-side output buffer circuit is supplied with the second regulated voltage.

14. The driver circuit according to claim 8, characterized in that The low-side intermediate buffer circuit includes an input stage, a differential to single-ended stage, and an output stage, wherein the input stage includes: an input differential transistor pair, a first transistor of the pair for receiving an input signal at a control terminal thereof, and a second transistor of the pair for receiving a reference signal at a control terminal thereof; a first current generator load coupled between the first transistor and a power supply node of the low-side intermediate buffer circuit; a second current generator load coupled between the second transistor and a power supply node of the low-side intermediate buffer circuit; and a tail current generator coupled between a tail node of the input differential transistor pair and a ground node of the low-side intermediate buffer circuit; and wherein the differential-to-single-ended stage comprises a current mirror arrangement coupled to a first output node and a second output node of the input differential transistor pair; And wherein the output stage includes a pair of cascaded inverter circuits, the first inverter circuit is used to receive the single-ended signal from the output node of the differential to single-ended stage, and the second inverter circuit is used to receive the complementary signal from the output node of the first inverter circuit to generate the output signal of the low-side intermediate buffer circuit.

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