Semiconductor structure

Abstract

Some embodiments of the present disclosure describe a semiconductor structure having an isolation layer surrounding a sloped portion of a channel structure. The semiconductor structure includes a channel structure having a first portion, a second portion, and a third portion on a substrate. The first portion has a first width. The second portion has a second width less than the first width. The third portion has a third width less than the second width. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion, a second isolation layer on the first isolation layer and surrounding a second portion of the channel structure, and a gate structure on the second isolation layer and surrounding a third portion of the channel structure.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor structure. Background Art

[0002] As semiconductor technology advances, there has been an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as MOSFETs including planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). This scaling down has increased the complexity of semiconductor manufacturing processes and increased difficulty in process control in semiconductor devices. Utility Model Content

[0003] According to some embodiments of the present disclosure, a semiconductor structure includes a channel structure on a substrate, the channel structure having a first portion, a second portion, and a third portion. The first portion has a first width. The second portion has a second width that is smaller than the first width. The third portion has a third width that is smaller than the second width. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion of the channel structure, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure.

[0004] According to some embodiments of the present disclosure, a semiconductor structure includes a first channel structure and a second channel structure on a substrate. Each of the first channel structure and the second channel structure includes an inclined first portion, an inclined second portion, and a vertical third portion. The semiconductor structure further includes a first isolation layer on the substrate and between the first channel structure and the second channel structure, a second isolation layer on the first isolation layer and between the first channel structure and the second channel structure, and a gate structure on the second isolation layer and surrounding the vertical third portion of the first channel structure and the vertical third portion of the second channel structure. The inclined second portion of the first channel structure and the inclined second portion of the second channel structure are within the second isolation layer.

[0005] According to some embodiments of the present disclosure, a semiconductor structure includes a channel structure on a substrate, the channel structure including a first portion, a second portion, and a third portion. The first portion has a first width, the second portion has a second width less than the first width, and the third portion has a third width less than the second width. The ratio between the height of the second portion of the channel structure and the height of the third portion of the channel structure ranges from 20% to 60%. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion of the channel structure, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some aspects of the present disclosure are described in the accompanying Figure 1 It is best understood from the following detailed description when read together.

[0007] Figure 1 illustrates an isometric view of a semiconductor component having an isolation layer surrounding an inclined portion of a channel structure according to some embodiments;

[0008] Figure 2 and Figure 3 illustrates a cross-sectional view of a semiconductor component having an isolation layer surrounding an inclined portion of a channel structure according to some embodiments;

[0009] Figure 4 is a flow chart of a method for forming an isolation layer surrounding an inclined portion of a channel structure according to some embodiments;

[0010] Figures 5 to 12 illustrates isometric and cross-sectional views of a semiconductor device having an isolation layer surrounding an inclined portion of a channel structure at various stages of fabrication according to some embodiments;

[0011] Illustrative embodiments will now be described with reference to the accompanying drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0012]

Explanation of symbols

[0013] 100:Semiconductor components

[0014] 102A~102C: Transistor

[0015] 104:Substrate

[0016] 106: first isolation layer

[0017] 106t:Thickness

[0018] 108: Fin structure

[0019] 108-1: Part 1

[0020] 108-2: Part 2

[0021] 108-3: Part 3

[0022] 108h:Height

[0023] 109: Fin sidewall spacer

[0024] 110:S / D structure

[0025] 112: Gate structure

[0026] 112*: Gate structure

[0027] 112h: Height

[0028] 112w: Width

[0029] 114: Gate spacer

[0030] 116: Etch stop layer (ESL)

[0031] 118: Interlayer dielectric (ILD) layer

[0032] 120: Second isolation layer

[0033] 120t:Thickness

[0034] 124: Gate dielectric layer

[0035] 400:Method

[0036] 410: Operation

[0037] 420: Operation

[0038] 430: Operation

[0039] 440: Operation

[0040] 450: Operation

[0041] 1130: Hard mask layer

[0042] H1: Height

[0043] H2: Height

[0044] H3: Height

[0045] W1: Width

[0046] W2: Width

[0047] W3: Width

[0048] X: Axis

[0049] Y: Axis

[0050] Z: Axis DETAILED DESCRIPTION

[0051] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify some embodiments of the present disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used in some embodiments of the present disclosure, the formation of a first feature on a second feature means that the first feature is formed in direct contact with the second feature. In addition, some embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0052] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used in some embodiments of the present disclosure for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure may likewise be interpreted accordingly.

[0053] It should be noted that references in the specification to "one embodiment", "an embodiment", "an example embodiment", "exemplary", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the particular feature, structure, or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, a person skilled in the art will recognize that such feature, structure, or characteristic may be implemented in conjunction with other embodiments regardless of whether it is explicitly described.

[0054] It should be understood that the phrases or terms in some embodiments of the present disclosure are for description and non-limiting purposes, so that the phrases or phrases in some embodiments of the present disclosure should be interpreted by those skilled in the art according to the teachings in some embodiments of the present disclosure.

[0055] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one skilled in the art according to the teachings in some embodiments of the present disclosure.

[0056] As the demand for lower power consumption, higher performance, and smaller semiconductor devices increases, the size of semiconductor devices continues to scale down. The continued scaling down of device size and the increased demand for device performance may require various process and material improvements, which may have various challenges. For example, the fin structure of the semiconductor device may have an inclined sidewall. In order to improve gate control in the fin structure and reduce leakage current, the bottom portion of the gate structure of the semiconductor device may have a larger width, which may be referred to as "gate footing". However, during the subsequent process of source / drain (S / D) epitaxial structure formation, the bottom portion of the gate structure may be etched through. As a result, metal gate extrusion defects and S / D epitaxial pit defects may increase.

[0057] Various embodiments disclosed herein provide example methods for forming an isolation layer surrounding an inclined portion of a channel structure in a semiconductor device (e.g., a nanostructure transistor) and / or other semiconductor devices in an integrated circuit. In some embodiments, a channel structure may be formed on a substrate, and a first isolation layer may be formed on the substrate and surround the first portion of the channel structure. The channel structure may have an inclined sidewall surface. The channel structure above the first isolation layer may be trimmed to form a second portion having an inclined sidewall surface and a third portion having a substantially vertical sidewall surface. A second isolation layer may be formed on the first isolation layer to surround the second portion of the channel structure so as to cover the inclined sidewall surface. A gate structure may be formed on the second isolation layer and surround the substantially vertical third portion of the channel structure. Thus, the gate structure may have a substantially vertical sidewall surface without a gate leg for improved gate control and reduced leakage current. The substantially vertical sidewall surface of the gate structure may reduce metal gate extrusion defects and S / D epitaxial pit defects in subsequent manufacturing processes.

[0058] Figure 1 An isometric view of a semiconductor component 100 is shown having an isolation layer surrounding an inclined portion of a channel structure, according to some embodiments. Figure 2 The semiconductor device 100 according to some embodiments is shown in FIG. Figure 1 A partial cross-sectional view taken along line AA in FIG. Figure 3 The semiconductor device 100 according to some embodiments is shown in FIG. Figure 1In some embodiments, the semiconductor device 100 may include transistors 102A to 102C, such as Figure 1 . In some embodiments, transistors 102A to 102C may be nanostructure transistors. Nanostructure transistors may include finFETs, gate-all-around field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other similar structured transistors. Nanostructure transistors may provide channels in fin structures or stacked nanosheets / nanowires.

[0059] In some embodiments, transistors 102A to 102C may be n-type field-effect transistors (NFETs). In some embodiments, transistors 102A to 102C may be p-type field-effect transistors (PFETs). In some embodiments, any of transistors 102A to 102C may be an NFET or a PFET. Figure 1 Three transistors are shown, but semiconductor device 100 may have any number of transistors. In addition, semiconductor device 100 may be incorporated into an IC by using other structural components, such as conductive vias, conductive wires, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity. Discussion of components with the same labeled transistors 102A-102C applies to each other unless otherwise mentioned. And similar reference numbers generally indicate identical, functionally similar, and / or structurally similar components.

[0060] See also Figures 1 to 3 , a semiconductor device 100 having transistors 102A to 102C may be formed on a substrate 104 and may be isolated by a first isolation layer 106 and a second isolation layer 120. Each of the transistors 102A to 102C may include a fin structure 108, a fin sidewall spacer 109, a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an S / D structure 110, an etch stop layer (ESL) 116, and an interlayer dielectric (ILD) layer 118. In some embodiments, the fin structure 108 below the gate structure 112 may extend above the second isolation layer 120.

[0061] See also Figure 1, the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. In addition, the substrate 104 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped by a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0062] See also Figure 1 and Figure 2 , the fin structure 108 may be formed on the patterned portion of the substrate 104. The embodiments of the fin structure disclosed in some embodiments of the present disclosure may be patterned by any suitable method. For example, the fin structure may be patterned using one or more optical lithography processes including a double patterning or multiple patterning process. The double patterning or multiple patterning process may combine an optical lithography process with a self-alignment process to form patterns having, for example, a smaller spacing than would otherwise be obtainable using a single direct optical lithography process. For example, a sacrificial layer is formed over the substrate using an optical lithography process and patterned. Spacers may be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure.

[0063] like Figure 1 and Figure 2 As shown in , the fin structure 108 may extend along the X-axis and extend through the transistors 102A to 102C. In some embodiments, the fin structure 108 may be disposed on the substrate 104. The fin structure 108 may act as a channel structure and form a channel region of the gate structure 112 underlying the transistors 102A to 102C. In some embodiments, the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the fin structure 108 may include silicon for the n-type transistors 102A to 102C. In some embodiments, the fin structure 108 may include silicon germanium for the p-type transistors 102A to 102C. The semiconductor material of the fin structure 108 may be undoped or may be doped in situ during its formation process. In some embodiments, the fin structure 108 below the gate structure 112 may form a channel region of the semiconductor device 100 and represent a current carrying channel structure of the semiconductor device 100.

[0064] In some embodiments, Figure 2As shown in FIG. 1 , the fin structure 108 may include a first portion 108-1, a second portion 108-2, and a third portion 108-3. The first portion 108-1 may be surrounded by and within the first isolation layer 106. The second portion 108-2 may be surrounded by and within the second isolation layer 120. The third portion 108-3 may be surrounded by the gate structure 112. In some embodiments, the first portion 108-1 may have a height H1 ranging from about 40 nm to about 60 nm along the Z axis and a width W1 ranging from about 9 nm to about 15 nm along the Y axis. In some embodiments, the first portion 108-1 may be an inclined portion and may have an inclined sidewall surface, such as Figure 2 The width W1 of the first portion 108 - 1 adjacent to its bottom surface may be greater than the width W1 of the first portion 108 - 1 adjacent to its top surface.

[0065] In some embodiments, the second portion 108-2 may have a height H2 ranging from about 10 nm to about 20 nm along the Z axis and a width W2 ranging from about 6 nm to about 8 nm along the Y axis. In some embodiments, the second portion 108-2 may be an inclined portion and may have an inclined sidewall surface, such as Figure 2 . The width W2 of the second portion 108-2 adjacent to its bottom surface may be greater than the width W2 of the second portion 108-2 adjacent to its top surface. In some embodiments, the width W2 may be less than the width W1. In some embodiments, the second portion 108-2 may be referred to as a “fin leg” of the fin structure 108.

[0066] In some embodiments, the third portion 108-3 may have a height H3 ranging from about 35 nm to about 45 nm along the Z axis and a width W3 ranging from about 4 nm to about 6 nm along the Y axis. In some embodiments, the third portion 108-3 may have a substantially vertical sidewall surface, such as Figure 2 . The width W3 of the third portion 108-3 adjacent to its bottom surface may be substantially the same as the width W3 of the third portion 108-3 adjacent to its top surface. In some embodiments, the width W3 may be less than the width W2. In some embodiments, the substantially vertical sidewall surface of the third portion 108-3 may improve gate control and reduce leakage current of the fin structure 108.

[0067] In some embodiments, the ratio between width W3 and width W2 may range from about 50% to about 90%. If the ratio is less than about 50% or width W3 is less than about 4 nm, fin defects such as broken fins may increase. If the ratio is greater than about 90%, or width W3 is greater than about 6 nm, the third portion 108-3 may not have a substantially vertical sidewall surface. Therefore, gate control of the current flowing through the fin structure 108 may be reduced, and the leakage current of the semiconductor device 100 may increase.

[0068] In some embodiments, the ratio between the height H2 and the height H3 may range from about 20% to about 60%. If the ratio is less than about 20% or the height H2 is less than about 10 nm, fin defects such as broken fins may increase. If the ratio is greater than about 60%, or the height H2 is greater than about 20 nm, the third portion 108-3 may not have a substantially vertical sidewall surface. Therefore, gate control of the current flowing through the fin structure 108 may be reduced, and the leakage current of the semiconductor device 100 may increase.

[0069] The first isolation layer 106 and the second isolation layer 120 may provide electrical isolation between the transistors 102A to 102C and from adjacent transistors (not shown) on the substrate 104 and / or adjacent active and passive components (not shown) integrated with or deposited on the substrate 104. In some embodiments, the first isolation layer 106 and the second isolation layer 120 may include the same dielectric material. In some embodiments, the first isolation layer 106 and the second isolation layer 120 may include different dielectric materials. In some embodiments, the first isolation layer 106 and the second isolation layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the second isolation layer 120 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, the flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may be deposited by CVD, atomic layer deposition (ALD), or other suitable deposition processes.

[0070] In some embodiments, the first isolation layer 106 may be disposed on the substrate 104 so as to surround the first portion 108-1 of the fin structure 108. In some embodiments, the first isolation layer 106 may have a thickness 106t ranging from about 40 nm to about 60 nm along the Z axis. In some embodiments, the second isolation layer 120 may be disposed on the first isolation layer 106 so as to surround the second portion 108-2 of the fin structure 108. In some embodiments, the second isolation layer 120 may have a thickness 120t ranging from about 10 nm to about 20 nm. In some embodiments, the thickness 120t may be equal to or greater than the height H2 to fully cover the fin leg of the fin structure 108, i.e., the second portion 108-2. In some embodiments, the top surface of the second isolation layer 120 may be above the second portion 108-2 of the fin structure 108 to fully cover the second portion 108-2. In some embodiments, the ratio of the thickness 120t to the sum of the heights (height H2 and height H3) may range from about 15% to about 40%. If the ratio is less than about 15% or the thickness 120t is less than about 10 nm, the second isolation layer 120 may not cover the fin legs of the fin structure 108, gate control of current through the fin structure 108 may be reduced, and leakage current of the semiconductor device 100 may increase. If the ratio is greater than about 40% or the thickness 120t is greater than about 20 nm, the portion of the fin surrounded by the gate structure 112 may be reduced, and the channel current may be reduced.

[0071] See also Figure 2 , the gate dielectric layer 124 may be disposed on the fin structure 108 and the second isolation layer 120. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. The term "high-k" may refer to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k may refer to a dielectric constant greater than the dielectric constant of silicon oxide (for example, greater than about 3.9). In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the gate dielectric layer 124 may have a thickness ranging from about 1 nm to about 5 nm.

[0072] In some embodiments, Figures 1 to 3As shown in , the gate structure 112 may be disposed on the gate dielectric layer 124 above the fin structure 108 and the second isolation layer 120. In some embodiments, the gate structure 112 may surround the third portion 108-3 of the fin structure 108 and may have a substantially vertical sidewall surface without a gate leg. Because of the substantially vertical sidewall surface of the third portion 108-3 of the fin structure 108, the gate structure 112 having a substantially vertical sidewall surface and no gate leg may have improved gate control and reduced leakage current. In addition, the substantially vertical sidewall surface of the gate structure 112 may reduce metal gate extrusion defects and S / D epitaxial pit defects in subsequent manufacturing processes. In some embodiments, the gate structure 112 may have a height 112h ranging from about 100nm to about 150nm along the Z axis. In some embodiments, the gate structure 112 may have a width 112w ranging from about 15nm to about 20nm along the X axis. In some embodiments, the width 112 w of the gate structure 112 adjacent to the top and bottom surfaces may be substantially the same due to the substantially vertical side surfaces of the gate structure 112 .

[0073] In some embodiments, the gate structure 112 may include one or more work function metal layers and metal fillers. The one or more work function metal layers may include work function metals to tune the threshold voltage (V t ). In some embodiments, transistors 102A to 102C (e.g., NFETs) may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, tantalum carbon silicide, hafnium carbide, silicon, titanium nitride, titanium nitride silicide, or other suitable work function metals. In some embodiments, transistors 102A to 102C (e.g., PFETs) may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium nitride silicide, tantalum nitride, tungsten nitride carbide, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a metal layer stack. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0074] See also Figure 1 and Figure 3, the gate spacer 114 may be disposed on the sidewalls of the gate structure 112, and the fin sidewall spacer 109 may be disposed on the sidewalls of the fin structure 108. The gate spacer 114 and the fin sidewall spacer 109 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k materials, and combinations thereof. The gate spacer 114 and the fin sidewall spacer 109 may include a single layer or a stack of insulating layers. The gate spacer 114 and the fin sidewall spacer 109 may have a low-k material with a dielectric constant that is less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8).

[0075] The S / D structure 110 may be disposed on the fin structure 108 and on the opposite side of the gate structure 112. The S / D structure 110 may serve as an S / D region for the transistors 102A to 102C. In some embodiments, the S / D structure 110 may be disposed on the second portion 108-2 of the fin structure 108. In some embodiments, the S / D structure 110 may be disposed above the second isolation layer 120. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the epitaxially grown semiconductor material may include an epitaxially grown semiconductor material different from the material of the substrate 104, such as silicon germanium, and impart strain to the channel region below the gate structure 112. Since the lattice constant of such epitaxially grown semiconductor material is different from the lattice constant of the material of the substrate 104, the channel region is strained to increase carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and gallium aluminum arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenic phosphide.

[0076] In some embodiments, the S / D structure 110 may include silicon and be in-situ doped with n-type dopants such as phosphorus and arsenic during the epitaxial growth process. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or a III-V material (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped with p-type dopants such as boron, indium, and gallium during the epitaxial growth process. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition.

[0077] The ESL 116 may be disposed on the second isolation layer 120, the S / D structure 110, the sidewalls of the gate spacer 114, and the fin sidewall spacer 109. The ESL 116 may be used to protect the second isolation layer 120, the S / D structure 110, and the gate structure 112 during the formation of the S / D contact structure on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination thereof.

[0078] The ILD layer 118 may be disposed on the ESL 116 over the S / D structure 110 and the second isolation layer 120. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for flowing dielectric materials. For example, flowing silicon oxide may be deposited using FCVD. In some embodiments, the dielectric material may include silicon oxide.

[0079] Figure 4 Flowchart of method 400 for manufacturing semiconductor device 100 having an isolation layer surrounding an inclined portion of a channel structure according to some embodiments. Method 400 may not be limited to nanostructure transistor devices and may be applicable to other devices that would benefit from an isolation layer surrounding an inclined portion of a channel structure. Additional manufacturing operations may be performed between various operations of method 400 and are omitted only for clarity and ease of description. Additional processes may be provided before, during and / or after method 400; one or more of these additional processes are briefly described in some embodiments of the present disclosure. In addition, not all operations may be required to perform the disclosure provided in some embodiments of the present disclosure. In addition, some of the operations may be performed simultaneously or in different steps. Figure 4 In some embodiments, one or more other operations may be performed in addition to or in place of the operations previously described.

[0080] For illustrative purposes, the Figure 4 The operations in will refer to Figures 5 to 12 An example manufacturing process for manufacturing semiconductor element 100 is described as illustrated in FIG. Figures 5 to 12 1 and 2 illustrate isometric views and partial cross-sectional views of a semiconductor device 100 having an isolation layer surrounding an inclined portion of a channel structure at various stages of manufacture according to some embodiments. Figures 1 to 3 The same markings as the components in Figures 5 to 12 Components in .

[0081] See also Figure 4 , method 400 begins with operation 410 and a process of forming a channel structure on a substrate. For example, Figure 5 and Figure 6As shown in FIG. 1 , the fin structure 108 may be formed on the substrate 104 and may serve as a channel structure in the semiconductor device 100 . Figure 6 The semiconductor device 100 according to some embodiments is shown along the Figure 5 1. In some embodiments, the fin structure 108 may include silicon. In some embodiments, the fin structure 108 may include silicon germanium. The semiconductor material of the fin structure 108 may be undoped or may be in-situ doped during its formation process. In some embodiments, the fin structure 108 may have an inclined sidewall surface, such as Figure 5 and Figure 6 . In some embodiments, the fin structure 108 may have a height 108h ranging from about 80 nm to about 150 nm along the Z axis. In some embodiments, after the fin structure 108 is formed, a protection layer (not shown) may be formed on the fin structure 108. The protection layer may protect the fin structure 108 during the etching process in subsequent operations (e.g., forming the first isolation layer 106 and forming the gate structure 112).

[0082] See also Figure 4 In operation 420, a first isolation layer is formed on the substrate and surrounding the first portion of the channel structure. Figure 5 and Figure 6 As shown in FIG. 1 , the first isolation layer 106 may be formed on the substrate 104 and surround the first portion 108-1 of the fin structure 108. The formation of the first isolation layer 106 may include depositing an insulating material layer on the substrate 104, annealing the insulating material layer, performing chemical mechanical polishing (CMP) on the annealed insulating material layer, and etching back the polished structure to form Figure 5 and Figure 6 The structure in .

[0083] In some embodiments, the insulating material layer may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. In some embodiments, the insulating material layer may be deposited using a CVD process, a high-density-plasma (HDP) CVD process, a sub-atmospheric CVD (SACVD) process, a high aspect-ratio process (HARP), or other suitable deposition process. In some embodiments, the insulating material layer may be formed by depositing flowing silicon oxide using a FCVD process. The FCVD process may be followed by a wet annealing process. The wet annealing process may be followed by a CMP process to make the top surface of the insulating material layer substantially coplanar with the top surface of the fin structure 108. The CMP process may be followed by a dry etching process, a wet etching process, or a combination of the two to etch back the insulating material layer to form Figure 5 and Figure 6 In some embodiments, the fin structure 108 may extend above the first isolation layer 106 after etching back the insulating material layer.

[0084] See also Figure 4 In operation 430, the channel structure above the first isolation layer is trimmed. For example, Figure 7 and Figure 8 As shown in FIG. 1 , the fin structure 108 above the first isolation layer 106 may be trimmed to form a second portion 108 - 2 having an inclined sidewall surface and a third portion 108 - 3 having a substantially vertical sidewall surface. Figure 8 The semiconductor device 100 according to some embodiments is shown along the Figure 7 DD in FIG. 1 . In some embodiments, the fin structure 108 may be trimmed by a dry etching process, a plasma etching process, or a combination thereof. In some embodiments, the trimming process may be directional to etch the inclined sidewall surface and form a substantially vertical sidewall surface. In some embodiments, the trimming process may include an etchant having an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, other suitable etching gases, and / or plasma, or a combination thereof.

[0085] In some embodiments, after the trimming process, the fin structure 108 may include a first portion 108 - 1 , a second portion 108 - 2 , and a third portion 108 - 3 . Figure 8. The second portion 108-2 may be an inclined portion and may have an inclined sidewall surface. The second portion 108-2 may have a height H2 in the range of about 10nm to about 20nm along the Z axis and a width W2 in the range of about 6nm to about 8nm along the Y axis. The width W2 of the second portion 108-2 adjacent to its bottom surface may be greater than the width W2 of the second portion 108-2 adjacent to its top surface. In some embodiments, the width W2 may be less than the width W1. The third portion 108-3 may be a vertical portion and may have a substantially vertical sidewall surface. The third portion 108-3 may have a height H3 in the range of about 35nm to about 45nm along the Z axis and a width W3 in the range of about 4nm to about 6nm along the Y axis. In some embodiments, the width W3 may be less than the width W2.

[0086] In some embodiments, the ratio between width W3 and width W2 may range from about 50% to about 90%. If the ratio is less than about 50% or width W3 is less than about 4 nm, fin defects such as broken fins may increase. If the ratio is greater than about 90%, or width W3 is greater than about 6 nm, the third portion 108-3 may not have a substantially vertical sidewall surface. Therefore, gate control of the current flowing through the fin structure 108 may be reduced, and the leakage current of the semiconductor device 100 may increase.

[0087] In some embodiments, the ratio between the height H2 and the height H3 may range from about 20% to about 60%. If the ratio is less than about 20% or the height H2 is less than about 10 nm, fin defects such as broken fins may increase. If the ratio is greater than about 60%, or the height H2 is greater than about 20 nm, the third portion 108-3 may not have a substantially vertical sidewall surface. Therefore, gate control of the current flowing through the fin structure 108 may be reduced, and the leakage current of the semiconductor device 100 may increase.

[0088] See also Figure 4 In operation 440, a second isolation layer is formed on the first isolation layer and surrounding the first portion of the channel structure. Fig. 9 and Fig.10 As shown in FIG. 1 , the second isolation layer 120 may be formed on the first isolation layer 106 and surround the second portion 108 - 2 of the fin structure 108 . Fig.10 The semiconductor device 100 according to some embodiments is shown along the Fig.10EE in FIG. 1 . In some embodiments, the second isolation layer 120 may include a dielectric material deposited using a deposition method suitable for a flowing dielectric material. For example, flowing silicon oxide may be deposited using FCVD. In some embodiments, the dielectric material may be deposited by CVD, ALD, and other suitable deposition processes. In some embodiments, the second isolation layer 120 may include silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and combinations thereof deposited by an FCVD process.

[0089] In some embodiments, the FCVD process may include depositing a flowing dielectric material, a curing process, and an annealing process. In some embodiments, the flowing dielectric material may be deposited on the surface of the semiconductor element 100 to fill the space between the fin structures 108. In some embodiments, the curing process may include an ozone pre-soaking process and an ultraviolet (UV) curing process. During the ozone pre-soaking process, the flowing dielectric material may be treated in an ozone environment to form an oxide-like shell layer on the surface of the flowing dielectric material. During the UV curing process, the flowing dielectric material may be treated in a UV light environment to exhaust gas and harden the flowing dielectric material. In some embodiments, the annealing process may include a wet annealing process, a dry annealing process, or a combination thereof. The annealing process may include annealing the cured flowing dielectric material at a temperature in the range of about 200°C to about 700°C for a period of time ranging from about 30 minutes to about 120 minutes.

[0090] In some embodiments, the FCVD process may be followed by a CMP process to make the top surface of the annealed flowing dielectric material layer substantially coplanar with the top surface of the fin structure 108. The CMP process may be followed by a dry etching process, a wet etching process, or a combination of the two to etch back the flowing dielectric material to form the second isolation layer 120, such as Fig. 9 and Fig.10 shown in.

[0091] In some embodiments, the second isolation layer 120 may have a thickness 120t ranging from about 10 nm to about 20 nm. In some embodiments, the thickness 120t may be equal to or greater than the height H2 to fully cover the fin legs of the fin structure 108, i.e., the second portion 108-2. In some embodiments, the top surface of the second isolation layer 120 may be above the second portion 108-2 of the fin structure 108. In some embodiments, the ratio of the thickness 120t to the sum of the heights (height H2 and height H3) may range from about 15% to about 40%. If the ratio is less than about 15% or the thickness 120t is less than about 10 nm, the second isolation layer 120 may not cover the fin legs of the fin structure 108, the gate control of the current through the fin structure 108 may be reduced, and the leakage current of the semiconductor device 100 may increase. If the ratio is greater than about 20% or the thickness 120t is greater than about 20 nm, the gate structure (e.g. Figures 1 to 3 The fin portion surrounded by the gate structure 112) can be reduced, and the channel current can be reduced.

[0092] See also Figure 4 In operation 450, a gate structure is formed on the second isolation layer and surrounding a third portion of the channel structure. Fig.11 and Fig.12 As shown in FIG. 1 , the gate structure 112 * may be formed on the second isolation layer 120 and surround the third portion 108 - 3 of the fin structure 108 . Fig.12 The semiconductor device 100 according to some embodiments is shown along the Fig.11 In some embodiments, the gate structure 112* may include polysilicon and may be replaced in a subsequent gate replacement process to form the gate structure 112 of the transistors 102A to 102C, such as Figures 1 to 3 shown in.

[0093] In some embodiments, the formation of the gate structure 112* may include blanket depositing a layer of polycrystalline material on the fin structure 108 and the second isolation layer 120, and etching the polycrystalline silicon material layer through a patterned hard mask layer 1130 formed on the layer of polycrystalline silicon material. The blanket deposition of the polycrystalline material layer may include CVD, physical vapor deposition (PVD), or other suitable deposition processes. In some embodiments, the polycrystalline silicon material may be undoped, and the hard mask layer 1130 may include an oxide layer and / or a nitride layer. The hard mask layer 1130 protects the gate structure 112* during subsequent processing operations (e.g., forming the gate spacer 114, the S / D structure 110, and / or the ILD layer 118).

[0094] In some embodiments, etching the deposited layer of polysilicon material may include dry etching, wet etching, or a combination thereof. In some embodiments, etching the deposited layer of polysilicon material may include multiple etching steps. After the etching step, the gate structure 112* may be formed around the third portion 108-3 of the fin structure 108, and may have a substantially vertical sidewall surface without a gate leg. Because of the substantially vertical sidewall surface of the third portion 108-3 of the fin structure 108, the gate structure 112* having a substantially vertical sidewall surface and no gate leg may have improved gate control and reduced leakage current. In addition, the substantially vertical sidewall surface of the gate structure 112* may reduce metal gate extrusion defects and S / D epitaxial pit defects in subsequent manufacturing processes. In some embodiments, the gate structure 112* may have a height ranging from about 100nm to about 150nm along the Z axis. In some embodiments, the gate structure 112* may have a width ranging from about 15nm to about 20nm along the X axis. In some embodiments, the width of the gate structure 112 * adjacent to the top surface and the bottom surface may be substantially the same due to the substantially vertical side surfaces of the gate structure 112 *.

[0095] The formation of the gate structure 112* may be followed by forming a gate spacer 114 on the sidewall surfaces of the gate structure 112* and on the top surface of the second isolation layer 120, forming the S / D structure 110 on the second portion 108-2 of the fin structure 108 and above the second isolation layer 120, removing the gate structure 112*, forming a gate dielectric layer 124 on the fin structure 108 and the second isolation layer 120, forming the gate structure 112 on the gate dielectric layer 124, and forming the ESL 116 and the ILD layer 118, each of which is not described in detail for the sake of clarity. After these operations, the semiconductor device 100 having the second isolation layer 120 surrounding the second portion 108-2 of the fin structure 108 may be as shown. Figures 1 to 3 Manufactured as shown in FIG.

[0096] Various embodiments of the present disclosure provide example methods for forming a second isolation layer 120 that surrounds a second portion 108-2 of a fin structure 108 in a semiconductor device 100. In some embodiments, the fin structure 108 may be formed on a substrate 104, and a first isolation layer 106 may be formed on the substrate 104 and surround the first portion 108-1 of the fin structure 108. The fin structure 108 may have an inclined sidewall. The fin structure 108 above the first isolation layer 106 may be trimmed to form a second portion 108-2 having an inclined sidewall surface and a third portion 108-3 having a substantially vertical sidewall surface. The second isolation layer 120 may be formed on the first isolation layer 106 to surround the second portion 108-2 of the fin structure 108 so as to cover the inclined sidewall surface. The gate structure 112* may be formed on the second isolation layer 120 and surround the third portion 108-3 of the fin structure 108. Therefore, the gate structure 112* may have substantially vertical sidewall surfaces without gate footers for improved gate control and reduced leakage current. The substantially vertical sidewall surfaces of the gate structure 112* may reduce metal gate extrusion defects and S / D epitaxial pit defects in subsequent manufacturing processes.

[0097] A semiconductor structure includes a channel structure on a substrate, the channel structure having a first portion, a second portion, and a third portion. The first portion has a first width. The second portion has a second width less than the first width. The third portion has a third width less than the second width. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion of the channel structure, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure. In some embodiments, the second portion of the channel structure has a plurality of inclined sidewall surfaces. In some embodiments, the third portion of the channel structure has a plurality of substantially vertical sidewall surfaces. In some embodiments, the semiconductor structure further includes a source / drain structure on the second portion of the channel structure and above the second isolation layer. In some embodiments, the top surface of the second isolation layer is above the second portion of the channel structure. In some embodiments, the ratio of the third width of the third portion to the second width of the second portion ranges from 50% to 90%. In some embodiments, the ratio of the thickness of the second isolation layer to the sum of the height of the second portion of the channel structure and the height of the third portion ranges from 15% to 40%.

[0098] A semiconductor structure includes a first channel structure and a second channel structure on a substrate. Each of the first channel structure and the second channel structure includes an inclined first portion, an inclined second portion, and a vertical third portion. The semiconductor structure further includes a first isolation layer on the substrate and between the first channel structure and the second channel structure, a second isolation layer on the first isolation layer and between the first channel structure and the second channel structure, and a gate structure on the second isolation layer and surrounding the vertical third portion of the first channel structure and the vertical third portion of the second channel structure. The inclined second portion of the first channel structure and the inclined second portion of the second channel structure are within the second isolation layer. In some embodiments, the inclined second portion of the first channel structure and the inclined second portion of the second channel structure contact the second isolation layer. In some embodiments, the semiconductor structure further includes a first source / drain structure on the inclined second portion of the first channel structure and a second source / drain structure on the inclined second portion of the second channel structure, wherein the first source / drain structure and the second source / drain structure are above the second isolation layer. In some embodiments, the top surface of the second isolation layer is above the inclined second portion of the first channel structure. In some embodiments, the inclined second portion of the first channel structure and the inclined second portion of the second channel structure have a first width, and the vertical third portion of the first channel structure and the vertical third portion of the second channel structure have a second width less than the first width. In some embodiments, the vertical third portion of the first channel structure and the vertical third portion of the second channel structure have a plurality of substantially vertical sidewall surfaces. In some embodiments, the gate structure has a plurality of substantially vertical sidewall surfaces. In some embodiments, the ratio of the thickness of the second isolation layer to the sum of the height of the first channel structure and the height of the second channel structure ranges from 15% to 40%.

[0099] A method for forming a semiconductor structure includes forming a channel structure on a substrate, and forming a first isolation layer on the substrate and surrounding a first portion of the channel structure. The first portion has a first width. The method further includes trimming the channel structure above the first isolation layer, forming a second isolation layer on the first isolation layer, and forming a gate structure on the second isolation layer and surrounding a third portion of the channel structure. The second isolation layer surrounds a second portion of the channel structure, and the second portion has a second width less than the first width. The third portion has a third width less than the second width. In some embodiments, trimming the channel structure above the first isolation layer includes forming a second portion of the channel structure having a plurality of inclined sidewall surfaces, and forming a third portion of the channel structure having a plurality of substantially vertical sidewall surfaces. In some embodiments, the method for forming a semiconductor structure further includes forming a source / drain structure on the second portion of the channel structure and above the second isolation layer. In some embodiments, forming the second isolation layer includes depositing a dielectric material on the first isolation layer using a flow chemical vapor deposition method. In some embodiments, forming the gate structure includes forming a plurality of substantially vertical sidewall surfaces of the gate structure.

[0100] A semiconductor structure includes a channel structure on a substrate, the channel structure including a first portion, a second portion, and a third portion. The first portion has a first width, the second portion has a second width less than the first width, and the third portion has a third width less than the second width. The ratio between the height of the second portion of the channel structure and the height of the third portion of the channel structure ranges from 20% to 60%. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion of the channel structure, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure.

[0101] It should be understood that the "Detailed Description" section, and not the "Abstract" section, is intended to be used to interpret the claims. The "Abstract" section may set forth one or more but not all possible embodiments of the disclosure as contemplated by the authors of the disclosure, and therefore is not intended to limit the appended claims in any way.

[0102] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they can easily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not deviate from the spirit and scope of some embodiments of the present disclosure, and such equivalent constructions can be variously changed, replaced and substituted in some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: Include: A channel structure comprises a first portion, a second portion and a third portion on a substrate, wherein: The first portion has a first width; The second portion has a second width that is smaller than the first width; and The third portion has a third width that is smaller than the second width; a first isolation layer on the substrate and surrounding the first portion of the channel structure; a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure; and A gate structure is on the second isolation layer and surrounds the third portion of the channel structure.

2. The semiconductor structure according to claim 1, wherein: The second portion of the channel structure has a plurality of inclined side wall surfaces.

3. The semiconductor structure according to claim 1, wherein: The third portion of the channel structure has a plurality of substantially vertical sidewall surfaces.

4. The semiconductor structure according to claim 1, wherein: A top surface of the second isolation layer is above the second portion of the channel structure.

5. The semiconductor structure according to claim 1, wherein: A ratio of the third width of the third portion to the second width of the second portion is in a range of 50% to 90%.

6. The semiconductor structure according to claim 1, wherein: A ratio of a thickness of the second isolation layer to a sum of a height of the second portion of the channel structure and a height of the third portion ranges from 15% to 40%.

7. A semiconductor structure, characterized in that: Include: A first channel structure and a second channel structure are on a substrate, wherein each of the first channel structure and the second channel structure comprises an inclined first portion, an inclined second portion and a vertical third portion; a first isolation layer on the substrate and between the first channel structure and the second channel structure; a second isolation layer on the first isolation layer and between the first channel structure and the second channel structure, wherein the inclined second portion of the first channel structure and the inclined second portion of the second channel structure are located in the second isolation layer; and A gate structure is on the second isolation layer and surrounds the vertical third portion of the first channel structure and the vertical third portion of the second channel structure.

8. The semiconductor structure according to claim 7, wherein: The inclined second portion of the first channel structure and the inclined second portion of the second channel structure contact the second isolation layer.

9. The semiconductor structure according to claim 7, wherein: Further including: A first source / drain structure on the inclined second portion of the first channel structure and a second source / drain structure on the inclined second portion of the second channel structure, wherein the first source / drain structure and the second source / drain structure are above the second isolation layer.

10. A semiconductor structure, characterized in that: Include: A channel structure is provided on a substrate, wherein the channel structure comprises a first portion, a second portion and a third portion, wherein: The first portion has a first width; The second portion has a second width that is smaller than the first width; and The third portion has a third width that is smaller than the second width, and wherein a ratio between a height of the second portion of the channel structure and a height of the third portion of the channel structure ranges from 20% to 60%; a first isolation layer on the substrate and surrounding the first portion of the channel structure; a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure; and A gate structure is on the second isolation layer and surrounds the third portion of the channel structure.

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