Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a fin, a gate structure, and a plurality of gate spacers. The fins are located on the substrate and longitudinally extend along a first direction. The gate structure is over the fin and extends longitudinally along a second direction perpendicular to the first direction. A plurality of gate spacers are on a plurality of sidewalls of the gate structure. The fin is provided with a first part and a second part, the first part is located under the gate structure, the second part is located under the gate spacer, and the width of the second part is larger than that of the first part in the second direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure, and more particularly to a fin with fog. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to many generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or circuit) that can be manufactured using a manufacturing process) has decreased. This reduction in size has also increased the complexity of IC processing and manufacturing.

[0003] As the geometric size of IC devices decreases, in some IC designs, such as Field-Effect Transistors (FETs) designs, the gate formation process with decreasing gate critical dimensions (CDs) and gate pitch may also introduce footing profiles, voids in the polysilicon gate, and excessive fin top loss, which may cause defects in the IC device and may affect the overall performance of the IC device. Although existing IC design and manufacturing methods are generally sufficient for the intended purpose, they are not satisfactory in every aspect. Utility Model Content

[0004] In an exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a fin, a dielectric fin, a gate structure, and a plurality of gate spacers. The fin is located above the substrate and extends longitudinally along a first direction. The dielectric fin is located above the substrate. The gate structure is located above the fin and the dielectric fin and extends longitudinally along a second direction perpendicular to the first direction. A plurality of gate spacers are located on a plurality of sidewalls of the gate structure. The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the gate spacer, wherein the width of the second portion along the second direction is greater than the width of the first portion.

[0005] In another exemplary embodiment, the present disclosure is related to a semiconductor structure. The semiconductor structure includes a substrate, a fin, a source / drain feature, a metal gate structure, and a plurality of gate spacers. The fin is located above the substrate and extends longitudinally along a first direction. The source / drain feature is located above the fin. The metal gate structure is located above the fin and extends longitudinally along a second direction perpendicular to the first direction. A plurality of gate spacers are located on a plurality of sidewalls of the metal gate structure. The fin has a first portion and a second portion, the first portion is located directly below the metal gate structure, and the second portion is located directly below the gate spacer, wherein the width of the second portion along the second direction is greater than the width of the first portion. A portion of some of the gate spacers protrudes into the metal gate structure.

[0006] In another exemplary aspect, the present disclosure is related to a semiconductor structure. The semiconductor structure includes a substrate; a fin located on the substrate and extending longitudinally along a first direction; a gate structure located above the fin and extending longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers located on a plurality of sidewalls of the gate structure. The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the gate spacer, wherein the width of the second portion along the second direction is greater than the width of the first portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0008] Figure 1 A flow chart for forming a semiconductor structure is shown according to one or more aspects of the present disclosure;

[0009] Figure 2 A partial perspective view showing an exemplary workpiece according to various aspects of the present disclosure;

[0010] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A According to various aspects of the present disclosure, Figure 1 A partial top view of an exemplary workpiece during various manufacturing stages in the method;

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B According to various aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A A partial cross-sectional view of the workpiece along line BB;

[0012] Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C and Fig. 10C According to various aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A A partial cross-sectional view of the workpiece along line CC;

[0013] Figure 3D , Figure 4D , Figure 5D , Fig.6D , Fig.7D , Fig.8D , Fig.9D and Fig. 10D According to various aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A A partial cross-sectional view of the workpiece along line DD;

[0014] Figure 3E , Figure 4E , Figure 5E , Fig. 6E , Fig. 7E , Fig. 8E , Fig.9E and Fig. 10E According to various aspects of the present disclosure, Figure 1During the various manufacturing stages of the method Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A A partial cross-sectional view of the workpiece along line EE;

[0015] Fig.10F According to various aspects of the present disclosure, Figure 1 During the manufacturing phase of the method Fig. 10A The area of ​​line FF and along Fig. 10B , Fig. 10C , Fig. 10D and Fig. 10E A partial cross-sectional view of the workpiece along line F-F'.

[0016]

Explanation of symbols

[0017] 10: Methods

[0018] 12,14,16,18,20,22,24,26,28:Step 100:Workpiece

[0019] 102:Substrate

[0020] 104,104',104a,104b,104a',104b': fins

[0021] 104c: Channel area

[0022] 104ca,104cb: Side part

[0023] 104cc: Center section

[0024] 104sd: Source / drain region

[0025] 105: Dielectric fin / dummy gate

[0026] 106: Isolation Structure / Isolation Characteristics

[0027] 108: Fin oxide layer

[0028] 110: Oxide layer

[0029] 115: epitaxial layer

[0030] 120: Footing part

[0031] 120': Oxidation footing

[0032] 125: Gate spacer

[0033] 126: Bump

[0034] 130: dummy gate structure

[0035] 131: Gap

[0036] 132: Gate hard mask layer

[0037] 135,135a,135b: Source / drain characteristics

[0038] 140:ILD layer

[0039] 145:CESL

[0040] 150: Gate trench

[0041] 155:Metal gate structure

[0042] 155a: Side part

[0043] 155c: Center part

[0044] 156: High-k dielectric layer

[0045] 158: Work function layer

[0046] 157: Gap

[0047] 160: Work function layer

[0048] 162:Metal filling layer

[0049] 165: Gate electrode

[0050] 170: Corner

[0051] 175: Footing corner

[0052] BB,CC,DD,EE,F'-F',GG:Line

[0053] FF: Region

[0054] D1, D2: distance

[0055] S1: Sidewall

[0056] S1': unoxidized sidewalls

[0057] S2, S2”: top surface

[0058] S2': unoxidized top surface

[0059] S3: Surface

[0060] S3': unoxidized surface

[0061] S4': unoxidized sidewalls

[0062] S5': unoxidized top surface

[0063] S5”: Top surface

[0064] T1, T2, T2', T3', T4', T5': thickness

[0065] W,W',Wa,Wb: Width

[0066] X,Y,Z: Direction DETAILED DESCRIPTION

[0067] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed. In addition, various features may be arbitrarily drawn in different proportions for simplicity and clarity.

[0068] In addition, for ease of description, the present disclosure may use spatially relative terms, such as "below", "under", "lower", "above", "upper", etc. to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientations shown in the accompanying drawings. For example, if the device in the figure is turned over, the elements described as "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the exemplary term "below" can cover both above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can also be interpreted accordingly.

[0069] In addition, when the terms "approximately", "about", etc. are used to describe a number or a range of numbers, such terms are intended to cover the inherent variations within a reasonable range that would occur during the process as understood by a person of ordinary skill in the art. A number or range of numbers encompasses a reasonable range of the number being described, for example, based on known manufacturing tolerances associated with manufacturing features having properties associated with the number, such as within + / -10% of the number being described. For example, a material layer having a thickness of "approximately 5 nanometers (nm)" may cover a range of sizes between 4.25 nm and 5.75, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with the deposited material layer is + / -15%. Further, the present disclosure may repeat figure numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself specify the relationship between the various embodiments and / or configurations discussed.

[0070] As integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). A multi-gate device generally refers to a device having a metal gate structure or a portion thereof disposed above more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel (e.g., a gate surrounds the top and sidewalls of a semiconductor material "fin" extending from a substrate) surrounded by a multi-sided gate. MBC transistors have a metal gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of an MBC transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also provides an alternative name for MBC transistors, such as a nanosheet transistor or a nanowire transistor. Variants of MBC transistors have been proposed to reduce the cell size, such as fishbone structures or fork-piece structures. In the fork-piece structure, adjacent stacks of channel members can be separated by dielectric walls (also called dielectric fins). The height of the dielectric wall is generally substantially equal to or greater than the height of the topmost channel member or source / drain feature. Complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) dominate the semiconductor industry due to their high noise immunity and low static power consumption. CMOS FETs include n-type FETs (n-type field effect transistors, NFETs) and p-type FETs (p-typefield effect transistors, PFETs) arranged side by side on the same substrate, and the NFETs and PFETs share the same structure. In some embodiments, the NFETs and PFETs are both planar devices, both are FinFETs, or both are MBC transistors.

[0071] The semiconductor structure may have a dummy gate formed above the fin structure. The dummy gate may be a polysilicon gate structure, which will be replaced by a gate stack (e.g., a high-k metal gate stack) in the last gate process. The dummy gate may be formed by various process steps, such as layer deposition, patterning, etching, and other suitable process steps. When forming the dummy gate, the top of the fin structure not covered by the dummy gate may be etched, resulting in loss of the top of the fin, thereby affecting the overall performance of the semiconductor device and reducing the device yield. In addition, the dummy gate at the bottom intersecting with the fin structure may have a footing portion, also referred to as a corner residue. Corner residue refers to the residue (or byproduct) left at the corner where the dummy gate structure, the fin structure, and the top surface of the substrate (as will be explained in further detail below, the top surface of the substrate may include isolation features) intersect. The residue accumulated in the corner causes the gate length to be uneven along the height of the dummy gate structure. When the dummy gate is replaced with a metal gate in the last gate process, the metal gate will inherit this gate length non-uniformity and have a protruding profile (i.e., a larger gate length) at the corner, referred to as a "protruding corner". This non-uniformity can affect many operating parameters of the device, such as speed performance and power consumption. There is also a concern that the increased protruding profile may cause an electrical short between the gate stack and the source / drain features formed after the dummy gate, and may cause a device short caused by leakage of metal material from the protruding corner during the last gate process, also known as a "metal gate protrusion". In addition, layer deposition may form a void in the dummy gate. When a gate spacer is formed on the sidewall of the dummy gate, the gate spacer may be formed inside the void. Subsequently, when the dummy gate is replaced with a gate stack, the gate spacer within the void is retained, resulting in defects in the gate stack.

[0072] The present disclosure generally relates to semiconductor structures and manufacturing methods. More specifically, the present disclosure relates to a semiconductor structure including a fin, a gate structure on the fin, and a gate spacer on a sidewall of the gate structure. The height and width of a portion of the fin directly below the gate spacer are greater than the height and width of the fin directly below the gate structure. The method of manufacturing the semiconductor structure includes oxidizing the surface of the dummy gate structure and the exposed surface of the fin to form an oxide layer, removing the oxide layer and epitaxially growing a cap layer. The base portion of the dummy gate structure can be oxidized to form a portion of the oxide layer and then removed. The cap layer can enlarge the fin not covered by the dummy gate structure and reduce the size of any gaps in the dummy gate structure.

[0073] The various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 According to an embodiment of the present disclosure, a flow chart of a method 10 for forming a semiconductor structure is shown. Figure 2-10F Description Method 10, Figure 2-10F 1 is a partial perspective view, a top view, and a cross-sectional view of a workpiece 100 at different stages of manufacture according to method 10 of an embodiment. Method 10 is merely an example and is not intended to limit the present disclosure to the contents explicitly described therein. Additional steps may be provided before, during, and after method 10, and additional embodiments of this method may replace, eliminate, or move some of the steps described. For simplicity, not all steps are described in detail herein. Because workpiece 100 will be manufactured into a semiconductor structure at the end of the manufacturing process, workpiece 100 may be referred to as semiconductor structure 100 as the context requires. For the avoidance of doubt, Figure 2-10F The X, Y and Z directions in FIG. 1 are perpendicular to each other and are used consistently in this disclosure. Unless otherwise specified, similar reference numerals are used throughout this disclosure to represent similar features.

[0074] refer to Figure 1 , Figure 2 and Figure 3A-3B The method 10 includes step 12 of providing a workpiece 100 in a fin. Figure 2 and Figure 3A According to various aspects of the present disclosure, the workpiece 100 is shown to undergo Figure 1 Partial perspective views and partial top views of various operating stages in method 10. Figure 3B-Figure 3E Shown along Figure 3A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0075] The workpiece 100 may be an intermediate device in the process of manufacturing an integrated circuit (IC), and may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors and inductors, active components such as p-type field effect transistors (pFETs), n-type FETs, fin field effect transistors (finFETs), metal-oxide semiconductor field effect transistors (metal-oxide semiconductor field effect transistors, MOSFETs), complementary metal oxide semiconductors (CMOS), transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other storage units and combinations thereof. In addition, for simplicity and ease of understanding, various features including transistors, gate stacks, active regions, isolation structures and other features are provided in various embodiments of the present disclosure, and the embodiments need not be limited to any type of device, any number of devices, any number of regions, or any configuration of structures or regions.

[0076] like Figure 2-Figure 3EAs shown, the workpiece 100 includes a substrate 102. In the illustrated embodiment, the substrate 102 is a silicon substrate. Alternatively, the substrate 102 may include another elementary semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or a combination thereof. In another embodiment, the substrate 102 includes indium tin oxide (ITO) glass. In various embodiments, the substrate 102 is a wafer, such as a silicon wafer, and one or more epitaxially grown semiconductor layers may be included above the wafer.

[0077] In some embodiments, the workpiece 100 includes a plurality of active regions 104 (eg, fin-shaped active regions, also referred to as fins 104 ), such as Figure 2 , Figure 3A The fins 104a and 104b in the embodiment may be individually or collectively referred to as fins 104. Figure 2 As shown, each fin 104 extends longitudinally along the X direction. The fin 104 and the fin 104b have a width Wa and a width Wb respectively along the Y direction. Figure 2 , Figure 3A The number of fins 104 and the number of dummy gate structures 130 shown in the figure are for illustration purposes only and should not be construed as limiting the scope of the present disclosure. In the described embodiment, the fins 104 are disposed above the substrate 102. In the embodiment where the workpiece 100 includes a FinFET, the fins 104 can be formed from a single semiconductor element (e.g., Si). In the embodiment where the workpiece 100 includes an MBC transistor, the fins 104 include one or more nanostructures (e.g., multiple channel layers). Each nanostructure can be formed from silicon (Si).

[0078] In the present embodiment, the workpiece 100 further includes an isolation feature 106 formed around each fin 104 to isolate two adjacent fins 104. The isolation feature 106 may also be referred to as a shallow trench isolation (STI) feature, and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0079] In some embodiments, Figure 2As shown, the workpiece 100 also includes a fin oxide layer 108 on the surface of the fin 104. In the illustrated embodiment, the fin oxide layer 108 is formed as a blanket layer over the top surface and sidewall surfaces of the fin 104, but not on the top surface of the isolation structure 106. In an alternative embodiment, the fin oxide layer 108 is formed over the top surface and sidewall surfaces of the fin 104 and on the top surface of the isolation structure 106. The fin oxide layer 108 can be formed before forming the dummy gate structure 130 and provides protection for the fin 104. The fin oxide layer 108 can be formed by various methods, such as chemical oxidation of silicon, thermal oxidation of silicon, ozone oxidation of silicon, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods. The fin oxide layer 108 may include silicon oxide or a high-k oxide (whose dielectric constant is greater than that of silicon oxide), such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, or a combination thereof. The fin oxide layer 108 may be formed to have a thickness of several angstroms to tens of angstroms. Figure 3A In the figure, the fin oxide layer 108 is not explicitly shown, however, its thickness along the Y direction is reflected in the portion of the fin 104 that does not overlap the gate hard mask layer 132 (i.e., not directly under the gate hard mask layer 132 (described below)). In other words, the portion of the fin 104 that does not overlap the gate hard mask layer 132 reflects the width along the Y direction, which includes the width of the fin 104 (e.g., Wa, Wb) and twice the thickness of the fin oxide layer 108; the portion of the fin 104 that overlaps the gate hard mask layer 132 (i.e., directly under the gate hard mask layer 132) reflects the width of the fin 104 along the Y direction (e.g., Wa, Wb).

[0080] In some embodiments, the workpiece 100 also includes a dielectric fin 105 (also referred to as a dummy gate 105) above the isolation structure 106. The dielectric fin 105 can be part of a hybrid fin. The formation of the dielectric fin 105 can include depositing a dielectric layer above the isolation structure 106, patterning the dielectric layer, and planarizing the top surface of the dielectric layer. The dielectric fin 105 can include any suitable dielectric material and can define a space for forming source / drain epitaxial features to prevent undesirable merging of adjacent source / drain epitaxial features.

[0081] In some embodiments, the workpiece 100 further includes a dummy gate structure 130 located above the fin 104 and the fin oxide layer 108. The dummy gate structure 130 may be located on the top surface and sidewalls of the fin oxide layer 108. The dummy gate structure 130 may span one or more fins 104, isolation structures 106, and / or dielectric fins 105. The length direction of the dummy gate structure 130 is perpendicular to the length direction of the fin 104. In some examples, forming the dummy gate structure 130 includes depositing a dummy gate layer comprising polysilicon or other suitable materials, and patterning the dummy gate layer by photolithography and etching. A gate hard mask layer 132 may be formed on the dummy gate material layer and used as an etching mask during the formation of the dummy gate structure 130. The gate hard mask layer 132 may include any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable materials, and / or combinations thereof. In one embodiment, the gate hard mask layer 132 includes a multilayer film, such as silicon oxide and silicon nitride. In some embodiments, the patterning process for forming the dummy gate structure 130 includes forming a patterned photoresist layer by a photolithography process; etching the hard mask layer using the patterned photoresist layer as an etching mask; and etching the dummy gate layer using the patterned hard mask layer (i.e., the gate hard mask layer 132) as an etching mask to form the dummy gate structure 130.

[0082] Due to process reasons such as etching effects during the formation of the dummy gate structure 130, the bottom portion of the dummy gate structure 130 intersecting the fin 104 may be wider than other portions away from the fin. The widening of the bottom portion of the dummy gate structure 130 intersecting the fin 104 is called the "footing effect" and the widened portion is called the footing region (or portion) 120. In the Z direction, the dummy gate structure 130 may include an upper portion having a straight and vertical sidewall, and a lower portion having an inclined sidewall. The inclined sidewall may also be straight, or may be substantially straight but with a slight curvature. The dummy gate structure 130 includes an exposed sidewall S1.

[0083] Due to process reasons, such as etching effects when forming the dummy gate structure 130, the top of some areas of the fin 104 and the fin oxide layer 108 above the fin may be removed. The area of ​​the fin 104 with such fin top loss is also called the fin top loss region (FTL region), and the area of ​​the fin 104 without fin top loss is called the non-FTL region. This fin top loss reduces the effective channel area and reduces the current therein. In the case of Figure 3B , Figure 3EIn the illustrated embodiment, the FTL region includes the portion of the fin 104a between two adjacent dummy gate structures 130, and the non-FTL region includes the fin 104b and the other portion of the fin 104a. The top portion of the FTL region and the fin oxide layer 108 thereon are removed (e.g., during the formation of the dummy gate structure 130), thereby forming an opening 112 (also referred to as a recess 112). The top portion of the non-FTL region is still protected by the fin oxide layer 108 and / or the dummy gate structure 130 thereon, and the top surface of the non-FTL region has a similar height. Therefore, the top surface S2 of the fin 104a (e.g., the FTL region) is exposed to the opening 112 and is lower than the top surface of the non-FTL region.

[0084] In some embodiments, the dummy gate structure 130 includes a void 131 adjacent to a sidewall of the dummy gate structure. The void 131 includes a surface S3 intersecting the sidewall S1. The surface S3 may include one or more surfaces having any shape, for example, the surface S3 may be a curved surface or include a plurality of facets. In some embodiments, as shown in FIG. Figure 3C As shown, the void 131 does not pass through the dummy gate structure 130. In some other embodiments, the void 131 horizontally crosses the dummy gate structure 130. Figure 3D In the cross-sectional view of , the void 131 has a maximum width W along the Y direction. The void 131 may be disposed between the dielectric fin 105 and the fin 104. The void 131 may be formed during the formation of the dummy gate structure 130 (eg, during the deposition of the dummy gate layer).

[0085] refer to Figure 1 and Figure 4A-4E The method 10 includes step 14 , wherein the exposed surfaces of the fins 104 and the dummy gate structure 130 are oxidized to form an oxide layer 10 . Figure 4A A partial top view of a workpiece 100 is shown. Figure 4B-Figure 4E Shown along Figure 4A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0086] In some embodiments, the oxide layer 110 is formed by performing an oxidizing process or oxidation process on the workpiece 100. In some embodiments, the exposed surfaces of the fin 104 and the dummy gate structure 130 include the sidewall S1 of the dummy gate structure 130, the top surface S2 of the fin 104a exposed to the opening 112, the surface S3 of the gap 131, or any combination thereof. In some embodiments, the footing portion 120 is also oxidized to form a portion of the oxide layer 110 (also referred to as an oxidized footing portion 120'). Any suitable method may be used to form the oxide layer 110. In some embodiments, the oxidation process includes a rapid thermal oxidation (RTO) process, a high pressure oxidation (HPO) process, a chemical oxidation process, an in-situ stream generation (ISSG) process, or an enhanced in-situ stream generation (EISSG) process. In some embodiments, oxygen (O 2 ) and ozone (O 3 ) as a reaction gas, and performing the RTO process at a temperature of about 400° C. to about 700° C. for about 1 second to about 30 seconds. 2 , O 2 With nitrogen (N 2 ) or N 2 The HPO is performed with a process gas such as sulphuric acid (HPO) at a pressure of about 1 atm to about 25 atm and a temperature of about 300° C. to about 700° C. for about 1 minute to about 10 minutes. Examples of chemical oxidation processes include wet SPM (sulfuric acid (H 2 SO 4 ) and / or hydrogen peroxide (H 2 O 2 )) Cleaning, wet O 3 / H 2 O, etc. In some embodiments, ozone deionized water (DIO3) can be applied to the workpiece 100. DIO3 can easily have an ozone concentration of 1ppm to about 100ppm, or about 30ppm to about 50ppm. Thereafter, an oxidation annealing can be performed on the workpiece 100 (i.e., in a processing chamber including an oxygen-containing gas). The oxidation process causes the oxide layer to have a certain thickness. The thickness of the oxide layer 110 can be in the range of about 0.1nm to about 5nm, or in the range of about 1nm to about 3nm. The oxide layer 110 formed on different exposed surfaces can have different thicknesses. In the example Figure 4CIn the illustrated embodiment, the void 131 may have a relatively small size, and the oxide layer 110 formed to the surface S3 of the void 131 may have a thickness T3 along the Y direction, and the oxide layer 110 formed to the sidewall S1 of the dummy gate structure 130 may have a thickness T1 along the X direction, and the thickness T3 is less than the thickness T1. In some embodiments, the oxide layer 110 may not be formed on all exposed surfaces of the fin 104 and the dummy gate structure 130. For example, when the DIO3 solution is applied, the DIO3 may not contact all surfaces S3 of the void 131, so only a portion of the surface S3 of the void 131 is oxidized or not oxidized. In some embodiments, the oxide layer 110 formed to the surface S2 of the fin 104a has a thickness T2 along the Z direction. T2 may be similar to T1. T2 and T1 may be in the range of about 0.3 nm to about 5 nm. If T1 and T2 are too small, the footing portion 120 may not be completely oxidized. If Tl and T2 are too large, too much of the dummy gate structure 130 and / or the top of the fin 104a exposed to the opening 112 may be oxidized, which will increase the difficulty of the subsequent step of removing the oxide layer 110 (to be described below) and may cause defects in the dummy gate structure 130 and / or the fin 104a; in addition, too many epitaxial layers will have to be grown in the subsequent steps (to be described below), resulting in the use of unnecessary materials and time costs.

[0087] refer to Figure 1 and Figure 5A-5E , the method 10 includes step 16 , in which the oxide layer 110 is removed. Figure 5A A partial top view of a workpiece 100 is shown. Figure 5B-5E Shown along Figure 5A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0088] In some embodiments, the exposed portion of the fin oxide layer 108 that is not covered by the dummy gate structure 130 (i.e., not directly under the dummy gate structure 130) is also removed in this step. After removing the exposed portion of the oxide layer 110 and the fin oxide layer 108, the unoxidized surface of the fin 104 and the dummy gate structure 130 is exposed. The unoxidized surface may include the unoxidized sidewall S1' of the dummy gate structure 130, the unoxidized top surface S2' of the FTL region of the fin 104a, the unoxidized top surface S5' of the non-FTL region of the fin 104a and the fin 104b, the unoxidized surface S3' of the gap 131, or any combination thereof. In some embodiments, the oxidized footing portion 120' is removed in this step. S5' may be higher than S2'.

[0089] The exposed portions of the oxide layer 110 and the fin oxide layer 108 may be removed using any suitable method. In one example, a wet etching process may be used to perform the removal process (step 16). In some embodiments, the removal process may be performed using a cycle of a high temperature sulfuric peroxide mixture (HTSPM) and dilute hydrofluoric acid (dHF), ozone (O3) and dHF, or a combination thereof.

[0090] refer to Figure 1 and Figure 6A-6E The method 10 includes step 18 , in which an epitaxial layer 115 (also referred to as a cap layer 115 ) is grown on the unoxidized surfaces of the fins 104 and the dummy gate structure 130 . Fig. 6A A partial top view of a workpiece 100 is shown. Figure 6B-Figure 6E Shown along Fig. 6A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0091] In some embodiments, the epitaxial layer 115 is grown directly from the unoxidized surfaces of the fin 104 and the dummy gate structure 130. In some embodiments, the epitaxial layer 115 is not grown directly from the unoxidized surfaces of the fin 104 and the dummy gate structure 130. In these embodiments, a seed layer (not shown) can be formed on the unoxidized surfaces of the fin 104 and the dummy gate structure 130, and then the epitaxial layer 115 is formed on the seed layer. In some embodiments, the epitaxial layer 115 includes silicon, carbon, germanium, or a combination thereof. In some embodiments, the epitaxial layer 115 includes silicon. In some embodiments, the epitaxial layer 115 includes a different composition than the fin 104. In the described embodiment, the epitaxial layer 115 includes the same composition as the fin 104 and is separated by the dotted fin 104. For illustration, the following describes an example in which the epitaxial layer 115 is formed of silicon. Using a material such as silane (SiH 4 ), silicon tetrachloride (SiCl 4 ), trichlorosilane (TCS) or dichlorosilane (SiH 2 Cl 2 or DSC) source gas to epitaxially grow the epitaxial layer 115. Hydrogen (H 2 ) as a reaction gas for reducing the above-mentioned source gas. Depending on the gas used, the deposition temperature during the formation of the epitaxial layer 115 can be in the range of about 700° C. to about 1250° C. For example, with a source gas having more chlorine atoms (e.g., SiCl4 Compared with TCS (or TCS), a source gas with fewer chlorine atoms (such as DSC) can be used at a lower formation temperature. The foregoing gas ranges and types are provided as examples and are not limiting. In an embodiment, the growth rates of the epitaxial layer 115 on the unoxidized surfaces of the fin 104 and the dummy gate structure 130 may be different, which may result in different thicknesses of the epitaxial layer 115 on the unoxidized surfaces of the fin 104 and the dummy gate structure 130. Forming the epitaxial layer 115 may be a time-controlled process such that the final thickness of the epitaxial layer 115 is achieved at the end of the process.

[0092] The fin 104 and the epitaxial layer 115 above the fin 104 together form a new fin including the fin 104a' and the fin 104b', and may be individually or collectively referred to as the fin 104'. Therefore, along the Y direction, the top of the fin 104' above the top surface of the isolation feature 106 is wider than the bottom of the fin 104' below the top surface of the isolation feature 106. In some embodiments, the thickness of the epitaxial layer 115 is in the range of about 0.1nm to about 5nm. If the thickness is too small, the fin top loss may not be recovered, so that the gap may be too large, affecting the overall performance of the semiconductor structure, and / or the width of the dummy gate 130 along the X direction may be too narrow, thereby collapsing more easily in subsequent steps. If the thickness is too large, adjacent fins 104' may be too close to each other, and / or adjacent dummy gate structures 130 may be too close to each other.

[0093] In some embodiments, the epitaxial layer 115 on different unoxidized surfaces is different. This may be due to the different shapes, materials and directions of the different unoxidized surfaces, as well as the operating conditions of the epitaxial growth process (such as seed materials, etc.). In some embodiments, the epitaxial layer 115 has a thickness T1' on the unoxidized sidewall S1' of the dummy gate structure 130, a thickness T2' on the unoxidized top surface S2' of the FTL region, a thickness T5' on the unoxidized top surface S5' of the non-FTL region, a thickness T3' on the unoxidized surface S3' of the gap 131, and a thickness T4' on the unoxidized sidewall S4' of the fin 104. In some embodiments, T2' is equal to or greater than T5'. In an embodiment, T2' and T5' are each equal to or greater than T1', T2', and T5' is each equal to or greater than T4'. In some embodiments, T3' is equal to or greater than T1' and / or T4'.

[0094] In some embodiments, T1′ is approximately the same as the thickness T1 of the oxide layer 110 formed to the sidewall S1 of the dummy gate structure 130. In some embodiments, T2′ is greater than the thickness T2 of the oxide layer 110 formed to the top surface S2 of the fin 104a. Fig. 6EIn the cross-sectional view of , the lowest top surface of the fin 104a' exposed to the opening 112 is higher than the lowest top surface of the fin 104a exposed to the opening 112. In other words, the fin top loss of the FTL region of the fin 104a is recovered, and the top surface of the FTL region is raised by about (T2'-T2) along the Z direction. A portion of the top surface S2" of the epitaxial layer 115 in the FTL region may be lower than a portion of the top surface S5" of the epitaxial layer 115 in the non-FTL region, and higher than, and may be higher than, the unoxidized top surface S5' of the non-FTL region of the fin 104 before forming the epitaxial layer 115. In some embodiments, T3' is greater than the thickness T3 of the oxide layer 110 formed to the surface S3 of the void 131. Therefore, in Fig.6D In the cross-sectional view of FIG. 1 , the gap 131 has a maximum width W' along the Y direction, which is smaller than Figure 3D The maximum width W before the oxidation process is shown. In other words, the size of the void 131 is reduced by approximately (W-W'). In an embodiment where the epitaxial layer 115 completely fills the void 131, W' is equal to 0. In the FTL region and between two adjacent epitaxial layers 115 on two opposite unoxidized sidewalls S1' of the dummy gate structure 130, the widths of the fins 104a' and 104b' along the Y direction are (Wa+2*T4') and (Wb+2*T4'), respectively. It should be noted that the portion of the fin 104 located directly below the dummy gate structure 130 can maintain the widths Wa and Wb along the Y direction during the process. Refer to Fig. 6A , from a top view, each fin 104' does not have a constant width, but has a junction with varying widths, which is called a fin jog structure. The fin jog structure includes two wider parts and a narrower part extending between the two wider parts. The two wider parts each have a width of (Wa+2*T4') or a width of (Wb+2*T4') along the Y direction. The two wider parts are not directly under the gate hard mask layer 132. In some embodiments, the narrower part is located under the gate hard mask layer 132 and has a width of Wa or Wb along the Y direction. In the next process, after the gate is replaced (e.g., step 26), the narrower part will be directly under the metal gate structure (described later).

[0095] After step 18, the top of the fin 104' above the top surface of the isolation feature 106 and not directly under the dummy gate structure 130 is enlarged in the Z direction and the Y direction. The bottom of the fin 104' below the top surface of the isolation feature 106 maintains the size of the fin 104. In the enlarged portion, the current driving capability of the fin 104' during the operation of the semiconductor structure 100 can be increased.

[0096] refer to Figure 1The method 10 further includes step 18, wherein an annealing process is performed on the workpiece 100. The annealing process may include rapid thermal annealing (RTA), millisecond annealing (MSA), microsecond annealing (μSA), microwave annealing, laser annealing, spike annealing, immersion annealing, furnace annealing, other suitable annealing processes, or combinations thereof.

[0097] refer to Figure 1 and Figure 7A-7E The method 10 includes step 22 , in which a gate spacer 125 is formed on the epitaxial layer 115 on the unoxidized sidewall S1 ′ of the dummy gate structure 130 . Fig. 7A A partial top view of a workpiece 100 is shown. Figure 7B-Figure 7E Shown along Fig. 7A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0098] The gate spacer 125 may have a thickness from about 2 nm to about 10 nm. In some embodiments where the epitaxial layer 115 does not completely fill the gap 131, the gate spacer 125 fills the remaining gap 131, such as Figure 7C , Fig.7DAs shown, a bump 126 of the gate spacer 125 is formed. In some examples, the gate spacer 125 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-k material, and / or a combination thereof. In some embodiments, the gate spacer 125 includes multiple layers, such as a liner spacer layer and a main spacer layer. For example, the gate spacer 125 can be formed by conformally depositing a dielectric material over the workpiece 100, using a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. After conformally depositing the dielectric material, a portion of the dielectric material used to form the gate spacer 125 can be etched back to expose a portion of the fin 104' (e.g., in the source / drain region 104sd, as described below). In some cases, the etch-back process removes a portion of the dielectric material forming the gate spacer 125 along the top surface of the dummy gate structure 130, thereby exposing the gate hard mask layer 132. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. It is noteworthy that after the etch-back process, the gate spacer 125 is still disposed on the epitaxial layer 115 located on the unoxidized sidewall S1' of the dummy gate structure 130. The width and height of the fin 104' directly below the gate spacer 125 may be respectively greater than the width and height of the fin 104' directly below the dummy gate structure 130. In some embodiments, on both sides of the dummy gate structure 130, the top surface S5" of the epitaxial layer 115 is higher than a portion of the top surface S2" of the epitaxial layer 115, and therefore, the gate spacers 125 located on both sides of the dummy gate structure 130 and connecting the top surface S5" and a portion of the top surface S2" have different heights. The region of the fin 104' directly below the gate hard mask layer 132 and the gate spacer 125 may be referred to as the channel region 104c. The region of the fin 104' not directly below the gate hard mask layer 132 or the gate spacer 125 may be referred to as the source / drain region 104sd. Depending on the context, the source / drain region 104sd may refer to the source region or the drain region individually or collectively. The FTL region may be wider than the source / drain region 104sd along the X direction, such as Figure 7B shown.

[0099] refer to Figure 1 and Figure 8A-8E , the method 10 includes step 24 , in which source / drain features 135 are formed in the source / drain region 104sd of the fin 104 ′. Fig. 8A A partial top view of a workpiece 100 is shown. Figure 8B-Figure 8E Shown along Fig. 8APartial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0100] The source / drain feature 135 may be formed by any suitable technique, such as an etching process followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove a portion of the fin 104', thereby forming a groove in the source / drain region 104sd. The groove may be cleaned using hydrofluoric acid (HF) or other suitable easy-to-perform cleaning processes. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial source / drain features in the groove. The top surface of the source / drain feature 135 may be higher than the top surface of the fin 104'. The source / drain feature 135 may be grown from the top surface and sidewall of the fin 104' exposed to the groove. Because in the fin 104 of step 18, the width and height of the fin 104' directly below the gate spacer (i.e., the portion of the fin 104' laterally exposed to the groove) begin to increase, the area of ​​the exposed surface of the fin 104' growing the source / drain feature 135 (also referred to as the exposed fin area) increases. In the depicted embodiment, the groove extends into the bottom portion of the fin 104' below the top surface of the isolation feature 106. In some other embodiments, the bottom surface of the groove is above the top surface of the isolation feature 106. Since the top of the fin 104' is wider than the bottom of the fin 104' in the Y direction, the groove can have a larger surface area. Each source / drain feature 135 can be suitable for forming a p-type FinFET device or an n-type FinFET device. The p-type source / drain feature can include one or more epitaxial layers of silicon germanium (epi SiGe) doped with a p-type dopant (e.g., boron, germanium, indium, and / or other p-type dopants). The n-type source / drain feature can include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC) doped with an n-type dopant such as arsenic, phosphorus, and / or other n-type dopants.

[0101] In some embodiments, Figure 8B , Figure 8C and Fig. 8EAs shown, a contact etch stop layer (CESL) 145 and an interlayer dielectric (ILD) layer 140 are formed over the workpiece 100. The CESL 145 may be formed of silicon nitride, silicon carbonitride, etc. For example, a conformal deposition method such as ALD or CVD may be used to form the CESL 145. The ILD layer 140 may include a dielectric material, which may be formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The ILD layer 140 may also be formed of an oxygen-containing dielectric material, which may be based on silicon oxide, such as Tetra Ethyl Ortho Silicate (TEOS) oxide, Plasma-Enhanced CVD (PECVD) oxide (SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), etc. A planarization step such as Chemical Mechanical Polish (CMP) or mechanical grinding is performed to make the top surfaces of the CESL 145, the ILD layer 140, the dummy gate structure 130, and the gate spacer 125 flush with each other. In some embodiments, the planarization step may remove the gate hard mask layer 132.

[0102] refer to Figure 1 and Figures 9A-10F The method 10 includes step 26 , in which the metal gate structure 155 replaces the dummy gate structure 130 , the epitaxial layer 115 on the unoxidized sidewall S1 ′ of the dummy gate structure 130 , and the fin oxide layer 108 .

[0103] refer to Figure 9A-9E , remove the dummy gate structure 130, the epitaxial layer 115 on the unoxidized sidewall S1' of the dummy gate structure 130, and the fin oxide layer 108 to form a gate trench 150. The resulting structure is as shown in FIG. Figure 9A-9E shown. Fig.9A A partial top view of a workpiece 100 is shown. Figure 9B-9E Shown along Fig.9A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE.

[0104] In some embodiments, the top surface and sidewalls of the fin 104' in the channel region 104c, the top surface and sidewalls of the dielectric fin 105, and the sidewalls of the gate spacer 125 including the bump 126 are exposed in the gate trench 150. In the illustrated embodiment, the dummy gate structure 130 and the epitaxial layer 115 on the unoxidized sidewall S1' of the dummy gate structure 130 are completely removed. In some other embodiments, a portion of the dummy gate structure 130 and / or the epitaxial layer 115 on the unoxidized sidewall S1' of the dummy gate structure 130 directly below the bump 126 are retained. However, because the size of the gap 131 has been reduced in the present method, the remaining portion can be ignored. The fin oxide layer 108 can be further removed. In some embodiments, the top surface of the fin 104' has a stepped profile in the channel region 104c. In some embodiments, the top surface of the center line (e.g., line GG) of the center portion 104cc of the fin 104' along the Y direction is lower than the top surface of the side portions 104ca and 104cb of the fin 104'. The side portion 104ca may have a stepped top surface, and the lower surface of the side portion 104ca is at the same level as the top surface of the side portion 104cb. This step may include one or more etching processes that are selective to the materials in the dummy gate structure 130 and the fin oxide layer 108, respectively. For example, a selective etching process such as selective wet etching, selective dry etching, or a combination thereof may be used to recess the epitaxial layer 115 on the unoxidized sidewall S1' of the dummy gate structure 130 and the dummy gate structure 130. In some embodiments, a solution having a fluoride compound is used as an etchant to recess the fin oxide layer 108 to remove the fin oxide layer 108. Fluoride can effectively remove silicon oxide material.

[0105] refer to Figures 10A-10F , a metal gate structure 155 is deposited in the gate trench 150 . Fig. 10A A partial top view of a workpiece 100 is shown. Figure 10B-10E Shown along Fig. 10A Partial cross-sectional views of the workpiece 100 are shown along lines BB, CC, DD, and EE. Fig.10F The workpiece 100 is shown in the region FF and along Fig. 10A and Fig. 10B The line F'-F' is slightly higher than the top surface of the isolation structure 106, so that any remaining footing portion in the region FF can be reflected in the Fig.10F in the cross-sectional view.

[0106] In some embodiments, the gate structure 155 follows the shape of the groove 150. The gate structure 155 may have an uneven bottom surface. In some embodiments, the gate structure 155 includes a central portion 155c along a center line (e.g., line GG) in the Y direction and two side portions 155a on both sides of the central portion 155c. The bottom surface of the central portion 155c is lower than the bottom surfaces of the two side portions 155a. In some embodiments, the gate structure 155 is connected to the bump 126.

[0107] In some embodiments, the gate structure 155 includes a high-k dielectric layer 156 and a gate electrode 165, such as Fig.10F The high-k dielectric layer 156 is formed of a high-k (dielectric constant greater than about 3.9) dielectric material, which may include hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, silicon zirconium oxide, aluminum oxide (Al 2 O 3 ), lanthanum oxide, yttrium oxide, strontium titanate, combinations thereof, or other suitable materials. High-k dielectric layer 156 may be deposited using CVD, ALD, and / or other suitable methods. Gate electrode 165 may include one or more work function layers 158 and 160 and a metal fill layer 162. Depending on the type of device (PFET or NFET), one or more work function layers 158 and 160 may include a p-type or n-type work function layer. Example n-type work function layers may be formed of aluminum, titanium aluminide, titanium aluminum carbide, tantalum silicon carbide, tantalum silicon aluminum tantalum, tantalum silicide, or hafnium carbide. Example p-type work function layers may be formed of titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbonitride, or molybdenum. Metal fill layer 162 may be formed of metals such as tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). Gate electrode 165 may be deposited using methods such as CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, the gate structure 155 further includes an interfacial layer (not shown), which may include a dielectric material such as a silicon oxide layer. The interfacial layer may be formed using chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods.

[0108] refer to Fig.10FIn some embodiments, the oxidized footing portion 120' is removed from the dummy gate structure 130 in step 16. The replacement metal gate structure 155 follows the shape and / or contour of the dummy gate structure 130 and thus has corners without footing effects, such as clean corners 170. In some other embodiments, a portion of the oxidized footing portion 120' is retained during this process. In such embodiments, the metal gate structure 155 includes a footing corner 175 extending to the remaining oxidized footing portion 120'. A gap 157 may be formed in the metal gate structure 155. The gap 157 may be located between the high-k dielectric layer 156 and the gate electrode 165. The gap 157 may include air. Although three clean corners 170 and one footing corner 175 are depicted, it should be understood that the metal gate structure 155 may include at least one clean corner 170 and any number of footing corners 175. In some embodiments, one metal gate structure 155 includes four clean corners 170 and no footing corners 175. As shown, the source / drain features 135 may include a source / drain feature 135a adjacent to the clean corner 170 and a source / drain feature 135b adjacent to the footing corner 175. The distance D1 between the gate electrode 165 at the clean corner 170 and the adjacent source / drain feature 135a is greater than the distance D2 between the gate electrode 165 at the footing corner 175 and the adjacent source / drain feature 135b. Therefore, an electrical short circuit between the gate electrode 165 at the clean corner 170 and the adjacent source / drain feature 135a can be avoided. In addition, the metal gate structure 155 with the clean corner 170 can improve many operating parameters of the semiconductor structure 100, such as speed performance and power consumption.

[0109] refer to Figure 1 , method 10 includes step 28, in which further processes are performed to complete the manufacturing workpiece 100. For example, subsequent processing can form contact openings, contact metals, and various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics), and is configured to connect various features to form functional circuits that may include one or more multi-gate devices. Various interconnect components can use various conductive materials, including copper, tungsten and / or silicide. In one example, a damascene and / or dual damascene process is used to form a copper-related multi-layer interconnect structure.

[0110] It will be understood by those skilled in the art that although Figure 2-10F FinFET devices are shown as an example, but various aspects of the present disclosure are also beneficial to other examples of semiconductor devices, such as GAA devices.

[0111] Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor devices and their formation. For example, embodiments of the present disclosure avoid electrical shorts in the device, reduce short channel effects (SCEs), and improve operating parameters of the device by reducing and / or eliminating the footing portion of the dummy gate structure. In addition, embodiments of the present disclosure increase current drive capability by vertically and horizontally expanding the fins not covered by the dummy gate structure during the manufacturing process of the device. Furthermore, the overall performance of the device can be improved by reducing the size and / or eliminating the gaps in the dummy gate structure in the methods disclosed herein.

[0112] In an exemplary embodiment, the present disclosure relates to a method for manufacturing a semiconductor structure. The method includes providing a workpiece. The workpiece includes a substrate, a fin protruding from the substrate, and a dummy gate structure above the fin. The method also includes performing an oxidation process on the exposed surfaces of the fin and the dummy gate structure to form an oxide layer above the exposed surfaces of the fin and the dummy gate structure; removing the oxide layer to expose the unoxidized top surface and multiple unoxidized sidewalls of the fin and multiple unoxidized sidewalls of the dummy gate; epitaxially growing a cap layer on the unoxidized top surface and unoxidized sidewalls of the fin and the unoxidized sidewalls of the dummy gate; forming source / drain features on the fin; and replacing the dummy gate structure with a metal gate structure. In some embodiments, the dummy gate includes a footing portion that intersects the fin, wherein performing the oxidation process includes oxidizing the footing portion, and removing the oxide layer includes removing the oxidized footing portion. In some embodiments, the oxide layer is a first oxide layer, the workpiece further includes a second oxide layer, the second oxide layer is disposed on a plurality of sidewalls of the fin, and the removal of the oxide layer includes removing a first portion of the first oxide layer and the second oxide layer that is not covered by the dummy gate structure, thereby retaining a second portion of the second oxide layer directly below the dummy gate structure. In some embodiments, before performing the oxidation process, a second oxide layer is further disposed on the top surface of the fin, the second oxide layer has a first thickness on the sidewalls of the fin, and the second oxide layer has a second thickness on the top surface of the fin, wherein the thickness of the cap layer on the unoxidized sidewalls of the fin is equal to or greater than the first thickness, and wherein the thickness of the cap layer on the unoxidized top surface of the fin is greater than the second thickness. In some embodiments, the dummy gate structure includes a void, wherein the exposed surfaces of the fin and the dummy gate include the exposed surface of the void, wherein the removal of the oxide layer further exposes the unoxidized surface of the void, and wherein epitaxially growing the cap layer includes epitaxially growing the cap layer on the unoxidized surface of the void. In some embodiments, after epitaxially growing the cap layer, the size of the void is smaller than the size before performing the oxidation process. In some embodiments, the workpiece further comprises a dielectric fin, the dielectric fin being located above the substrate and adjacent to the fin, and wherein a void is disposed between the fin and the dielectric fin. In some embodiments, before forming source / drain features on the fin, the method further comprises forming a plurality of gate spacers on the cap layer on the unoxidized sidewalls of the dummy gate structure. In some embodiments, the cap layer and the fin comprise the same composition. In some embodiments, the cap layer is epitaxially grown on the unoxidized top surface of the fin at a first rate, and wherein a second rate at which the cap layer is epitaxially grown on the unoxidized sidewalls of the fin and the dummy gate is less than the first rate.

[0113] In another exemplary aspect, the present disclosure relates to a method for a semiconductor structure. The method includes providing a workpiece. The workpiece includes a fin above a substrate, a first oxide layer disposed above a sidewall of the fin, and a dummy gate structure above the fin and directly above a first portion of the first oxide layer, wherein the first oxide layer also includes a second portion not covered by the dummy gate structure. The method also includes oxidizing multiple exposed surfaces of the fin and the dummy gate structure to form a second oxide layer; removing the second portion of the first oxide layer and the second oxide layer to expose multiple unoxidized surfaces of the fin and the dummy gate structure; and forming an epitaxial layer on the unoxidized surfaces of the fin and the dummy gate structure; wherein a thickness of the epitaxial layer is greater than or equal to the second oxide layer. Preferably, the method also includes forming multiple gate spacers on the epitaxial layer of the unoxidized surface of the dummy gate structure; forming source / drain features on the fin; and replacing the dummy gate structure with a metal gate structure. In some embodiments, the workpiece further includes an isolation feature adjacent to the fin and located below the dummy gate structure, wherein the dummy gate structure includes a footing portion that intersects the fin and the isolation feature, and wherein the exposed surface of the fin and the dummy gate structure is oxidized including the footing portion to form a portion of a second oxide layer. In some embodiments, the exposed surface of the fin and the dummy gate structure includes a top surface of the fin. In some embodiments, the method further includes performing an annealing process on the workpiece after forming the epitaxial layer. Preferably, the first portion of the first oxide layer is further disposed on the top surface of the fin, wherein the top surface of the epitaxial layer of the fin is higher than the top surface of the first oxide layer.

[0114] In another exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate; a fin is located on the substrate and extends longitudinally along a first direction; a gate structure is located above the fin and extends longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers are located on a plurality of sidewalls of the gate structure. The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the gate spacer, wherein the width of the second portion along the second direction is greater than the width of the first portion. In some embodiments, the height of the second portion of the fin is equal to or greater than the height of the first portion of the fin. In some embodiments, a portion of the gate spacer protrudes into the gate structure. In some embodiments, the first portion of the fin includes two first sub-portions and a second sub-portion, the first sub-portion is adjacent to the second portion of the fin, and the second sub-portion is inserted between the two first sub-portions along the first direction; wherein the top surfaces of the two first sub-portions are higher than the top surface of the second sub-portion.

[0115] In another exemplary embodiment, the present disclosure is related to a semiconductor structure. The semiconductor structure includes a substrate, a fin, a dielectric fin, a gate structure, and a plurality of gate spacers. The fin is located above the substrate and extends longitudinally along a first direction. The dielectric fin is located above the substrate. The gate structure is located above the fin and the dielectric fin and extends longitudinally along a second direction perpendicular to the first direction. A plurality of gate spacers are located on a plurality of sidewalls of the gate structure. The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the gate spacer, wherein the width of the second portion along the second direction is greater than the width of the first portion. In some embodiments, the fin is separated from the dielectric fin. In some embodiments, the source / drain feature is located above the fin and the dielectric fin. In some embodiments, the height of the second portion of the fin is equal to or greater than the height of the first portion of the fin.

[0116] In another exemplary embodiment, the present disclosure is related to a semiconductor structure. The semiconductor structure includes a substrate, a fin, a source / drain feature, a metal gate structure, and a plurality of gate spacers. The fin is located above the substrate and extends longitudinally along a first direction. The source / drain feature is located above the fin. The metal gate structure is located above the fin and extends longitudinally along a second direction perpendicular to the first direction. A plurality of gate spacers are located on a plurality of sidewalls of the metal gate structure. The fin has a first portion and a second portion, the first portion is located directly below the metal gate structure, and the second portion is located directly below the gate spacer, wherein the width of the second portion along the second direction is greater than the width of the first portion. A portion of the gate spacer protrudes into the metal gate structure. In some embodiments, the isolation feature is adjacent to the fin and is located below the metal gate structure.

[0117] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the content of the present disclosure. It should be understood by those skilled in the art that the content of the present disclosure can be easily used as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions and modifications herein.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; a fin, located above the substrate and extending longitudinally along a first direction; a dielectric fin located above the substrate; a gate structure, located above the fin and the dielectric fin, and extending longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers disposed on a plurality of sidewalls of the gate structure; The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the plurality of gate spacers. The width of the second portion along the second direction is greater than the width of the first portion.

2. The semiconductor structure according to claim 1, wherein: The fin is separated from the dielectric fin.

3. The semiconductor structure according to claim 1, wherein: Further including: A source / drain feature is located above the fin and the dielectric fin.

4. The semiconductor structure according to claim 1, wherein: A height of the second portion of the fin is equal to or greater than a height of the first portion of the fin.

5. A semiconductor structure, characterized in that: include: a substrate; a fin, located above the substrate and extending longitudinally along a first direction; a source / drain feature located above the fin; a metal gate structure, located above the fin and extending longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers disposed on a plurality of sidewalls of the metal gate structure; The fin has a first portion and a second portion, the first portion is located directly below the metal gate structure, and the second portion is located directly below the plurality of gate spacers. wherein the width of the second portion along the second direction is greater than the width of the first portion, Parts of the plurality of gate spacers protrude into the metal gate structure.

6. The semiconductor structure according to claim 5, characterized in that Further including: An isolation feature is adjacent to the fin and below the metal gate structure.

7. A semiconductor structure, characterized in that: include: a substrate; a fin, located above the substrate and extending longitudinally along a first direction; A gate structure is located above the fin and extends longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers disposed on a plurality of sidewalls of the gate structure; The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the plurality of gate spacers. The width of the second portion along the second direction is greater than the width of the first portion.

8. The semiconductor structure according to claim 7, wherein: A height of the second portion of the fin is equal to or greater than a height of the first portion of the fin.

9. The semiconductor structure according to claim 7, wherein: Parts of the plurality of gate spacers protrude into the gate structure.

10. The semiconductor structure according to claim 7, wherein: The first portion of the fin includes two first sub-portions and a second sub-portion, the first sub-portion is adjacent to the second portion of the fin, and the second sub-portion is inserted between the two first sub-portions along the first direction, The top surfaces of the two first sub-portions are higher than the top surface of the second sub-portion.

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