Signal time delay measuring circuit

Abstract

The utility model discloses a signal time delay measurement circuit, and the circuit comprises a first channel unit which is used for accessing a first test signal, and is also used for converting the first test signal into a first square wave signal; the second channel unit is used for accessing a second test signal and converting the second test signal into a second square wave signal; the logic XOR unit is electrically connected to the first channel unit and the second channel unit and is used for outputting a pulse signal according to the first square wave signal and the second square wave signal; the delay judgment unit is electrically connected to the first channel unit and the second channel unit and used for judging the delay relation between the first square wave signal and the second square wave signal according to the first square wave signal and the second square wave signal and outputting a delay signal; and the main control unit is electrically connected to the logic XOR unit and the time delay judgment unit and is used for calculating the lead time or the lag time of the first test signal relative to the second test signal according to the pulse signal and the time delay signal, the measurement cost is low, the method can be applied to automatic production, and the production efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic product detection, and in particular to a signal delay measurement circuit. Background Art

[0002] In electronic circuit design and manufacturing, it is usually necessary to measure the timing (such as power-on timing) to verify whether the circuit design meets the requirements for normal operation of the IC, or to detect whether the input and output delays of the related delay circuits meet the required design requirements. In laboratory testing, equipment such as oscilloscopes can be used for measurement, but in manufacturing, using oscilloscopes for measurement is not only costly, but also not conducive to automation and has low production efficiency. Utility Model Content

[0003] In view of this, it is necessary to provide a signal delay measurement circuit that reduces costs and can be applied to automation to improve production efficiency.

[0004] The embodiment of the present application discloses a signal delay measurement circuit, including: a first channel unit, used to access a first test signal, and also used to convert the first test signal into a first square wave signal; a second channel unit, used to access a second test signal, and also used to convert the second test signal into a second square wave signal; a logic XOR unit, electrically connected to the first channel unit and the second channel unit, used to perform XOR processing according to the first square wave signal and the second square wave signal and output a pulse signal; a delay judgment unit, electrically connected to the first channel unit and the second channel unit, used to determine the delay relationship between the first test signal and the second test signal according to the first square wave signal and the second square wave signal, and output a delay signal; a main control unit, electrically connected to the logic XOR unit and the delay judgment unit, used to calculate the lead time or lag time of the first test signal relative to the second test signal according to the pulse signal and the delay signal.

[0005] Preferably, the first channel unit includes: a limiting unit, electrically connected to the main control unit, for receiving the first test signal, and also for limiting the amplitude of the first test signal to a second preset value when the amplitude of the first test signal exceeds a first preset value; a first shaping unit, electrically connected to the limiting unit, the logical XOR unit and the delay judgment unit, for converting the first test signal into a square wave signal; a second shaping unit, electrically connected to the limiting unit, the logical XOR unit and the delay judgment unit, for de-jittering and shaping the first test signal; a first switch unit, including an input end, a first output end, a second output end and a control end, the first switch unit The input end of the first switch unit is electrically connected to the limiting unit, the first output end of the first switch unit is electrically connected to the first shaping unit, the second output end of the first switch unit is electrically connected to the second shaping unit, and the control end of the first switch unit is electrically connected to the main control unit; the second switch unit includes a first input end, a second input end, an output end and a control end, the first input end of the second switch unit is electrically connected to the first shaping unit, the second input end of the second switch unit is electrically connected to the second shaping unit, the output end of the second switch unit is electrically connected to the logical XOR unit and the delay judgment unit, and the control end of the second switch unit is electrically connected to the main control unit.

[0006] Preferably, the main control unit is further used to determine whether the first test signal is a square wave signal, and output a first control signal when the first test signal is not a square wave signal, and output a second control signal when the first test signal is a square wave signal;

[0007] The first switch unit is used to connect the input end of the first switch unit and the first output end of the first switch unit according to the first control signal, and to connect the input end of the first switch unit and the second output end of the first switch unit according to the second control signal;

[0008] The second switch unit is used to connect the first input end of the second switch unit to the output end of the second switch unit according to the first control signal, and to connect the second input end of the second switch unit and the output end of the second switch unit according to the second control signal.

[0009] Preferably, the limiting unit includes: a first resistor, one end of which is used to connect the first test signal; a first voltage-regulating diode, the cathode of which is electrically connected to the other end of the first resistor, and the anode of which is grounded; when the amplitude of the first test signal exceeds the first preset value, the first voltage-regulating diode is broken down, and the amplitude of the first test signal is limited to the second preset value.

[0010] Preferably, the first channel unit also includes: a buffer unit, including a first operational amplifier, the non-phase input terminal of the first operational amplifier is electrically connected to the cathode of the first voltage regulator tube, the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is electrically connected to the input terminal of the first switch unit.

[0011] Preferably, the first shaping unit includes: a second resistor, one end of which is electrically connected to the first output end of the first switching unit; a first hysteresis comparator, the inverting input end of the first hysteresis comparator is electrically connected to the other end of the second resistor; a third resistor, one end of which is electrically connected to the non-inverting input end of the first hysteresis comparator, and the other end is grounded; a fourth resistor, one end of which is electrically connected to one end of the third resistor, and the other end is electrically connected to the output end of the first hysteresis comparator; a second zener diode, the cathode of the second zener diode is electrically connected to the output end of the first hysteresis comparator, and the anode of the second zener diode is grounded; a diode, the anode of the diode is electrically connected to the output end of the first hysteresis comparator, and the anode of the diode is electrically connected to the logical XOR unit.

[0012] Preferably, the second shaping unit comprises: a Schmitt input buffer, the input end of the Schmitt input buffer is electrically connected to the first output end of the first switch unit, and the output end of the Schmitt input buffer is electrically connected to the first input end of the second switch unit.

[0013] Preferably, the structure of the second channel unit is the same as that of the first channel unit.

[0014] Preferably, the delay judgment circuit includes: a D flip-flop, including a clock signal input terminal, a data input terminal and a data output terminal, the clock signal input terminal of the D flip-flop is electrically connected to the output terminal of the second switch unit of the second channel unit, the data input terminal of the D flip-flop is electrically connected to the output terminal of the second switch unit of the first channel unit, and the output terminal of the D flip-flop is electrically connected to the main control unit; when the first test signal leads the second test signal, the D flip-flop outputs a high level signal; when the first test signal lags behind the second test signal, the D flip-flop outputs a low level signal.

[0015] Preferably, the main control unit is also used to: determine that the first test signal leads the second test signal based on the high-level signal, and determine that the first test signal lags behind the second test signal based on the low-level signal; start counting when the pulse signal reaches the rising edge, stop counting when the falling edge of the pulse signal arrives, and calculate the lead time or lag time of the first test signal and the second test signal based on the count.

[0016] Compared with the prior art, the signal delay measurement circuit provided in the embodiment of the present application obtains two sets of square wave signals after the first test signal and the second test signal pass through a shaping unit, and inputs the two sets of square wave signals into a logic XOR unit for XOR processing and then outputs a pulse signal; the lead and lag relationship between the first test signal and the second test signal is determined by a delay judgment unit and a delay signal is output, so that the main control unit calculates the lead time and lag time of the first test signal and the second test signal according to the delay signal and the pulse width of the pulse signal. The measurement cost is low and can be used in automated production to improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a module schematic diagram of an implementation of the signal delay measurement circuit of the present application.

[0018] Figure 2 It is a circuit diagram of an implementation of the signal delay measurement circuit of the present application.

[0019] Figure 3 It is a schematic diagram showing that a first test signal leads a second test signal in one implementation of the signal delay measurement circuit of the present application.

[0020] Figure 4 It is a schematic diagram showing that a first test signal lags behind a second test signal in one implementation of the signal delay measurement circuit of the present application.

[0021] Main component symbols

[0022] 1-Signal delay measurement circuit

[0023] 10-First channel unit

[0024] 11- Second channel unit

[0025] 12-Logical XOR unit

[0026] 13-Delay judgment unit

[0027] 14- Main control unit

[0028] 101a, 101b - Limiting unit

[0029] 102a, 102b - first shaping unit

[0030] 103a, 103b - second shaping unit

[0031] 104a, 104b-first switch unit

[0032] 105a, 105b- second switch unit

[0033] R1a, R1b - first resistor

[0034] D1a, D1b - the first voltage regulator

[0035] 106a, 106b-buffer unit

[0036] OA1a, OA1b - First operational amplifier

[0037] R2a, R2b - second resistor

[0038] OP1a, OP1b - first hysteresis comparator

[0039] R3a, R3b - the third resistor

[0040] R4a, R4b - the fourth resistor

[0041] D2a, D2b - the second voltage stabilizing diode

[0042] D3a, D3b - diode

[0043] OA2a, OA2b - Schmitt Input Buffer

[0044] 141-Edge Detection Unit

[0045] 142-Counter

[0046] 143-Clock

[0047] 144-Clock pre-scaling unit DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly described below in conjunction with the drawings in the embodiments of the present application.

[0049] It is understandable that the connection relationship described in this application refers to direct or indirect connection. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components. For example, A and C can be directly connected, and C and B can be directly connected, so that A and B are connected through C. It is also understandable that the "A connects B" described in this application can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0050] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is only a way to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0051] In the description of this application, words such as "first" and "second" are only used to distinguish different objects, and do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0052] The technical solution of the present application is further described in detail below in conjunction with the accompanying drawings.

[0053] See also Figure 1 , Figure 1 This is a functional module diagram of an implementation of the signal delay measurement circuit of the present application. The signal delay measurement circuit 1 can be used to measure the relative timing of two signals. The two signals can be the input signal and the output signal of the delay circuit respectively, and the signal delay measurement circuit 1 is used to detect whether the delay of the input signal and the output signal meets the design requirements. The two signals can also be timing signals, such as power-on timing, and the signal delay measurement circuit 1 is used to measure whether the delay of the timing signal meets the requirements for normal operation of the chip, etc.

[0054] In this embodiment, the signal delay measurement circuit 1 includes a first channel unit 10, a second channel unit 11, a logic XOR unit 12, a delay judgment unit 13 and a main control unit 14. The first channel unit 10 is used to access a first test signal and also to convert the first test signal into a first square wave signal. The second channel unit 11 is used to access a second test signal and also to convert the second test signal into a second square wave signal. The logic XOR unit 12 is electrically connected to the first channel unit 10 and the second channel unit 11, and is used to output a pulse signal according to the first square wave signal and the second square wave signal. The pulse width of the pulse signal reflects the delay between the first test signal and the second test signal. The delay judgment unit 13 is electrically connected to the first channel unit 10 and the second channel unit 11, and is used to determine the delay relationship between the first test signal and the second test signal according to the first square wave signal and the second square wave signal and output a delay signal. The main control unit 14 is electrically connected to the logic XOR unit 12 and the delay judgment unit 13, and is used to calculate the leading time or lagging time of the first test signal relative to the second test signal according to the pulse signal and the delay signal.

[0055] In this embodiment, the first channel unit 10 includes a limiting unit 101a, a first shaping unit 102a, a second shaping unit 103a, a first switch unit 104a and a second switch unit 105a. The limiting unit 101a is electrically connected to the main control unit 14 for accessing the first test signal, and is also used to limit the amplitude of the first test signal to a second preset value when the amplitude of the first test signal exceeds the first preset value. By limiting the amplitude of the first test signal to the second preset value by the limiting unit 101a, it is possible to prevent the input test signal from damaging the subsequent stage measurement circuit due to excessive amplitude. The first shaping unit 102a is electrically connected to the limiting unit 101a, the logical exclusive OR unit 12 and the delay judgment unit 13, and is used to convert the first test signal into a square wave signal. The second shaping unit 103a is electrically connected to the limiting unit 101a, the logical exclusive OR unit 12 and the delay judgment unit 13, and is used to de-jitter and shape the first test signal. The first switch unit 104a includes an input end, a first output end, a second output end and a control end. The input end of the first switch unit 104a is electrically connected to the limiter unit 101a, the first output end of the first switch unit 104a is electrically connected to the first shaping unit 102a, the second output end of the first switch unit 104a is electrically connected to the second shaping unit 103a, and the control end of the first switch unit 104a is electrically connected to the main control unit 14. The second switch unit 105a includes a first input end, a second input end, an output end and a control end. The first input end of the second switch unit 105a is electrically connected to the first shaping unit 102a, the second input end of the second switch unit 105a is electrically connected to the second shaping unit 103a, the output end of the second switch unit 105a is electrically connected to the logical XOR unit 12 and the delay judgment unit 13, and the control end of the second switch unit 105a is electrically connected to the main control unit 14.

[0056] The first test signal can be a sine wave signal or a square wave signal. When the first test signal is a sine wave signal, the main control unit 14 inputs the first test signal to the first shaping unit 102a by controlling the first switch unit 104a and the second switch unit 105a; when the first test signal is a square wave signal, the main control unit 14 inputs the first test signal to the second shaping unit 103a by controlling the first switch unit 104a and the second switch unit 105a. Specifically, the main control unit 14 determines whether the first test signal is a square wave signal. When the first test signal is not a square wave signal, the main control unit 14 outputs a first control signal. When the first test signal is a square wave signal, the main control unit 14 outputs a second control signal. The first switch unit 104a connects the input end of the first switch unit 104a with the first output end of the first switch unit 104a according to the first control signal, and also connects the input end of the first switch unit 104a with the second output end of the first switch unit 104a according to the second control signal. The second switch unit 105a connects the first input terminal of the second switch unit 105a to the output terminal of the second switch unit 105a according to the first control signal, and connects the second input terminal of the second switch unit 105a and the output terminal of the second switch unit 105a according to the second control signal.

[0057] In this embodiment, the second channel unit 11 includes a limiting unit 101b, a first shaping unit 102b, a second shaping unit 103b, a first switch unit 104b and a second switch unit 105b. In this embodiment, the second channel unit 11 has the same structure, connection relationship and working principle as the first channel unit 10, which will not be described in detail.

[0058] In this embodiment, the first test signal and the second test signal are passed through a shaping unit to obtain two groups of square wave signals, and the two groups of square wave signals are input into a logic XOR unit for XOR processing and then a pulse signal is output; the lead and lag relationship between the first test signal and the second test signal is determined by a delay judgment unit and a delay signal is output, so that the main control unit calculates the lead time and lag time of the first test signal and the second test signal according to the delay signal and the pulse width of the pulse signal. The measurement cost is low and can be used in automated production to improve production efficiency.

[0059] See also Figure 2 , Figure 2This is a functional module diagram of an implementation method of the signal delay measurement circuit of the present application. In this embodiment, the first channel unit 10 is taken as an example. The limiting unit 101a includes a first resistor R1a and a first voltage regulator D1a. One end of the first resistor R1a is used to access the first test signal. The cathode of the first voltage regulator D1a is electrically connected to the other end of the first resistor R1a, and the anode of the first voltage regulator D1a is grounded. The other end of the first resistor R1a is also electrically connected to the I / O port crl5 of the main control unit 14. When the amplitude of the first test signal exceeds the first preset value, the first voltage regulator D1a is broken down, and the amplitude of the first test signal is limited to the second preset value. The second preset value is usually the breakdown voltage of the first voltage regulator D1a.

[0060] In this embodiment, the first channel unit 10 may further include a buffer unit 106a. The buffer unit 106a includes a first operational amplifier OA1a. The positive input terminal of the first operational amplifier OA1a is electrically connected to the cathode of the first voltage regulator tube D1a, the negative input terminal of the first operational amplifier OA1a is electrically connected to the output terminal of the first operational amplifier OA1a, and the output terminal of the first operational amplifier OA1a is electrically connected to the input terminal of the first switch unit 104a. The buffer composed of the first operational amplifier OA1a, also known as a voltage follower, has a large input impedance and a small output impedance, and has the functions of isolating and enhancing the driving capability of the subsequent stage while ensuring that the previous stage circuit and the subsequent stage circuit do not affect each other.

[0061] In this embodiment, the first shaping unit 102a includes a second resistor R2a, a first hysteresis comparator OP1a, a third resistor R3a, a fourth resistor R4a, a second voltage regulator diode D2a and a diode D3a. One end of the second resistor R2a is electrically connected to the first output end of the first switch unit 104a. The inverting input end of the first hysteresis comparator OP1a is electrically connected to the other end of the second resistor R2a; one end of the third resistor R3a is electrically connected to the non-inverting input end of the first hysteresis comparator OP1a, and the other end is grounded; one end of the fourth resistor R4a is electrically connected to one end of the third resistor R3a, and the other end is electrically connected to the output end of the first hysteresis comparator OP1a; the cathode of the second voltage regulator diode D2a is electrically connected to the output end of the first hysteresis comparator OP1a, and the anode of the second voltage regulator diode D2a is grounded; the anode of the diode D3a is electrically connected to the output end of the first hysteresis comparator OP1a, and the anode of the diode D3a is electrically connected to the logic XOR unit 12. When the first test signal is a sine wave, the sine wave is input to the inverting input terminal of the first hysteresis comparator OP1a. When the sine wave is in the upper half cycle, the first hysteresis comparator OP1a outputs a low level, and when the sine wave is in the lower half cycle, the first hysteresis comparator OP1a outputs a high level.

[0062] The second shaping unit 103a includes a Schmitt input buffer OA2a. The input end of the Schmitt input buffer OA2a is electrically connected to the first output end of the first switch unit 104a, and is used to receive the first test signal. The output end of the Schmitt input buffer OA2a is electrically connected to the first input end of the first switch unit 104a. The second shaping unit 103a is used to de-jitter and process the signal abnormality of the first test signal.

[0063] The control end of the first switch unit 104a and the control end of the second switch unit 105a are electrically connected to the main control unit 14 to control the I / O ports crl1 and crl2, respectively.

[0064] The internal circuit structure of the second channel unit 11 is the same as that of the first channel unit 10 , and will not be described in detail herein.

[0065] In this embodiment, the delay judgment circuit 13 is a D flip-flop D1. The D flip-flop D1 includes a clock signal input terminal CP, a data input terminal D and a data output terminal Q. The clock signal input terminal CP of the D flip-flop D1 is electrically connected to the output terminal of the second switch unit 105b of the second channel unit 11, the data input terminal D of the D flip-flop D1 is electrically connected to the output terminal of the second switch unit 105a of the first channel unit 10, and the output terminal of the D flip-flop D1 is electrically connected to the main control unit 14. When the first test signal is ahead of the second test signal, the D flip-flop D1 outputs a high level signal; when the first test signal lags behind the second test signal, the D flip-flop D1 outputs a low level signal. The second test signal serves as the clock signal of the D flip-flop D1. When the rising edge of the second test signal arrives, if the D flip-flop D1 outputs a high level, then the first test signal is ahead of the second test signal, such as Figure 3 When the rising edge of the second test signal arrives, if the D flip-flop D1 outputs a low level, the first test signal lags behind the second test signal, as shown in FIG. Figure 4 The logic XOR unit 12 performs XOR processing on the first test signal and the second test signal, and the pulse width of the output pulse signal is the time delay T between the first test signal and the second test signal.

[0066] In this embodiment, the main control unit 14 can also determine that the first test signal is ahead of the second test signal according to the high level, and determine that the first test signal lags behind the second test signal according to the low level. When the pulse signal output by the logical XOR unit 12 reaches the rising edge, the main control unit 14 starts counting; when the falling edge of the pulse signal arrives, the main control unit 14 stops counting and calculates the leading time or lagging time of the first test signal and the second test signal according to the counting. Specifically, the main control unit 14 is built with an edge detection unit 141, a counter 142, a clock 143 and a clock pre-dividing unit 144. By setting the coefficient value of the clock pre-dividing unit 144, the frequency f of the clock 143 is 1MHz, and the bit width of the counter 142 is 16bit. The edge detection unit 141 is set to rising edge detection. When the edge detection unit 141 detects the arrival of the rising edge of the pulse signal, interrupt 1 is triggered, and the counter 142 is initialized, that is, the overflow number n and the count value N are cleared to start counting, and the trigger type of the edge detection unit 141 is changed to falling edge detection. When the edge detection unit 141 detects the arrival of the falling edge of the pulse signal, interrupt 2 is triggered and the counter 142 stops counting.

[0067] at this time

[0068] Wherein, T is the time delay between the first test signal and the second test signal, n is the overflow number of the counter 142 , S is the maximum overflow value of the counter 142 , N is the count value of the counter 142 , and f is the frequency of the clock 143 .

[0069] Compared with the prior art, the signal delay measurement circuit provided in the embodiment of the present application obtains two sets of square wave signals after the first test signal and the second test signal pass through a shaping unit, and inputs the two sets of square wave signals into a logic XOR unit for XOR processing and then outputs a pulse signal; the lead and lag relationship between the first test signal and the second test signal is determined by a delay judgment unit and a delay signal is output, so that the main control unit calculates the lead time and lag time of the first test signal and the second test signal according to the delay signal and the pulse width of the pulse signal. The measurement cost is low and can be used in automated production to improve production efficiency.

[0070] Those skilled in the art should recognize that the above embodiments are only used to illustrate the present application and are not intended to be limiting of the present application. As long as they are within the spirit and scope of the present application, appropriate changes and modifications to the above embodiments are within the scope of protection claimed in the present application.

Claims

1. A signal delay measurement circuit, characterized in that: include: A first channel unit, used for receiving a first test signal, and further used for converting the first test signal into a first square wave signal; A second channel unit, used for receiving a second test signal, and further used for converting the second test signal into a second square wave signal; A logic XOR unit, electrically connected to the first channel unit and the second channel unit, configured to perform XOR processing on the first square wave signal and the second square wave signal and output a pulse signal; a delay determination unit, electrically connected to the first channel unit and the second channel unit, for determining a delay relationship between the first test signal and the second test signal according to the first square wave signal and the second square wave signal, and outputting a delay signal; The main control unit is electrically connected to the logic XOR unit and the delay judgment unit, and is used to calculate the lead time or lag time of the first test signal relative to the second test signal according to the pulse signal and the delay signal.

2. The signal delay measurement circuit according to claim 1, characterized in that: The first channel unit comprises: A limiting unit, electrically connected to the main control unit, for receiving the first test signal, and for limiting the amplitude of the first test signal to a second preset value when the amplitude of the first test signal exceeds a first preset value; A first shaping unit, electrically connected to the limiting unit, the logical XOR unit and the delay determination unit, for converting the first test signal into a square wave signal; A second shaping unit, electrically connected to the limiting unit, the logical XOR unit and the delay judgment unit, for de-jittering and shaping the first test signal; A first switch unit, comprising an input end, a first output end, a second output end and a control end, wherein the input end of the first switch unit is electrically connected to the limiter unit, the first output end of the first switch unit is electrically connected to the first shaping unit, the second output end of the first switch unit is electrically connected to the second shaping unit, and the control end of the first switch unit is electrically connected to the main control unit; The second switch unit includes a first input end, a second input end, an output end and a control end. The first input end of the second switch unit is electrically connected to the first shaping unit, the second input end of the second switch unit is electrically connected to the second shaping unit, the output end of the second switch unit is electrically connected to the logical XOR unit and the delay judgment unit, and the control end of the second switch unit is electrically connected to the main control unit.

3. The signal delay measurement circuit according to claim 2, wherein: The main control unit is further configured to determine whether the first test signal is a square wave signal, and output a first control signal when the first test signal is determined not to be a square wave signal, and output a second control signal when the first test signal is determined to be a square wave signal; The first switch unit is used to connect the input end of the first switch unit and the first output end of the first switch unit according to the first control signal, and to connect the input end of the first switch unit and the second output end of the first switch unit according to the second control signal; The second switch unit is used to connect the first input end of the second switch unit to the output end of the second switch unit according to the first control signal, and to connect the second input end of the second switch unit and the output end of the second switch unit according to the second control signal.

4. The signal delay measurement circuit according to claim 2, wherein: The limiting unit comprises: A first resistor, one end of which is used to receive the first test signal; A first voltage-stabilizer diode, wherein the cathode of the first voltage-stabilizer diode is electrically connected to the other end of the first resistor, and the anode of the first voltage-stabilizer diode is grounded; when the amplitude of the first test signal exceeds the first preset value, the first voltage-stabilizer diode is broken down, and the amplitude of the first test signal is limited to the second preset value.

5. The signal delay measurement circuit according to claim 4, characterized in that: The first channel unit further includes: The buffer unit includes a first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is electrically connected to the cathode of the first voltage regulator tube, the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is electrically connected to the input terminal of the first switch unit.

6. The signal delay measurement circuit according to claim 5, characterized in that: The first shaping unit comprises: a second resistor, one end of which is electrically connected to the first output end of the first switch unit; A first hysteresis comparator, wherein an inverting input terminal of the first hysteresis comparator is electrically connected to the other end of the second resistor; A third resistor, one end of which is electrically connected to the non-inverting input terminal of the first hysteresis comparator, and the other end of which is grounded; a fourth resistor, one end of which is electrically connected to one end of the third resistor, and the other end of which is electrically connected to the output end of the first hysteresis comparator; a second voltage stabilizing diode, wherein a cathode of the second voltage stabilizing diode is electrically connected to an output terminal of the first hysteresis comparator, and an anode of the second voltage stabilizing diode is grounded; A diode, wherein an anode of the diode is electrically connected to the output end of the first hysteresis comparator, and an anode of the diode is electrically connected to the logical XOR unit.

7. The signal delay measurement circuit according to claim 6, wherein: The second shaping unit comprises: A Schmitt input buffer, wherein the input end of the Schmitt input buffer is electrically connected to the first output end of the first switch unit, and the output end of the Schmitt input buffer is electrically connected to the first input end of the second switch unit.

8. The signal delay measurement circuit according to claim 7, wherein: The structure of the second channel unit is the same as that of the first channel unit.

9. The signal delay measurement circuit according to claim 8, characterized in that: The delay determination unit comprises: A D flip-flop comprises a clock signal input terminal, a data input terminal and a data output terminal, wherein the clock signal input terminal of the D flip-flop is electrically connected to the output terminal of the second switch unit of the second channel unit, the data input terminal of the D flip-flop is electrically connected to the output terminal of the second switch unit of the first channel unit, and the output terminal of the D flip-flop is electrically connected to the main control unit; when the first test signal is ahead of the second test signal, the D flip-flop outputs a high level signal; when the first test signal lags behind the second test signal, the D flip-flop outputs a low level signal.

10. The signal delay measurement circuit according to claim 9, characterized in that: The main control unit is also used for: Determine that the first test signal leads the second test signal according to the high level signal, and determine that the first test signal lags behind the second test signal according to the low level signal; When the pulse signal reaches a rising edge, counting starts; when the pulse signal reaches a falling edge, counting stops; and the lead time or lag time of the first test signal and the second test signal is calculated based on the count.

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