Semiconductor structure

Abstract

A semiconductor structure is provided. According to some embodiments of the utility model, the semiconductor structure comprises a substrate and a fin structure which is arranged above the substrate and longitudinally extends along a direction, the fin structure comprises a middle part which is clamped between a first tail end part and a second tail end part along the direction, and a gate structure which is coated above a channel region of the middle part, and a first source / drain feature and a second source / drain feature clamping the channel region of the middle portion in this direction. The middle portion includes a first semiconductor structure, and the first and second end portions include a second semiconductor structure different from the first semiconductor structure.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide semiconductor structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) has decreased. This scale reduction process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scale reduction has also been accompanied by an increase in the complexity of the design and manufacture of the devices that incorporate these ICs, and in order to achieve these advances, similar developments in device manufacturing are needed.

[0003] Neuromorphic computing has been developed to simulate the information processing of the human brain, with the goal of better achieving artificial intelligence. In contrast to traditional intelligence that reduces noise, aspects of neuromorphic computing rely on random noise generation. Some noise generating devices have been developed. Although existing noise generating devices are adequate for their intended purpose, they are not satisfactory in all aspects. Utility Model Content

[0004] Some embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate, a fin structure, a gate structure, and a first source / drain feature and a second source / drain feature. The fin structure is above the substrate and extends longitudinally along a direction, and the fin structure includes a middle portion, and the middle portion is sandwiched between a first end portion and a second end portion along a direction. The gate structure is coated above the channel region of the middle portion. The first source / drain feature and the second source / drain feature sandwich the channel region of the middle portion along this direction, the middle portion includes a first semiconductor structure, and the first end portion and the second end portion include a second semiconductor structure different from the first semiconductor structure.

[0005] Some embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate of a first semiconductor structure, a fin structure, a first gate structure, a second gate structure, a third gate structure, a first source / drain feature, and a second source / drain feature. The fin structure is above the substrate, and the fin structure includes a middle portion, a first end portion, and a second end portion. The middle portion is formed by the first semiconductor structure. The first end portion and the second end portion clamp the middle portion along this direction and are formed by a second semiconductor structure different from the first semiconductor structure. The first gate structure is coated above the channel region of the middle portion. The second gate structure is coated above the first end portion. The third gate structure is coated above the second end portion. The first source / drain feature and the second source / drain feature clamp the channel region of the middle portion along this direction.

[0006] Some embodiments of the present disclosure provide a semiconductor structure, including a substrate, a fin structure, a gate structure, a first source / drain feature, and a second source / drain feature. The fin structure is above the substrate and extends longitudinally along this direction, and the fin structure includes a middle portion, and the middle portion is sandwiched between a first end portion and a second end portion along this direction, wherein the channel region of the middle portion is wavy in a top view. The gate structure is coated above the channel region of the middle portion. The first source / drain feature and the second source / drain feature sandwich the channel region of the middle portion along this direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some embodiments of the present invention are described in detail in the accompanying drawings. Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flowchart of a method for manufacturing a semiconductor device on a workpiece according to some embodiments of the present invention;

[0009] Figures 2 to 22 According to some embodiments of the present invention, the workpiece is in Figure 1 A partial cross-sectional view or a top view of each step of the method.

[0010]

Explanation of symbols

[0011] 100: Method

[0012] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124: Blocks

[0013] 200: Workpiece / Semiconductor Structure

[0014] 202:Substrate

[0015] 204: Hard Mask Layer

[0016] 206: Bottom layer

[0017] 208: Middle layer

[0018] 210: Photosensitive layer

[0019] 211: Groove-shaped opening

[0020] 212: Groove

[0021] 214: Second semiconductor structure

[0022] 216: Buffer semiconductor layer

[0023] 218:Semiconductor lining

[0024] 220: Fin structure

[0025] 220C: Channel area

[0026] 220E: terminal part

[0027] 220M: Middle part

[0028] 220SD: Source / Drain Region

[0029] 222: Isolation Features

[0030] 226:Dummy Gate Stack

[0031] 228: Protective dummy gate stack

[0032] 230: Gate spacer

[0033] 232: Source / drain groove

[0034] 234: Source / Drain Characteristics

[0035] 236: Contact etching stop layer

[0036] 238: Interlayer dielectric layer

[0037] 240: Gate dielectric layer

[0038] 242: Gate electrode layer

[0039] 250: first gate structure

[0040] 252: Second gate structure

[0041] 260: Etching stop layer

[0042] 262: Top interlayer dielectric layer

[0043] 268: Silicate Characteristics

[0044] 270: Source / drain contact

[0045] 272: Gate contact through hole

[0046] 274: Source / drain contact via

[0047] D: Depth

[0048] L: Distance

[0049] W: Width

[0050] X: X direction

[0051] Y: Y direction

[0052] Z: Z direction

[0053] A-A': Line AA'

[0054] B-B': Line BB'

[0055] C-C': Line CC' DETAILED DESCRIPTION

[0056] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0057] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0058] In addition, when a number or a series of numbers is described using "about," "approximately," and the like, the term is intended to encompass numbers within a reasonable range, taking into account variations that occur inherently during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number, a number or range of numbers encompasses a reasonable range including the described number, such as within + / -10% of the described number. For example, a material layer having a thickness of "about 5 nanometers" may encompass dimensions from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerance associated with the deposited material layer is + / -15% known to those of ordinary skill in the art. Still further, the present invention may repeat reference numbers and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0059] Artificial intelligence (AI) is a field that enables machines to learn from experience, adapt to new inputs, and perform human-like tasks. Conventional computers are able to store and process large amounts of data. However, everyday tasks present problems that conventional computers cannot solve. For example, identifying objects and predicting events in a dynamic natural environment involves dealing with interference and learning quickly from a limited set of examples. For such everyday tasks, biological brains, such as the human brain, are far superior to conventional computers, especially in terms of energy consumption. Recognizing a face requires only a small amount of human effort, while doing so requires a conventional computer to identify the features of the face and compare these features to the features of faces in a large database. To compensate for the shortcomings of conventional computers, neuromorphic computing has emerged, in which AI tasks are performed by specialized brain-like computers.

[0060] To advance neuromorphic computing, computer scientists turned to neuroscientists for help. Neuroscientists have long been able to record the neural responses of animals to stimuli. They were surprised to find that neural responses to repeated stimulation varied greatly. Spontaneous neuronal activity was observed even in the absence of any stimulation. These fluctuations and spontaneous activity were found to be random and were once considered noise. This view has changed dramatically over the past decade or so. This noise, which may be generated in the cerebral cortex, was found to be related to arousal and stress, which can enhance perception and sensory function. These findings led to a probabilistic approach based on random systems. Random systems require completely random sources of noise in order to enhance the system's response to input signals.

[0061] Some embodiments of the present invention provide a noisy semiconductor device and a method for forming the same. Instead of forming a complex semiconductor structure of various geometric shapes, some embodiments of the present invention utilize a swinging fin structure formed by stress from a heterogeneous semiconductor structure. In an example, at least two regions of a second semiconductor structure are formed in a substrate of a first semiconductor structure so that a portion of the substrate is sandwiched between at least two regions of the second semiconductor structure. The fin structure is patterned from the two regions and the substrate to have a middle portion sandwiched between two end portions. The middle portion is formed by the first semiconductor structure and the two end portions are formed by the second semiconductor structure. When the first semiconductor structure is silicon (Si) and the second semiconductor structure is silicon germanium (SiGe), the two end portions apply compressive stress to the middle portion. When the fin structure is formed, the compressive stress may cause the middle portion to deform to form a swinging fin structure. After a gate structure is formed above the swinging fin structure, a noise transistor for generating random noise is formed. The process for forming the noise device of some embodiments of the present invention is highly integrated with the existing field effect transistor (FET) manufacturing process.

[0062] The various aspects of some embodiments of the present invention will now be described in more detail with reference to the drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 of forming a self-powered image sensor according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the present invention to what is explicitly illustrated in method 100. Additional steps may be provided before, during, and after method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figures 2 to 22 Describing the operation of method 100, Figures 2 to 22 1 is a partial cross-sectional view or a top view of the workpiece 200 at different manufacturing stages. Because the workpiece 200 will be manufactured into a semiconductor device at the end of the operation of the method 100, the workpiece 200 may also be referred to as a semiconductor structure 200 according to the context. In addition, throughout this application, unless otherwise specified, the same reference numerals represent the same features. The X, Y, and Z directions are Figures 2 to 22 Use consistent and perpendicular to each other.

[0063] refer to Figure 1 , Figure 2 and Figure 3 , the method 100 includes block 102, wherein a trench 212 is formed on a substrate 202. Figure 2 The substrate 202 includes or is formed of a first semiconductor structure different from the second semiconductor structure 214 (hereinafter referred to as block 104 and Figure 4). The first semiconductor structure and the second semiconductor structure 214 are selected so that when the second semiconductor structure 214 is epitaxially grown on the first semiconductor structure, compressive stress is applied to the first semiconductor structure due to lattice mismatch. In other words, the lattice constant of the second semiconductor structure 214 is greater than the lattice constant of the first semiconductor structure. In the depicted embodiment, the substrate 202 is formed of silicon (Si) and the second semiconductor structure 214 is formed of silicon germanium (SiGe). In some examples, the second semiconductor structure 214 has a germanium content between about 40% and about 95%. This range of germanium content is not insignificant. When the germanium content in the second semiconductor structure 214 is less than 40%, the second semiconductor structure 214 may not apply sufficient stress to the substrate 202 to achieve the intended purpose of some embodiments of the present utility model. When the germanium content in the second semiconductor structure 214 is greater than 95%, the lattice mismatch between the first semiconductor structure and the second semiconductor structure 214 may be too large. Such a large lattice mismatch may result in excessive voids or dislocation defects at the interface between the first semiconductor structure and the second semiconductor structure 214, thereby preventing the mechanical transfer of compressive stress.

[0064] Still reference Figure 2 To perform the operations at block 104, a hard mask layer 204 is deposited over the substrate 202 and a photoresist is formed over the hard mask layer. In some embodiments, the hard mask layer 204 may include a dielectric material such as silicon oxide or silicon nitride. As will be further described below, the composition of the hard mask layer 204 makes it less likely that a semiconductor material will be epitaxially formed on the hard mask layer 204. Figure 2 The photoresist shown in is a multi-layer photoresist, including a bottom layer 206 on the hard mask layer 204, an intermediate layer 208 on the bottom layer 206, and a photosensitive layer 210 on the intermediate layer 208. In some implementations, the bottom layer 206 may be a carbon-containing layer including carbon (C), hydrogen (H), and oxygen (O). The intermediate layer 208 may be a silicon-containing layer including silicon (Si), hydrogen (H), and oxygen (O). The photosensitive layer 210 may include a polymer, a photosensitizer, and a solvent. In order to form grooves on the substrate 202, an optical lithography process is performed to pattern the photosensitive layer 210. As shown in FIG. Figure 2 As shown in FIG. 2 , two groove-shaped openings 211 are formed in the photosensitive layer 210 . Each of the groove-shaped openings 211 is elongated along the X direction. The groove-shaped openings 211 expose a portion of the intermediate layer 208 .

[0065] refer to Figure 3 , the patterned photosensitive layer 210 is used as an etching mask to etch the intermediate layer 208, the bottom layer 206, the hard mask layer 204, and the substrate 202. In some embodiments, the etching process at block 102 may be a dry etching process. Figure 3 As shown in Figure 2The groove-shaped opening 211 in the substrate 202 partially extends into the substrate 202 to form a groove 212. Figure 3 In the embodiment shown in , the grooves 212 are spaced apart from each other by a distance L along the Y direction. Each of the grooves 212 has a width W along the Y direction. Along the Z direction, each of the grooves 212 extends a depth D into the substrate 202. In some cases, the distance L may be between 100 nanometers and about 2000 nanometers, the width W may be between about 50 nanometers and about 1000 nanometers, and the depth D may be between about 30 nanometers and about 200 nanometers. As will be further described below, these ranges are not trivial. The distance L is related to the channel length of the fin structure, which is designed to have a swinging or wavy shape due to compressive stress. When the distance L is less than 100 nanometers, the formed fin may not have space to form the desired swinging shape. When the distance L is greater than 2000 μm, the formed fin may not be subjected to sufficient stress to deform. The stress applied by the second semiconductor structure 214 in the groove 212 can be dissipated along the Y direction. When the width W is less than 50 nanometers, the second semiconductor structure 214 may not apply sufficient stress. When the width W is greater than 1000 nanometers, the second semiconductor structure 214 may occupy too much device area. The depth D of the trench 212 is related to the epitaxial quality of the second semiconductor structure 214 and the height of the fin. When the depth D is greater than 200 nanometers, the quality of the second semiconductor structure 214 may be affected. When the depth D is less than 30 nanometers, the on-current may be insufficient and the swing may not be sufficient to generate noise. After forming the trench 212, the bottom layer 206 and the middle layer 208 are removed by ashing or selective etching. Figure 2 As shown in FIG. 2 , after the bottom layer 206 and the middle layer 208 are removed, the hard mask layer 204 remains on the substrate 202 , and the trenches 212 also extend through the hard mask layer 204 .

[0066] refer to Figure 1 , Figure 4 and Figure 5 , the method 100 includes block 104, wherein a second semiconductor structure 214 is deposited over the trench 212. With the trench 212 defined in the hard mask layer 204 and the substrate 202, the second semiconductor structure 214 is epitaxially and selectively grown over the trench 212. As described above, the hard mask layer 204 is formed of a dielectric material that does not provide a suitable surface for epitaxial growth of semiconductor materials. In some embodiments, the second semiconductor structure 214 includes silicon germanium (SiGe). In these embodiments, the second semiconductor structure 214 is grown using a silicon-containing gas (e.g., SiH 4 、Si 2 H 6 、SiH 2 Cl 2 ), germanium-containing gases (e.g., GeH 4 Or Ge2 H 6 ), and combinations thereof, and reactants / carrier gases (such as H 2 、N 2 , or Ar, or a combination thereof) is epitaxially grown on the exposed surface of substrate 202 (in trench 212) at a temperature between about 550°C and about 700°C. Figure 4 As shown in FIG, although the second semiconductor structure 214 is unlikely to be deposited on the hard mask layer 204, the overgrowth of the second semiconductor structure 214 may extend laterally to cover a portion of the top surface of the hard mask layer 204. It can be seen that at block 104, the hard mask layer 204 acts as a deposition mask.

[0067] refer to Figure 5 After depositing the second semiconductor structure 214 over the trench 212, the workpiece 200 is planarized to remove the hard mask layer 204 and portions of the second semiconductor structure 214 and the substrate 202, thereby forming a planar top surface. In some embodiments, the workpiece 200 is planarized using a chemical mechanical polishing (CMP) process.

[0068] refer to Figure 1 and Figure 6 , the method 100 includes block 106, wherein a buffer semiconductor layer 216 is deposited over the substrate 202. The buffer semiconductor layer 216 may include silicon (Si) to provide a more uniform top-facing surface when the workpiece 200 is patterned to form the fin structure 220. Generally, when the second semiconductor structure 214 is formed of silicon germanium (SiGe) and the substrate 202 is formed of silicon (Si), the etching rate of the second semiconductor structure 214 is greater than the etching rate of the substrate 202 in most anisotropic etching processes. To prevent uneven etching, the buffer semiconductor layer 216 is formed over the substrate 202, including over the second semiconductor structure 214, to provide uniform etching characteristics in a subsequent anisotropic etching process. The buffer semiconductor layer 216 is epitaxially grown on the workpiece 200. In an example process, a source gas of silane (SiH 4 ), silicon tetrachloride (SiCl 4 ), trichlorosilane (TCS), dichlorosilane (SiH 2 Cl 2 or DSC), or hydrogen (H 2 ) epitaxially grows a buffer semiconductor layer 216 on the planar surface of the workpiece 200. The deposition temperature of the buffer semiconductor layer 216 may be between about 700° C. and about 1250° C. In some embodiments, the buffer semiconductor layer 216 may optionally be subjected to an annealing process using radiation heating at a temperature between about 800° C. and about 1050° C. to improve its quality.

[0069] refer to Figure 1 and Figures 7 to 10 , the method 100 includes a block 108, wherein the substrate 202 is patterned to form a fin structure 220, the fin structure 220 having a middle portion 220M sandwiched between two end portions 220E along the Y direction. To form the fin structure 220, a fin top hard mask layer (not explicitly shown in the figure) may be deposited over the buffer semiconductor layer 216. The fin top hard mask layer may be a single layer or multiple layers. When the fin top hard mask layer is multiple layers, it may include a first hard mask layer and a second hard mask layer on the first hard mask layer. The first hard mask layer and the second hard mask layer have different compositions. In some embodiments, the first hard mask layer is formed of silicon oxide and the second hard mask layer is formed of silicon nitride. In some implementations, a combination of deposition, lithography, and / or etching processes are performed to define the fin structure 220. The etching process may include a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof.

[0070] like Figure 7 The cross-sectional view and Fig.10 As shown in the top view in FIG. 2 , the fin structure 220 includes a middle portion 220M and two end portions 220E. The middle portion 220M is sandwiched between the two end portions 220E along the Y direction. Since the second semiconductor structure 214 is formed in the trench 212, the middle portion 220M includes silicon (Si) because both the substrate 202 and the buffer semiconductor layer 216 are formed of silicon (Si). Since the second semiconductor structure 214 includes silicon germanium (SiGe) and the buffer semiconductor layer 216 is formed of silicon (Si), the two end portions 220E of the fin structure 220 can be mainly formed of silicon germanium (SiGe). Figure 7 The partial cross-sectional views along lines AA', BB' and CC' in FIG. 2 better illustrate the structure of the middle portion 220M and the two end portions 220E. Figure 7 As shown in FIG. 2 , line AA′ cuts through the end portion 220E on the left side, line BB′ cuts through the middle portion 220M, and line CC′ cuts through the end portion 220E on the right side. Figure 8 A partial cross-sectional view across line AA' or line CC' is shown. Fig. 9 A partial cross-sectional view across line BB' is shown. Figure 8 , each of the two end portions 220E includes a fin segment patterned from the second semiconductor structure 214 and the overlying buffer semiconductor layer 216. Fig. 9 , the middle portion 220M includes fin segments patterned from the substrate 202 and the overlying buffer semiconductor layer 216 .

[0071] Reference now Fig.10 As described above, the lattice mismatch between the first semiconductor structure and the second semiconductor structure 214 of the substrate 202 induces compressive stress in the portion between the two second semiconductor structures 214 of the substrate 202. Before the fin structure 220 is formed at block 108, the stress is insufficient to deform the portion between the two filled trenches 212 of the substrate 202. However, as Fig.10 As shown in FIG. 2 , after the fin structure 220 is formed, the middle portion 220M may yield to the compressive stress applied by the two end portions 220E and exhibit deformation in the form of swinging. Figure 3 The distance L between the grooves 212 shown in FIG. 1 is directly related to the length of the middle portion 220M, and the deformation may be slight or significant. In general, the middle portion 220M with a greater distance L may exhibit more sway. Fig.10 As shown in , the middle portion 220M may be characterized as a wobbled fin section or a wavy fin section. Although the amount of wobbling is related to the distance L, variations in material uniformity, thermal history, and process may make the amount of wobbling random and unpredictable. Because the amount of wobbling is directly related to noise, the unpredictable wobbling of the middle portion 220M may result in completely random noise in the resulting device. Fig.10 It also shows how the trench 212 and the second semiconductor structure 214 extend longitudinally along the X-direction.

[0072] refer to Figure 1 and Figures 11 to 13 The method 100 includes a block 110, wherein a semiconductor liner 218 is formed over the substrate 202, including over the fin structure 220. The semiconductor liner 218 is used to protect the sidewalls of the second semiconductor structure 214 in the end portion 220E during a subsequent etch-back process. In some embodiments, the semiconductor liner 218 includes silicon (Si) and is formed using a silane (SiH 4 ), silicon tetrachloride (SiCl 4 ), trichlorosilane (TCS), or dichlorosilane (SiH 2 Cl 2 or DSC) and source gases such as hydrogen (H 2 ) is epitaxially deposited on the surfaces of substrate 202 and fin structure 220. In some cases, semiconductor liner 218 may have a thickness between about 0.5 nanometers and about 5 nanometers. The deposition temperature of semiconductor liner 218 may be in the range of about 700° C. to about 1250° C., depending on the gas used. Figures 11 to 13As shown in , the semiconductor liner 218 is disposed over the top surface and sidewalls of the fin structure 220 and the top surface of the substrate 202. It should be noted that because the buffer semiconductor layer 216 above the fin structure 220 has not been removed, a portion of the semiconductor liner 218 is directly disposed on the top surface of the buffer semiconductor layer 216. In other words, in the end portion 220E, the top portion of the semiconductor liner 218 is spaced apart from the top surface of the second semiconductor structure 214 by the buffer semiconductor layer 216. In some embodiments, the semiconductor liner 218 may optionally be subjected to an annealing process using radiation heating at a temperature between about 800° C. and about 1050° C. to improve its quality.

[0073] refer to Figure 1 , Fig.14 and Fig.15 , the method 100 includes block 112, where an isolation feature 222 is formed around the fin structure 220. Fig.14 and Fig.15 As shown in , the isolation feature 222 isolates the fin structure 220 (including the middle portion 220M and the end portion 220E) from another fin structure (omitted for simplicity). In the example process, a dielectric material is first deposited flatly over the workpiece 200 to fill the space between the fin structure 220 and the other fin structure. The dielectric material may include silicon oxide, silicon oxynitride, other suitable isolation materials, or a combination thereof, and may be deposited by a chemical vapor deposition (CVD) or spin-on-glass (SOG) process. A planarization process such as a CMP process is then performed until the semiconductor liner 218 is exposed. The planarized dielectric material is then selectively etched back to form the isolation feature 222. It can be seen that the semiconductor liner 218 protects the second semiconductor structure 214 in the end portion 220E during the etch-back process. Although Fig.14 and Fig.15 Although not explicitly shown in FIG. 2 , a portion of the semiconductor liner 218 may be removed or etched during the planarization and etch-back processes.

[0074] refer to Figure 1 , Fig.16 and Fig.17, the method 100 includes a block 114, wherein a dummy gate stack is formed over the channel region 220C of the middle portion 220M and the two end portions 220E. In the depicted embodiment, a replacement gate process is employed, wherein the dummy gate stack is formed as a reserve position to undergo a process that is harmful to the metal gate structure, and the dummy gate stack is replaced with a functional metal gate structure. In some embodiments of the present invention, the dummy gate stack is also used to protect the second semiconductor structure 214 in the fin structure 220. When the dummy gate stack is not formed to cover the second semiconductor structure 214 in the end portions, the second semiconductor structure 214 may suffer significant loss during the recessing of the source / drain region, resulting in stress loss. This is undesirable because the second semiconductor structure 214 acts as a stress source, and the substantial loss of the stress source inevitably leads to a loss of stress. In the depicted embodiment, the dummy gate stack formed at block 114 includes a dummy gate stack 226 above the channel region 220C of the middle portion 220M and two protective dummy gate stacks 228 above the entire length (along the Y direction) of the end portion 220E. The dummy gate stack 226 serves as a placeholder gate, while the protective dummy gate stack 228 covers and protects the second semiconductor structure 214. The dummy gate stack 226 and the protective dummy gate stack 228 can be formed simultaneously. In an example process, a dummy gate dielectric layer is first formed on the fin structure 220 using thermal oxidation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), and a dummy electrode layer is formed on the dummy gate dielectric layer using CVD. In some embodiments, the dummy electrode layer includes polysilicon. After the dummy gate dielectric layer and the dummy electrode layer are deposited, they are patterned to form the dummy gate stack 226 and the protective dummy gate stack 228.

[0075] After forming the dummy gate stack, at least one gate spacer 230 may be deposited over the dummy gate stack (including the dummy gate stack 226 and the protective dummy gate stack 228). Fig.18 ). The at least one gate spacer 230 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0076] refer to Figure 1 and Fig.18 , the method 100 includes a block 116, wherein the source / drain region 220SD of the middle portion 220M is recessed. In some embodiments, the source / drain region 220SD of the middle portion 220M is anisotropically etched using dry etching or a suitable etching process to form the source / drain recess 232. For example, the dry etching process may be performed by oxygen (O 2), oxygen-containing gases, fluorine-containing gases (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and / or C 2 F 6 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 , and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gas, other suitable gas and / or plasma, and / or a combination thereof. Fig.18 As shown in , after forming the source / drain recesses 232 , at least one gate spacer 230 may remain disposed along the sidewalls of the dummy gate stack 226 and the protective dummy gate stack 228 .

[0077] refer to Figure 1 and Fig.19 , the method 100 includes a block 118, wherein a source / drain feature 234 is formed over the source / drain region 220SD. At block 118, the source / drain feature 234 is formed over the source / drain recess 232 in the source / drain region 220SD using an epitaxy process. The epitaxy process may implement a CVD deposition technique (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy (MBE), other suitable selective epitaxial growth (SEG) processes, or a combination thereof. The source / drain feature 234 may be n-type or p-type. When the source / drain feature 234 is p-type, it includes silicon germanium (SiGe) and a p-type dopant, such as boron (B). When the source / drain feature 234 is n-type, it includes silicon (Si) and an n-type dopant, such as phosphorus (P). In the depicted embodiment, the source / drain feature 234 is n-type. After forming the source / drain feature 234, an annealing process may be performed to activate the dopant in the source / drain feature 234.

[0078] refer to Figure 1 and Fig. 20The method 100 includes block 120, wherein a contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are formed over the source / drain features 234. Fig. 20 As shown in FIG. 1 , a CESL 236 is formed on the source / drain features 234, and an ILD layer 238 is formed on the CESL 236. The ILD layer 238 is separated from the at least one gate spacer 230 by the CESL 236. In some embodiments, the CESL 236 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 236 can be deposited using an ALD, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The ILD layer 238 is then deposited over the CESL 236. In some embodiments, the ILD layer 238 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicon glass, or doped silicon oxide materials such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borophosilicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 238 can be deposited by a spin-on coating process, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 238, the workpiece 200 may be annealed to improve the integrity of the ILD layer 238. Fig. 20 After depositing the ILD layer 238, the workpiece 200 is planarized to expose the dummy gate stack 226 and the protective dummy gate stack 228. At the end of the planarization process, the top surfaces of the ILD layer 238, CESL 236, dummy gate stack 226, and protective dummy gate stack 228 are coplanar.

[0079] refer to Figure 1 and Fig.21, method 100 includes block 122, wherein the dummy gate stack is replaced with a gate structure. At block 122, a gate replacement operation is performed to replace the dummy gate stack (including the dummy gate stack 226 and the protective dummy gate stack 228) with a metal gate structure (including the first gate structure 250 and the two second gate structures 252). First, the dummy gate stack (including the dummy gate stack 226 and the protective dummy gate stack 228) is removed to form a gate trench. The channel region 220C of the end portion 220E and the middle portion 220M is exposed in the gate trench. Next, the first gate structure 250 and the two second gate structures 252 are deposited in the gate trench. In some embodiments, each of the first gate structure 250 and the second gate structure 252 may include a gate dielectric layer 240 and a gate electrode layer 242 above the gate dielectric layer 240. In some implementations, the gate dielectric layer 240 may include a silicon oxide interface layer and a high-k dielectric layer. The high-k dielectric layer is formed of a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable components, or combinations thereof. In some implementations, the high-k dielectric layer may include, for example, HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 , HfO 2 -Al 2 O 3 、TiO 2 、 2 O 5 ,La 2 O 3 , Y 2 O 3 , other suitable high-k dielectric materials, or combinations thereof. The gate electrode layer 242 includes a conductive material. In some implementations, the gate electrode layer 242 includes multiple layers, such as one or more capping layers, work function layers, adhesive / barrier layers, and / or metal fill (or body) layers. The capping layer may include a material that prevents or eliminates diffusion and / or reaction of components between the gate dielectric layer 240 and other layers of the gate electrode layer 242. In some implementations, the capping layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like. 2 N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or a combination thereof. The work function layer includes a conductive material tuned to have a desired work function (such as an n-type work function or a p-type work function), such as an n-type work function material and / or a p-type work function material. The p-type work function material includes TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 、MoSi2 、TaSi 2 、NiSi 2 , WN, other p-type work function materials, or combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. The bonding / barrier layer may include a material that promotes adhesion between adjacent layers, such as a work function layer and a metal fill layer, and / or a material that blocks and / or reduces diffusion between gate layers, such as a work function layer and a metal fill layer. For example, the bonding / barrier layer includes a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), a metal oxide, a metal nitride (e.g., TiN), or combinations thereof. The metal fill layer may include a suitable conductive material, such as W or Cu. In the depicted embodiment, the gate dielectric layer 240 includes silicon oxide and hafnium oxide, and the gate electrode layer 242 includes TiN, TiAl, and tungsten. As Fig.21 As shown in , a planarization process such as CMP is performed to remove excess material.

[0080] refer to Figure 1 and Fig. 22 , method 100 includes block 124, where further processing is performed. Such further processing may include, for example, forming source / drain contacts 270, depositing an etch stop layer (ESL) 260, depositing a top interlayer dielectric (ILD) layer 262, forming gate contact vias 272, and forming source / drain contact vias 274. In some embodiments, each of source / drain contacts 270 extends through CESL 236 and ILD layer 238 ( Fig.21 ) and contact the source / drain features 234 by way of silicide features 268. In some embodiments, the source / drain contacts 270 may include ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The silicide features 268 may include titanium silicide. Although not explicitly shown in the figures, each of the source / drain contacts 270 is separated from the ILD layer 238 by a barrier layer, which may include titanium nitride (TiN) or tantalum nitride (TaN). The ESL 260 may have a composition similar to that of the CESL 236, and the top ILD layer 262 may have a composition similar to that of the ILD layer 238. As shown in FIG. Fig. 22As shown in , the gate contact via 272 extends through the ESL 260 and the top ILD layer 262 to contact the first gate structure 250. The source / drain contact vias 274 extend through the ESL 260 and the top ILD layer 262 to contact the source / drain contacts 270. In some cases, the gate contact via 272 and the source / drain contact vias 274 may include titanium nitride (TiN), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The source / drain contact vias 274 are shown in dashed lines because they are out of the plane of the gate contact via 272 or the first gate structure 250. In Fig. 22 In some embodiments shown in , the second gate structure 252 is not electrically connected to any conductive contact and is electrically floating.

[0081] Some embodiments of the present invention provide a noisy semiconductor structure and a method for forming the same. In one embodiment, a semiconductor structure is provided. The semiconductor structure includes a substrate; a fin structure extending longitudinally along a direction above the substrate, the fin structure including a middle portion sandwiched between a first end portion and a second end portion along the direction; a gate structure covering a channel region of the middle portion; and a first source / drain feature and a second source / drain feature of the channel region sandwiching the middle portion along the direction. The middle portion includes a first semiconductor structure, and the first end portion and the second end portion include a second semiconductor structure different from the first semiconductor structure.

[0082] In some embodiments, the first end portion and the second end portion apply compressive stress to the middle portion along this direction. In some implementations, the first semiconductor structure includes silicon (Si) and the second semiconductor structure includes silicon germanium (SiGe). In some embodiments, the second semiconductor structure includes a germanium content between about 40% and about 95%. In some cases, the semiconductor structure further includes a buffer semiconductor layer disposed on the top surface of the channel region of the middle portion, the first end portion, and the second end portion. In some embodiments, the buffer semiconductor layer includes silicon (Si). In some implementations, the semiconductor structure further includes a semiconductor liner disposed above the buffer semiconductor layer and the sidewalls of the channel region of the middle portion, the first end portion, and the second end portion. In some cases, the semiconductor liner includes silicon (Si). In some embodiments, the channel region of the middle portion is wavy in a top view.

[0083] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes a substrate of a first semiconductor structure; a fin structure above the substrate and including a middle portion formed by the first semiconductor structure and a first end portion and a second end portion formed by a second semiconductor structure different from the first semiconductor structure and sandwiching the middle portion along a direction; a first gate structure covering a channel region of the middle portion; a second gate structure covering the first end portion; a third gate structure covering the second end portion; and a first source / drain feature and a second source / drain feature of the channel region sandwiching the middle portion along the direction.

[0084] In some embodiments, the first semiconductor structure includes silicon (Si), and the second semiconductor structure includes silicon germanium (SiGe). In some implementations, the first gate structure includes a first gate dielectric layer coated over the channel region of the middle portion and a first gate electrode coated over the first gate dielectric layer; the second gate structure includes a second gate dielectric layer coated over the first end portion and a second gate electrode coated over the second gate dielectric layer; the third gate structure includes a third gate dielectric layer coated over the second end portion and a third gate electrode coated over the third gate dielectric layer. The composition of the first gate dielectric layer, the composition of the second gate dielectric layer, and the composition of the third gate dielectric layer are the same. The composition of the first gate electrode, the composition of the second gate electrode, and the composition of the third gate electrode are the same. In some embodiments, the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, or a combination thereof, and the first gate electrode, the second gate electrode, and the third gate electrode include titanium nitride, titanium aluminum, titanium aluminum carbide, titanium aluminum nitride, or tungsten. In some embodiments, the first source / drain feature contacts the first end portion, and the second source / drain feature contacts the second end portion. In some embodiments, the first end portion and the second end portion apply compressive stress to the middle portion along this direction.

[0085] In still another embodiment, a method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer on a substrate of a first semiconductor structure, forming a first trench and a second trench in the substrate and the hard mask, the first trench and the second trench extending longitudinally along a first direction, epitaxially depositing a second semiconductor structure over the first trench and the second trench, patterning the substrate to form a fin structure extending longitudinally along a second direction perpendicular to the first direction, so that the fin structure has a middle portion formed by the first semiconductor structure and a first end portion and a second end portion formed by the second semiconductor structure, forming a first dummy gate stack over a channel region of the middle portion, forming a second dummy gate stack over the first end portion, and forming a third dummy gate stack over the second end portion, recessing a source / drain region of the middle portion to form two source / drain recesses adjacent to the end portion of the channel region, forming source / drain features in the two source / drain recesses, and replacing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack with the first gate structure, the second gate structure, and the third gate structure, respectively. The second semiconductor structure is different from the first semiconductor structure.

[0086] In some embodiments, the first semiconductor structure includes silicon (Si) and the second semiconductor structure includes silicon germanium (SiGe). In some implementations, the method further includes planarizing the substrate and the second semiconductor structure after epitaxially depositing the second semiconductor structure over the first trench and the second trench until the hard mask layer is removed. In some embodiments, the method further includes depositing a buffer semiconductor layer over the substrate and the second semiconductor structure after planarizing the substrate and the second semiconductor structure. In some cases, the method further includes depositing a semiconductor liner over the buffer semiconductor layer and the fin structure after patterning the substrate to form the fin structure.

[0087] In another embodiment, a semiconductor structure is provided, comprising a substrate, a fin structure, a gate structure, a first source / drain feature, and a second source / drain feature. The fin structure is above the substrate and extends longitudinally along this direction, and the fin structure includes a middle portion, and the middle portion is sandwiched between the first end portion and the second end portion along this direction, wherein the channel region of the middle portion is wavy in a top view. The gate structure is coated above the channel region of the middle portion. The first source / drain feature and the second source / drain feature sandwich the channel region of the middle portion along this direction.

[0088] In some embodiments, the gate structure includes a first gate structure, a second gate structure, and a third gate structure. The first gate structure is coated over the channel region of the middle portion. The second gate structure is coated over the first end portion. The third gate structure is coated over the second end portion. In some embodiments, the semiconductor structure further includes: a buffer semiconductor layer disposed on multiple top surfaces of the channel region of the middle portion, the first end portion, and the second end portion. In some embodiments, the semiconductor structure further includes: a semiconductor liner disposed over the buffer semiconductor layer and multiple sidewalls of the channel region of the middle portion, the first end portion, and the second end portion.

[0089] The foregoing summarizes the features of several embodiments. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: Include: a substrate; a fin structure, which is above the substrate and extends longitudinally along a direction, the fin structure comprising a middle portion, the middle portion being sandwiched between a first end portion and a second end portion along the direction; a gate structure covering a channel region of the middle portion; and a first source / drain feature and a second source / drain feature, sandwiching the channel region of the middle portion along the direction, The middle portion includes a first semiconductor structure, and the first end portion and the second end portion include a second semiconductor structure different from the first semiconductor structure.

2. The semiconductor structure according to claim 1, wherein: Further including: A buffer semiconductor layer is disposed on the channel region of the middle portion, the first end portion and the top surfaces of the second end portion.

3. The semiconductor structure according to claim 2, wherein: Further including: A semiconductor liner is disposed on the buffer semiconductor layer and the channel region of the middle portion, the first end portion and the sidewalls of the second end portion.

4. The semiconductor structure according to claim 1, wherein: The channel area of ​​the middle portion is wavy in a top view.

5. A semiconductor structure, characterized in that: Include: A substrate of a first semiconductor structure; A fin structure is provided above the substrate, the fin structure comprising: a middle portion formed by the first semiconductor structure, and A first end portion and a second end portion sandwich the middle portion along a direction and are formed of a second semiconductor structure different from the first semiconductor structure; a first gate structure covering a channel region of the middle portion; a second gate structure covering the first end portion; a third gate structure covering the second end portion; and A first source / drain feature and a second source / drain feature sandwich the channel region of the middle portion along the direction.

6. The semiconductor structure according to claim 5, characterized in that wherein the first source / drain feature contacts the first end portion, Wherein the second source / drain feature contacts the second end portion.

7. A semiconductor structure, characterized in that: Include: a substrate; a fin structure extending longitudinally along a direction above the substrate, the fin structure comprising a middle portion sandwiched between a first end portion and a second end portion along the direction, wherein a channel region of the middle portion is wavy in a top view; a gate structure covering the channel region of the middle portion; and A first source / drain feature and a second source / drain feature sandwich the channel region of the middle portion along the direction.

8. The semiconductor structure according to claim 7, wherein: The gate structure comprises: a first gate structure covering the channel region of the middle portion; a second gate structure covering the first end portion; and A third gate structure is coated on the second end portion.

9. The semiconductor structure according to claim 7, wherein: Further including: A buffer semiconductor layer is disposed on the channel region of the middle portion, the first end portion and the top surfaces of the second end portion.

10. The semiconductor structure according to claim 9, wherein: Further including: A semiconductor liner is disposed on the buffer semiconductor layer and the channel region of the middle portion, the first end portion and the sidewalls of the second end portion.

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