Silicon carbide MOSFET device

Abstract

The utility model discloses a silicon carbide MOSFET device comprising at least one cell, and each cell comprises a silicon carbide substrate of a first doping type; an epitaxial layer of a first doping type; the well regions of the second doping type are located in the epitaxial layer, and JFET regions are arranged between the adjacent well regions; the source region of the first doping type is located in the well region; the contact region of the second doping type is located in the well region and is adjacent to the source region; the field oxide layer is located on the surface of the epitaxial layer and located above the JFET region; the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer, and the first gate oxide layer and the second gate oxide layer are located on the two sides of the field oxide layer respectively and are adjacent to the field oxide layer respectively; the gate conductors comprise a first gate conductor and a second gate conductor, the first gate conductor covers the surface of the first gate oxide layer and part of the surface of the field oxide layer, the second gate oxide layer covers the surface of the second gate oxide layer and part of the surface of the field oxide layer, and the first gate conductor and the second gate conductor are separated from each other.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device. Background Art

[0002] Silicon carbide (SiC), as a new generation of semiconductor materials, has excellent properties such as large bandgap, high breakdown electric field, high saturated electron drift rate, and high thermal conductivity. It can be widely used in the fields of high temperature, high voltage, high current, and high frequency. It is a semiconductor material with broad prospects. Compared with traditional silicon (Si)-based power devices, silicon carbide (SiC) power devices have a series of advantages such as fast switching speed, high operating frequency, and high input impedance, making them widely used in switching regulated power supplies, high frequencies, and power amplifiers.

[0003] Due to the Miller effect of gate-drain charge, the response frequency of the traditional SiC high-voltage MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device is greatly reduced when it works in a high-frequency state, which leads to a loss of device performance. In addition, in traditional SiC high-voltage MOSFET devices, the barrier height between the silicon carbide epitaxial layer and the gate oxide is 2.7eV, which is 0.4eV lower than the barrier height between the silicon epitaxial layer and the gate oxide. Therefore, under the same electric field, the gate tunnel current of the silicon carbide MOSFET device is much higher than that of the Si-based device; and the effective barrier height at the interface between the silicon carbide epitaxial layer and the gate oxide decreases significantly with the increase of temperature, making the device less reliable under high temperature conditions. Utility Model Content

[0004] In view of the above problems, the purpose of the present application is to provide a silicon carbide MOSFET device to improve the reliability of the device.

[0005] According to one aspect of the present invention, a silicon carbide MOSFET device is provided, comprising at least one unit cell, each of the unit cells comprising: a silicon carbide substrate of a first doping type; an epitaxial layer of a first doping type, located on the substrate; a well region of a second doping type, located in the epitaxial layer, with a JFET region between adjacent well regions; a source region of a first doping type, located in the well region; a contact region of a second doping type, located in the well region and adjacent to the source region; a field oxide layer, located on a surface of the epitaxial layer and above the JFET region; a gate oxide layer, comprising a first gate oxide layer and a second gate oxide layer, the first gate oxide layer and the second gate oxide layer being located on both sides of the field oxide layer, respectively, and adjacent to the field oxide layer, respectively; and a gate conductor, comprising a first gate conductor and a second gate conductor, the first gate conductor covering a surface of the first gate oxide layer and a portion of a surface of the field oxide layer, the second gate oxide layer covering a surface of the second gate oxide layer and a portion of a surface of the field oxide layer, and the first gate conductor and the second gate conductor being separated from each other.

[0006] Optionally, the width of the field oxide layer is smaller than the width of the JFET region, and a projection of the field oxide layer on the surface of the epitaxial layer is located within the region of the JFET region.

[0007] Optionally, the thickness of the field oxide layer is greater than the thickness of the gate oxide layer.

[0008] Optionally, the thickness of the field oxide layer is The thickness of the gate oxide layer is

[0009] Optionally, the first gate oxide layer is located on a first side of the field oxide layer, one side wall of the first gate oxide layer is adjacent to the field oxide layer, and one side wall of the first gate oxide layer away from the field oxide layer is flush with a side wall of the source region close to the field oxide layer or extends above the source region; the second gate oxide layer is located on a second side of the field oxide layer, one side wall of the second gate oxide layer is adjacent to the field oxide layer, and one side wall of the second gate oxide layer away from the field oxide layer is flush with a side wall of the source region close to the field oxide layer or extends above the source region; wherein the first side and the second side of the field oxide layer are opposite.

[0010] Optionally, the thickness of the first gate conductor and the second gate conductor is

[0011] Optionally, a distance between the first gate conductor and the second gate conductor is 1 μm to 1.2 μm.

[0012] Optionally, it also includes: an interlayer dielectric layer, covering the surface and side walls of the first gate conductor and the second gate conductor, the surface of the field oxide layer exposed between the first gate conductor and the second gate conductor, and the surface of the source region and the contact region; a source electrode, located on the interlayer dielectric layer, and passing through the interlayer dielectric layer to be electrically connected to the source region and the contact region; a drain electrode, located on the surface of the substrate away from the epitaxial layer, and electrically connected to the substrate; and a gate electrode, located on the interlayer dielectric layer, and passing through the interlayer dielectric layer to be electrically connected to the first gate conductor and the second gate conductor.

[0013] The silicon carbide MOSFET device provided in the present application forms a field oxide layer above the JFET region, and the gate conductor separates and covers the gate oxide layer and part of the field oxide layer. While ensuring the normal parameters of the device, the reverse transfer capacitance and the amount of charge between the gate and the drain can be reduced, and the switching frequency of the device can be further increased and the switching loss can be reduced. Both reduce the input capacitance Ciss, and improve the switching speed, high-frequency performance and reliability of the device.

[0014] Furthermore, the field oxide layer has a greater thickness than the gate oxide layer, so that the device has a thick field oxide layer in the JFET region, which improves the anti-breakdown performance of the field oxide layer under high voltage in the JFET region, increases the breakdown voltage of the device, enhances the stability of the silicon carbide MOSFET device, and improves the reliability of the device; at the same time, the field oxide layer is thicker and the input capacitance Ciss is smaller, so that the device has a faster switching speed and smaller switching loss.

[0015] Furthermore, the present application isolates the gate conductor to form a separated gate structure, which can reduce the charge density at the gate oxide interface and improve the high-frequency performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic structural diagram of a cell of a silicon carbide MOSFET device according to an embodiment of the present application is shown;

[0018] Figure 2a to Figure 2g The cross-sectional views at various stages in the process of preparing the silicon carbide MOSFET device according to the embodiment of the present application are shown. DETAILED DESCRIPTION

[0019] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0020] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this disclosure are only for the purpose of describing specific embodiments and are not intended to limit this disclosure. The term "and / or" used in this disclosure includes any and all combinations of one or more related listed items.

[0021] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0022] Unless otherwise specified below, the various layers or regions of the semiconductor device may be formed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer may be made of SiO2 or a material with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.

[0023] In the present disclosure, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

[0024] The specific implementation of the present disclosure is further described in detail below in conjunction with the drawings and examples.

[0025] The silicon carbide MOSFET device includes at least one cell. Figure 1 FIG. 1 shows a schematic structural diagram of a cell of a silicon carbide MOSFET device according to an embodiment of the present application. Figure 1 As shown, each cell includes a substrate 101 of a first doping type, an epitaxial layer 102 of a first doping type located on the substrate 101; a well region 103 of a second doping type located in the epitaxial layer 102; a source region 105 of a first doping type located in the well region 103, and a contact region 104 of a second doping type located in the well region 103 and adjacent to the source region 105, wherein the doping concentration of the contact region 104 is higher than that of the well region 103. The epitaxial layer 102 between adjacent well regions 103 forms a JFET region 106. The first doping type is one of an N doping type and a P doping type, and the second doping type is the other of the N doping type and the P doping type. In this embodiment, the first doping type is, for example, an N doping type, and the second doping type is, for example, a P doping type, that is, the substrate 101, the epitaxial layer 102, and the source region 105 are N doping types, and the well region 103 and the contact region 104 are P doping types.

[0026] The silicon carbide MOSFET device includes a field oxide layer 107 , a gate oxide layer and a gate conductor.

[0027] The field oxide layer 107 is located above the JFET region 106 . The width of the field oxide layer 107 is smaller than the width of the JFET region 106 . The projection of the field oxide layer 107 on the surface of the epitaxial layer 101 is located within the region of the JFET region 106 .

[0028] The gate oxide layer includes a first gate oxide layer 1081 and a second gate oxide layer 1082. The first gate oxide layer 1081 and the second gate oxide layer 1082 are respectively located on both sides of the field oxide layer 107 and are respectively adjacent to the field oxide layer 107. Specifically, the first gate oxide layer 1081 is located on a first side (e.g. Figure 1 The left side of the figure), the side wall of the first gate oxide layer 1081 is adjacent to the field oxide layer 107, the side wall of the first gate oxide layer 1081 away from the field oxide layer 107 is flush with the side wall of the source region 105 close to the field oxide layer 107 or extends above the source region 105; the second gate oxide layer 1082 is located on the second side of the field oxide layer 107 (for example Figure 1 ), a side wall of the second gate oxide layer 1082 is adjacent to the field oxide layer 107, and a side wall of the second gate oxide layer 1082 away from the field oxide layer 107 is flush with the source region 105 or extends above the source region 105; wherein the first side and the second side of the field oxide layer 107 are opposite. The gate conductor includes a first gate conductor 1091 and a second gate conductor 1092, the first gate conductor 1091 covers the first gate oxide layer 1081 and a portion of the field oxide layer 107, the second gate conductor 1092 covers the second gate oxide layer 1082 and a portion of the field oxide layer 107, and there is a gap between the first gate conductor 1091 and the second gate conductor 1092, and the gap exposes a portion of the surface of the field oxide layer 107, that is, the first gate conductor 1091 and the second gate conductor 1092 are separated from each other.

[0029] In this embodiment, the thickness of the field oxide layer 107 is greater than the thickness of the gate oxide layer. In one embodiment, the thickness of the field oxide layer 107 is, for example, The thickness of the gate oxide layer is, for example, The thickness of the gate conductor is, for example, The distance between the first gate conductor 1091 and the second gate conductor 1092 is, for example, 1 μm to 1.2 μm.

[0030] In the present application, the thickness of the field oxide layer 107 is relatively thin, which can reduce production costs and improve the voltage resistance level of the device, thereby improving the reliability of the device; the use of a structure separated by a gate conductor can make the thickness of the gate oxide layer thinner, which can reduce the driving voltage of the device and improve the device turn-on speed and current driving capability.

[0031] The silicon carbide MOSFET device includes an interlayer dielectric layer 110, which covers the surface of the first gate conductor 1091 and the second gate conductor 1092, the sidewalls of the first gate conductor 1091 and the second gate conductor 1092, the surface of the field oxide layer 107 exposed between the first gate conductor 1091 and the second gate conductor 1092, and the surface of the source region 105 and the contact region 104. In one embodiment, the interlayer dielectric layer 110 is, for example, a borophosphosilicate glass layer (BPSG) and a silicon nitride layer (SIN x )'s composite structure.

[0032] The silicon carbide MOSFET device further includes a source electrode 111 and a drain electrode 112. The source electrode 111 is located on the interlayer dielectric layer 110, and penetrates the interlayer dielectric layer 110 to be electrically connected to the source region 105 and the contact region 104. The substrate 101 serves as the drain region of the device 100, and the drain electrode 112 is located on the surface of the substrate 101 away from the epitaxial layer 102, and is electrically connected to the substrate 101.

[0033] although Figure 1 Although not shown in the figure, it should be known that the silicon carbide MOSFET device further includes a gate electrode, which is located on the interlayer dielectric layer 110 and penetrates the interlayer dielectric layer 110 to be electrically connected to the first gate conductor 1091 and the second gate conductor 1092 .

[0034] Figure 2a to Figure 2g The cross-sectional views at various stages in the process of preparing the silicon carbide MOSFET device according to the embodiment of the present application are shown.

[0035] like Figure 2a As shown, an epitaxial layer 102 is formed on a substrate 101 .

[0036] In this step, for example, an N-type epitaxial layer 102 is grown on an N+ type substrate 101. The substrate 101 is, for example, an N+ type doped SiC substrate having a (0001) crystal plane and 4±0.5° toward the <11-20> crystal direction. The doping concentration of the substrate 101 is, for example, 6E18 cm -3 ~1.5E19 cm -3 The doping concentration of the epitaxial layer 102 is, for example, 8E15 cm -3 ~2E16 cm -3 The thickness of the epitaxial layer 102 is, for example, 8 μm to 12 μm.

[0037] like Figure 2b As shown, a well region 103 is formed in the epitaxial layer 102 .

[0038] In this step, for example, a first mask is formed on the surface of the epitaxial layer 102, the first mask is patterned by photolithography and etching processes, and a first ion implantation is performed on the epitaxial layer 102 through the patterned first mask, and P-type ions (usually Al ions or B ions) are doped in the epitaxial layer 102 through the first ion implantation to form a P-type doped well region 103 in the epitaxial layer 102. After the well region 103 is formed, the first mask is removed.

[0039] In one embodiment, the junction depth of the well region 103 is, for example, 0.5 μm to 2 μm, and the width is, for example, 2 μm to 8 μm. The region between the well regions 103 is the JFET region 106 .

[0040] like Figure 2c As shown, a source region 105 and a contact region 106 are formed in the well region 103 .

[0041] In this step, for example, a second mask is formed on the surface of the epitaxial layer 102, the second mask is patterned by photolithography and etching processes, and a second ion implantation is performed on the well region 103 through the patterned second mask, and N-type ions are doped in the well region 103 through the second ion implantation to form an N-type doped source region 105 in the well region 103. After the source region 105 is formed, the second mask is removed.

[0042] Next, a third mask is formed on the surface of the epitaxial layer 102, the third mask is patterned by photolithography and etching processes, and a third ion implantation is performed on the well region 103 through the patterned third mask, and P-type ions are doped in the well region 103 through the third ion implantation to form a P-type doped contact region 104 in the well region 103. After the contact region 104 is formed, the third mask is removed.

[0043] In one embodiment, the first mask, the second mask and the third mask are, for example, SiO 2 masks or polysilicon masks.

[0044] Next, high temperature annealing is performed to activate the impurities. The annealing temperature is, for example, 1650° C. to 1750° C., and the annealing time is, for example, 10 min to 40 min. After the high temperature annealing, the active region of the silicon carbide MOSFET device is formed.

[0045] like Figure 2d As shown, a field oxide layer 107 is formed on the JFET region 106 .

[0046] In this step, an oxide layer is grown on the epitaxial layer 103, and then the oxide layer is etched by photolithography and etching processes to form a field oxide layer 107 located on the JFET region 106. The width of the field oxide layer 107 is smaller than the width of the JFET region 106. In one embodiment, the thickness of the field oxide layer 107 is, for example,

[0047] like Figure 2e As shown, an oxide layer 108 a is formed on both sides of the field oxide layer 107 , and a gate conductor layer 109 a is formed on the field oxide layer 107 and the oxide layer 108 a .

[0048] In this step, for example, a thermal oxidation process is used to form oxide layers 108a on both sides of the field oxide layer 107. The oxide layers 108a are located on both sides of the field oxide layer 107 and are adjacent to the field oxide layer 107. In one embodiment, the thickness of the oxide layer 108a is, for example, It should be noted that an oxide layer is also formed on the field oxide layer 107 , but the thickness thereof can be ignored.

[0049] Next, the oxide layer 108 a is annealed in a NO or N 2 atmosphere to reduce the interface state density and improve the quality of the oxide layer 108 a .

[0050] Next, a gate conductor layer 109a is formed on the field oxide layer 107 and the oxide layer 108a by, for example, a deposition process. That is, the gate conductor layer 109a covers the surfaces of the oxide layer 107 and the oxide layer 108a.

[0051] like Figure 2f As shown, for example, photolithography and etching processes are used to etch the gate conductor layer 109a and the oxide layer 108a to form a gate oxide layer and a gate conductor.

[0052] The gate oxide layer includes a first gate oxide layer 1081 and a second gate oxide layer 1082. The first gate oxide layer 1081 and the second gate oxide layer 1082 are respectively located on both sides of the field oxide layer 107 and are respectively adjacent to the field oxide layer 107. Specifically, the first gate oxide layer 1081 is located on a first side (e.g. Figure 1 The left side of the figure), the side wall of the first gate oxide layer 1081 is adjacent to the field oxide layer 107, the side wall of the first gate oxide layer 1081 away from the field oxide layer 107 is flush with the side wall of the source region 105 close to the field oxide layer 107 or extends above the source region 105; the second gate oxide layer 1082 is located on the second side of the field oxide layer 107 (for example Figure 1 ), one side wall of the second gate oxide layer 1082 is adjacent to the field oxide layer 107, and one side wall of the second gate oxide layer 1082 away from the field oxide layer 107 is flush with one side wall of the source region 105 close to the field oxide layer 107 or extends above the source region 105; wherein the first side and the second side of the field oxide layer 107 are opposite.

[0053] The gate conductor includes a first gate conductor 1091 and a second gate conductor 1092. The first gate conductor 1091 covers the first gate oxide layer 1081 and a portion of the field oxide layer 107. The second gate conductor 1092 covers the second gate oxide layer 1082 and a portion of the field oxide layer 107. There is a gap between the first gate conductor 1091 and the second gate conductor 1092. The gap exposes a portion of the surface of the field oxide layer 107, that is, the first gate conductor 1091 and the second gate conductor 1092 are separated from each other. The thickness of the first gate conductor 1091 and the second gate conductor 1092 is, for example, The distance between the first gate conductor 1091 and the second gate conductor 1092 is, for example, 1 μm to 1.2 μm.

[0054] like Figure 2g As shown, an interlayer dielectric layer 110 is formed.

[0055] In this step, for example, an interlayer dielectric layer 110 is formed on the surfaces of the first gate conductor 1091 and the second gate conductor 1092 , the surface of the field oxide layer 107 exposed between the first gate conductor 1091 and the second gate conductor 1092 , and the surfaces of the source region 105 and the contact region 104 by a deposition process.

[0056] Next, a lead hole is formed in the interlayer dielectric layer 110 by using photolithography and etching processes, a gate electrode (not shown) and a source electrode 111 are formed on the interlayer dielectric layer 110, and a drain electrode 112 is formed by performing a thinning process and a back metallization process on the surface of the substrate 101 away from the epitaxial layer 102.

[0057] The source electrode 111 is located above the interlayer dielectric layer 110 and penetrates the interlayer dielectric layer 110 to be electrically connected to the source region 105 and the contact region 104. The substrate 101 serves as the drain region of the silicon carbide MOSFET device. The drain electrode 112 is located on the surface of the substrate 101 away from the epitaxial layer 102 and is electrically connected to the substrate 101. Figure 1 Although not shown in the figure, it should be known that the gate electrode is located above the interlayer dielectric layer 110 and penetrates the interlayer dielectric layer 110 to be electrically connected to the first gate conductor 1091 and the second gate conductor 1092. The gate electrode and the source electrode 111 are separated from each other.

[0058] The silicon carbide MOSFET device provided in the present application forms a field oxide layer above the JFET region, and the gate conductor separates and covers the gate oxide layer and part of the field oxide layer. While ensuring the normal parameters of the device, the reverse transfer capacitance and the amount of charge between the gate and the drain can be reduced, and the switching frequency of the device can be further increased and the switching loss can be reduced. Both reduce the input capacitance Ciss, and improve the switching speed, high-frequency performance and reliability of the device.

[0059] Furthermore, the field oxide layer has a greater thickness than the gate oxide layer, so that the device has a thick field oxide layer in the JFET region, which improves the anti-breakdown performance of the field oxide layer under high voltage in the JFET region, increases the breakdown voltage of the device, enhances the stability of the silicon carbide MOSFET device, and improves the reliability of the device; at the same time, the field oxide layer is thicker and the input capacitance Ciss is smaller, so that the device has a faster switching speed and smaller switching loss.

[0060] Furthermore, the present application isolates the gate conductor to form a separated gate structure, which can reduce the charge density at the gate oxide interface and improve the high-frequency performance of the device.

[0061] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A silicon carbide MOSFET device, characterized in that: comprising at least one cell, each of the cells comprising: a silicon carbide substrate of a first doping type; An epitaxial layer of a first doping type, located on the substrate; A well region of a second doping type is located in the epitaxial layer, and a JFET region is located between adjacent well regions; A source region of a first doping type, located in the well region; A contact region of a second doping type, located in the well region and adjacent to the source region; A field oxide layer, located on the surface of the epitaxial layer and above the JFET region; a gate oxide layer, comprising a first gate oxide layer and a second gate oxide layer, wherein the first gate oxide layer and the second gate oxide layer are respectively located on both sides of the field oxide layer and are respectively adjacent to the field oxide layer; and The gate conductor comprises a first gate conductor and a second gate conductor, wherein the first gate conductor covers a surface of the first gate oxide layer and a portion of a surface of the field oxide layer, the second gate oxide layer covers a surface of the second gate oxide layer and a portion of a surface of the field oxide layer, and the first gate conductor and the second gate conductor are separated from each other.

2. The silicon carbide MOSFET device according to claim 1, characterized in that: The width of the field oxide layer is smaller than the width of the JFET region, and the projection of the field oxide layer on the surface of the epitaxial layer is located within the region of the JFET region.

3. The silicon carbide MOSFET device according to claim 1, characterized in that: The thickness of the field oxide layer is greater than the thickness of the gate oxide layer.

4. The silicon carbide MOSFET device according to claim 3, characterized in that: The thickness of the field oxide layer is The thickness of the gate oxide layer is 5. The silicon carbide MOSFET device according to claim 1, characterized in that: The first gate oxide layer is located on a first side of the field oxide layer, a side wall of the first gate oxide layer is adjacent to the field oxide layer, and a side wall of the first gate oxide layer away from the field oxide layer is flush with a side wall of the source region close to the field oxide layer or extends above the source region; The second gate oxide layer is located on a second side of the field oxide layer, a side wall of the second gate oxide layer is adjacent to the field oxide layer, and a side wall of the second gate oxide layer away from the field oxide layer is flush with a side wall of the source region close to the field oxide layer or extends above the source region; The first side and the second side of the field oxide layer are opposite to each other.

6. The silicon carbide MOSFET device according to claim 1, characterized in that: The thickness of the first gate conductor and the second gate conductor is 7. The silicon carbide MOSFET device according to claim 1, characterized in that: The distance between the first gate conductor and the second gate conductor is 1 μm to 1.2 μm.

8. The silicon carbide MOSFET device according to claim 1, characterized in that: Also includes: an interlayer dielectric layer, covering the surface and sidewalls of the first gate conductor and the second gate conductor, the surface of the field oxide layer exposed between the first gate conductor and the second gate conductor, and the surfaces of the source region and the contact region; a source electrode, located on the interlayer dielectric layer and penetrating the interlayer dielectric layer to be electrically connected to the source region and the contact region; A drain electrode, located on a surface of the substrate away from the epitaxial layer and electrically connected to the substrate; as well as The gate electrode is located on the interlayer dielectric layer and penetrates the interlayer dielectric layer to be electrically connected to the first gate conductor and the second gate conductor.

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