Semiconductor structure

Abstract

The present disclosure provides a semiconductor structure including a first semiconductor fin and a second semiconductor fin on a substrate, a first gate structure on the first semiconductor fin, a second gate structure on the second semiconductor fin, and a gate isolation structure between the first semiconductor fin and the second semiconductor fin and between the first gate structure and the second gate structure, where the gate isolation structure includes a first dielectric layer at a lower portion of the gate isolation structure and a second dielectric layer at an upper portion of the gate isolation structure, and the width of the second dielectric layer is greater than that of the first dielectric layer.

Description

Technical Field

[0001] The present disclosure provides a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component or line that can be created using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This reduction has also increased the complexity of processing and manufacturing ICs, and similar developments are needed in IC processing and manufacturing to achieve these advances. As semiconductor devices continue to shrink, challenges arise in achieving the required density and performance. For example, the formation of a gate isolation structure can cut the gate structure into segments, and when the spacing distance between two adjacent active regions is reduced to meet the design requirements of smaller technology nodes, the space for forming the gate isolation structure becomes smaller, resulting in an increase in parasitic capacitance between the two segments of the gate structure cut by the gate isolation structure. Higher parasitic capacitance is detrimental to the overall performance of the IC device. In some examples, higher parasitic capacitance may result in lower component speeds (e.g., RC delays). Therefore, although existing gate isolation structures are generally sufficient to isolate the gate structure into multiple segments, they are unsatisfactory in all aspects. Utility Model Content

[0004] The present disclosure provides a semiconductor structure, including a first semiconductor fin and a second semiconductor fin on a substrate, a first gate structure on the first semiconductor fin, a second gate structure on the second semiconductor fin, and a gate isolation structure between the first semiconductor fin and the second semiconductor fin and between the first gate structure and the second gate structure, wherein the gate isolation structure includes a first dielectric layer located at the bottom of the gate isolation structure and a second dielectric layer located at the top of the gate isolation structure, and the width of the second dielectric layer is greater than the width of the first dielectric layer.

[0005] The present disclosure also provides a semiconductor structure, including a first fin-shaped active region and a second fin-shaped active region on a substrate, a first gate structure on a channel region of the first fin-shaped active region, a second gate structure on a channel region of the second fin-shaped active region, and a gate isolation structure between the first gate structure and the second gate structure and between the first fin-shaped active region and the second fin-shaped active region. The first fin-shaped active region and the second fin-shaped active region extend longitudinally along a first direction. The first gate structure extends longitudinally along a second direction substantially perpendicular to the first direction. The second gate structure extends longitudinally along the second direction. The gate isolation structure extends longitudinally along the first direction, wherein in a cross section cutting through the first fin-shaped active region, the second fin-shaped active region, the first gate structure, and the second gate structure, the gate isolation structure is a T-shaped structure.

[0006] The present disclosure also provides a semiconductor structure, including a first transistor, a second transistor and a gate isolation structure. The first transistor includes: a first gate structure on a first channel region, and a plurality of first source / drain features coupled to the first channel region and disposed near the first gate structure. The second transistor includes: a second gate structure on a second channel region, and a plurality of second source / drain features coupled to the second channel region and disposed near the second gate structure. The gate isolation structure is used to provide isolation between the first gate structure and the second gate structure and to directly contact the first gate structure and the second gate structure, wherein in a cross section cutting through the first gate structure, the second gate structure, the first channel region and the second channel region, the shape of the gate isolation structure includes a T-shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 The disclosure will be best understood from the following detailed description when read together. It should be emphasized that, in accordance with standard industry practice, various features may not be drawn to scale and are only used for illustrative purposes. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flowchart illustrating an exemplary method for fabricating a semiconductor structure according to various embodiments of the present disclosure;

[0009] Figure 2 Showing various aspects of the present disclosure Figure 1 A fragmentary top view of an exemplary workpiece at various stages of operation;

[0010] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A, Fig.11A and Fig.13A The following are examples of various aspects of the present disclosure: Figure 2 The workpiece cut out by line AA is shown in Figure 1 fragmentary cross-sectional views of various manufacturing stages in the method;

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B and Fig. 13B The following are examples of various aspects of the present disclosure: Figure 2 The workpiece cut out by line BB is shown in Figure 1 fragmentary cross-sectional views of various manufacturing stages in the method;

[0012] Fig.12 Various embodiments according to the present disclosure are shown in Fig.13A and Fig. 13B A fragmentary top view of an exemplary workpiece is shown;

[0013] Fig.14A and Fig. 14B A fragmentary cross-sectional view showing an alternative working piece according to various aspects of the present disclosure;

[0014] Fig.15 , Fig.16 and Fig.17 Showing various aspects of the present disclosure Figure 1 Fragmentary cross-sectional views of alternative workpieces at various stages of manufacture in a method.

[0015]

Explanation of symbols

[0016] 100: Method

[0017] 102: Blocks

[0018] 104: Blocks

[0019] 106: Blocks

[0020] 108: Blocks

[0021] 110: Block

[0022] 112: Block

[0023] 114: Blocks

[0024] 116: Blocks

[0025] 118: Blocks

[0026] 120: Blocks

[0027] 122: Blocks

[0028] 200:Workpiece

[0029] 202:Substrate

[0030] 204: Isolation Features

[0031] 205a: Fin structure

[0032] 205b: Fin structure

[0033] 205c: Fin structure

[0034] 205C: Channel area

[0035] 205d: Fin-like structure

[0036] 205SD: Source / Drain Region

[0037] 206: Channel layer

[0038] 207: Sacrificial layer

[0039] 208: Source / Drain Characteristics

[0040] 210a: Virtual gate structure

[0041] 210b: Virtual gate structure

[0042] 210b': paragraph

[0043] 210b”: Paragraph

[0044] 210b1: Part

[0045] 210bs:Surface

[0046] 210c: Virtual gate structure

[0047] 210d: Virtual gate structure

[0048] 212: Virtual gate dielectric layer

[0049] 214: Virtual gate electrode

[0050] 216: Gate spacer

[0051] 218: Contact etching stop layer

[0052] 220: Interlayer dielectric layer

[0053] 222: Mask layer

[0054] 224: First Opening

[0055] 228: Etching process

[0056] 230: Groove

[0057] 230e: Groove

[0058] 230u: upper

[0059] 232: first dielectric layer

[0060] 234: Etching process

[0061] 236: first dielectric layer

[0062] 236':Multi-layer structure

[0063] 236a: Outer layer

[0064] 236b: Inner layer

[0065] 238: Mask layer

[0066] 240: Opening

[0067] 242: Etching process

[0068] 244: Second dielectric layer

[0069] 244a: Part 1

[0070] 244b: Part 2

[0071] 246: Gate isolation structure

[0072] 246': Gate isolation structure

[0073] 248:Seam

[0074] 250: Gate stack

[0075] 250a: Gate stack

[0076] 250b': Gate stack

[0077] 250b”: Gate stack

[0078] 250c: Gate stack

[0079] 250d: Gate stack

[0080] 252: Dielectric layer

[0081] 254: Gate electrode

[0082] 270: Internal gap

[0083] A: Width

[0084] AA:Line

[0085] B: Width

[0086] BB:Line

[0087] C: Distance

[0088] D: Distance

[0089] D1: Depth

[0090] D2: Depth

[0091] S: Spacing

[0092] W1: Width

[0093] W2: Width

[0094] X: Direction

[0095] Y: direction

[0096] Z: Direction DETAILED DESCRIPTION

[0097] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and compositions are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the subsequent description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed by direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0098] Spatially relative terms, such as "lower," "below," "beneath," "upper," "above," etc., may be used herein for convenience to describe the relationship between one element or feature and another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0099] In addition, when "about," "approximately," etc. are used to describe a value or range of numbers, these terms are intended to include values ​​within a reasonable range, taking into account variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known process tolerances for manufacturing features associated with the value, a value or range of values ​​includes a reasonable range containing the value, such as within + / -10% of the value. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the process tolerance associated with depositing the material layer is known by those of ordinary skill in the art to be + / -15%.

[0100] Multi-gate devices improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or part thereof disposed on more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices, which are a trend and a forward-looking choice for high-performance and low-leakage applications. Fin field effect transistors have an elevated channel with multiple sides wrapped by a gate (e.g., a gate wraps around the top and multiple sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that extends to partially or completely surround the channel region to provide flow to both sides or more of the channel region. Because the gate structure surrounds the channel region, MBC transistors may also be referred to as surrounding gate transistors (SGTs) or gate-all-around (GAA) transistors. The channel region of an MBC transistor may be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives the MBC transistor alternative names, such as nanosheet transistor or nanowire transistor.

[0101] The present disclosure relates to methods for forming T-shaped gate isolation structures and forming semiconductor structures related thereto. In some embodiments, an exemplary method includes forming a trench to cut the gate structure into two segments, forming a first dielectric layer to substantially fill the trench, etching back the first dielectric layer to release the upper portion of the trench, performing an etching process to expand at least a portion of the upper portion of the trench, and forming a second dielectric layer in the expanded upper portion of the trench. Therefore, in a cross-sectional view, the gate isolation structure resembles a T-shape. By forming a T-shaped gate isolation structure, the parasitic capacitance between the two segments of the gate structure divided by the T-shaped gate isolation structure can be advantageously reduced, and the device speed can be increased. In some other embodiments, different portions of the T-shaped gate isolation structure can be formed of dielectric materials with different dielectric constants, and the device speed can be adjusted to meet the requirements of different device speeds.

[0102] Various aspects of the disclosure will now be described in more detail with reference to the drawings. Figure 1 A flowchart of a method 100 for forming a semiconductor structure according to some embodiments of the present disclosure is shown. The method 100 is hereinafter combined with Figure 2 , FIG. 3A to FIG. 11A , FIG. 3B to FIG. 11B , Fig.12 , FIG. 13A to FIG. 14A , FIG. 13B to FIG. 14B , Fig.15 , Fig.16 and Fig.17 100 is described, and these figures are fragmentary cross-sectional views or top views of the workpiece 200 in different manufacturing stages according to an embodiment of the method 100. The method 100 is only an example and is not intended to limit the present disclosure to the contents explicitly described herein. Additional steps may be provided before, between, and after the method 100, and some of the steps may be replaced, removed, or exchanged for use in additional embodiments of the method. For simplicity, not all steps are described in detail herein. Since the workpiece 200 will be manufactured into a semiconductor structure after the manufacturing process is completed, the workpiece 200 may be referred to as a semiconductor structure or workpiece 200 according to the context. To avoid misunderstanding, the directions X, Y, and Z in the figures are perpendicular to each other and are used consistently in the figures. Throughout the present disclosure, similar reference numerals represent similar features unless otherwise specified.

[0103] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B The method 100 includes a block 102 of receiving a workpiece 200. The workpiece 200 includes a substrate 202 (eg, Figure 3A and Figure 3B). In an embodiment, substrate 202 is a bulk silicon substrate (i.e., includes bulk single crystal silicon). Substrate 202 may include other semiconductor materials in various embodiments, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some alternative embodiments, substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate, and include carriers, insulators on carriers, and semiconductor layers on insulators. Substrate 202 may include various doped regions (not shown) arranged according to the design requirements of the semiconductor structure or workpiece 200, such as p-type doped regions, n-type doped regions, or combinations thereof. The p-type doped region (e.g., p-type well) includes a p-type dopant, such as boron (B), gallium (Ga), other p-type dopants, or a combination thereof. The n-type doped region (e.g., n-type well) includes an n-type dopant, such as phosphorus (P), arsenic (As), other n-type dopants, or a combination thereof. In some embodiments, the substrate 202 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. An ion implantation process, a diffusion process, and / or other suitable doping processes may be performed to form the various doped regions.

[0104] The workpiece 200 further includes a plurality of fin-shaped structures / fin-shaped active regions (such as fin-shaped structure 205a, fin-shaped structure 205b, fin-shaped structure 205c, and fin-shaped structure 205d) disposed on the substrate 202. Figure 2 The number of fin structures 205a, 205b, 205c, and 205d shown is only an example. The workpiece 200 may include any suitable number of fin structures. In some embodiments, the fin structures 205a, 205b, 205c, and 205d may be formed by patterning the top of the substrate 202. Each of the fin structures 205a, 205b, 205c, and 205d protrudes vertically along the direction Z, extends in an increasing manner along the direction X, and is separated from each other along the direction Y, such as Figure 2As shown. In this embodiment, the fin structure 205a, the fin structure 205b, the fin structure 205c, and the fin structure 205d may include semiconductor compositions uniformly distributed along the direction Z, and the final structure of the workpiece 200 includes a FinFET. In some embodiments, the fin structure 205a and the fin structure 205b are used as a dual-fin active region in a dual-fin device (e.g., an n-type dual-fin device), and the fin structure 205c and the fin structure 205d are used as a dual-fin active region in another dual-fin device (e.g., a p-type dual-fin device). The present disclosure is also applicable to single-fin devices or other multi-fin devices.

[0105] like Figure 3A As shown, each fin structure 205a, fin structure 205b, fin structure 205c and fin structure 205d includes a channel region 205C and a source / drain region 205SD. Each channel region 205C is located below the gate structure, and the source / drain region 205SD does not overlap with the gate structure. As will be further described below, source / drain features 208 will be formed in and / or on the source / drain region 205SD. The source / drain features 208 can refer to the source or drain individually or collectively depending on the context.

[0106] The workpiece 200 also includes a plurality of isolation features (such as Figure 3B The isolation features 204 shown are used to isolate two adjacent fin structures. The isolation features 204 may also be referred to as shallow trench isolation (STI) features 204. In some embodiments, the shallow trench isolation features 204 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0107] like Figure 2 and Figure 3AAs shown, the workpiece 200 also includes source / drain features 208 formed on the source / drain region 205SD and coupled to the channel region 205C. Depending on the conductivity type of the transistor to be formed, the source / drain features 208 can be n-type source / drain features or p-type source / drain features. Exemplary n-type source / drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing n-type dopants (e.g., phosphorus, arsenic, or antimony) during the epitaxial process, or performed ex-situ doping using a junction implant process. Exemplary p-type source / drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped by introducing p-type dopants (e.g., boron or gallium) during the epitaxial process, or performed ex-situ doping using a junction implant process. Each of the source / drain features 208 may span a single fin structure or span two fin structures. For example, the source / drain features 208 in a dual-fin device may span across the fin structure 205 a and the fin structure 205 b , or span across the fin structure 205 c and the fin structure 205 d .

[0108] Continue to refer to Figure 2 , Figure 3A and Figure 3B The workpiece 200 includes a dummy gate structure (e.g., dummy gate structure 210a, dummy gate structure 210b, dummy gate structure 210c, and dummy gate structure 210d) disposed on the channel region 205C of the fin structure 205a, fin structure 205b, fin structure 205c, and fin structure 205d. Figure 2 and Figure 3B In the illustrated embodiment, the dummy gate structure 210b is formed directly on the channel region 205C of the fin structure 205a, the fin structure 205b, the fin structure 205c, and the fin structure 205d. Each dummy gate structure 210a, the dummy gate structure 210b, the dummy gate structure 210c, and the dummy gate structure 210d includes a dummy gate dielectric layer 212 and a dummy gate electrode 214 on the dummy gate dielectric layer 212. In some embodiments, the dummy gate dielectric layer 212 may include silicon oxide, and the dummy gate electrode 214 may include polysilicon. In such an embodiment, a gate replacement process (or a gate-last process) is adopted, in which one or more dummy gate structures 210a, dummy gate structures 210b, dummy gate structures 210c, and dummy gate structures 210d provide a placeholder for a functional gate stack. Other processes and configurations are also possible.

[0109] The sidewalls of the dummy gate structure 210a, the dummy gate structure 210b, the dummy gate structure 210c, and the dummy gate structure 210d are lined with gate spacers 216. In an exemplary process, the gate spacers can be conformally deposited on the workpiece 200, including on the top surface and sidewalls of the dummy gate structure 210a, the dummy gate structure 210b, the dummy gate structure 210c, and the dummy gate structure 210d. The term "conformal" is used herein to facilitate describing a layer having a substantially uniform thickness in various regions. The gate spacer can be a single-layer structure or a multi-layer structure. The gate spacer can include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, silicon oxynitride, and / or a combination thereof, and can be deposited using processes such as chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. The gate spacers may then be etched back to form gate spacers 216 extending along the sidewall surfaces of the dummy gate structures 210a, 210b, 210c, and 210d. The dielectric material used for the gate spacers may be selected so that the dummy gate structures 210a, 210b, 210c, and 210d are selectively removed without substantially damaging the gate spacers 216.

[0110] Continue to refer to Figure 3A , the workpiece 200 also includes a contact etch stop layer (CESL) 218 ​​and an interlayer dielectric (ILD) layer 220 deposited on the source / drain features 208. The contact etch stop layer 218 is configured to protect various underlying components during subsequent manufacturing processes and may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. Figure 3AAs shown, the contact etch stop layer 218 can be deposited on the top surface of the source / drain features 208 and the sidewalls of the gate spacer 216. The interlayer dielectric layer 220 is deposited on the workpiece 200 by a CVD process, a PECVD process, or other suitable deposition techniques after the contact etch stop layer 218 is deposited. The interlayer dielectric layer 220 can include silicon oxide, a low-k dielectric material, tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG)), other suitable dielectric materials, or combinations thereof. One or more planarization processes (e.g., chemical mechanical polishing (CMP)) can be performed after the interlayer dielectric layer 220 is deposited to planarize the top surface of the workpiece 200. The planarization process may further remove the gate hard mask layer (not shown) formed on the dummy gate electrodes 214 of the dummy gate structures 210 a , 210 b , 210 c , and 210 d .

[0111] Reference Figure 1 , FIG. 4A to FIG. 4B , the method 100 includes forming a mask layer 222 on the workpiece 200 at block 104. The mask layer 222 may be a single layer structure or a multi-layer structure. The mask layer 222 may include any suitable material as long as its composition is different from the composition of the dummy gate structure 210a, the dummy gate structure 210b, the dummy gate structure 210c, the dummy gate structure 210d, and the gate spacer 216, so as to be selectively removed by an etching process.

[0112] Reference Figure 1 and FIG. 5A to FIG. 5B, the method 100 includes a block 106, the mask layer 222 is patterned to form a first opening 224 that exposes a portion of the dummy gate structure 210b. In some embodiments, a combination of lithography and etching processes are performed to form the patterned mask layer 222. For example, a photoresist layer (not shown) is formed on the workpiece 200 by, for example, spin coating. An exposure process is then performed using a mask. A development process can then be performed to remove the exposed portion of the photoresist layer, thereby forming a patterned mask layer 222. In some other embodiments, the patterned mask layer may include a patterned hard mask layer. The patterned hard mask layer can be patterned by using the patterned photoresist layer as an etching mask. In the illustrated embodiment, the patterned mask layer 222 exposes a portion 210b1 of the dummy gate structure 210b, which is disposed between the fin structure 205b and the fin structure 205c. The portion 210b1 of the dummy gate structure 210b is disposed on the isolation feature 204. The fin structure 205b is separated from the fin structure 205c by a spacing S. The first opening 224 has a width W1 along the direction Y. The width W1 is smaller than the spacing S.

[0113] Reference Figure 1 and FIG. 6A to FIG. 6B The method 100 includes a block 108 of performing an etching process 228 to form a trench 230 to divide the dummy gate structure 210b into a segment 210b′ and a segment 210b″. After forming a patterned mask layer 222 including a first opening 224, an etching process is performed on the workpiece 200 using the patterned mask layer 222 as an etching mask to form the trench 230. The etching process 228 may include a dry etching process, a wet etching process, or other suitable etching processes. In the present embodiment, the etching process 228 is performed using a chlorine-containing gas (e.g., Cl 2 ), fluorine-containing gases (such as CF 4 and / or C 2 F 6 ), other suitable gases and / or plasma, and / or a combination thereof. After performing the etching process 228, at least the sidewall surfaces of the segments 210b' and 210b" of the dummy gate structure 210b exposed to the trench 230 are substantially vertical. The width of the portion of the trench 230 extending through the dummy gate structure 210b is substantially equal to the width W1. Figure 6BIn the illustrated embodiment, the etching process 228 removes the portion 210b1 of the dummy gate structure 210b and removes a portion of the shallow trench isolation feature 204 disposed directly under the portion 210b1 of the dummy gate structure 210b. That is, the trench 230 extends through the dummy gate structure 210b and extends to the shallow trench isolation feature 204. Due to the high aspect ratio, the portion of the trench 230 extending to the shallow trench isolation feature 204 may have a width less than the width W1. In some other embodiments, the etching process 228 may also etch a portion of the substrate 202. In other words, the trench 230 may extend through the dummy gate structure 210b and the shallow trench isolation feature 204 and further extend into the substrate 202.

[0114] The trench 230 divides the remaining portion of the dummy gate structure 210b into two segments, namely, segment 210b' and segment 210b". The two segments 210b' and segment 210b" of the dummy gate structure 210b may be referred to as gate structures, respectively. Figure 6B In the illustrated embodiment, the groove 230 is disposed between the fin structure 205b and the fin structure 205c, the segment 210b' is wrapped around the fin structure 205a and the fin structure 205b, and the segment 210b" is wrapped around the fin structure 205c and the fin structure 205d. It will be appreciated that the workpiece 200 may include fin structures having different configurations, the groove 230 may be formed between any two adjacent fin structures, and the segment 210b' / segment 210b" may wrap around any suitable number (e.g., 1, 3, 4 or more) of fin structures. Although not illustrated, from a top view of the workpiece 200, the groove 230 extends longitudinally along the direction X and may further separate the virtual gate structure 210a, the virtual gate structure 210c, and the virtual gate structure 210d. The patterned mask layer 222 may be selectively removed after the groove 230 is formed.

[0115] Reference Figure 1 and FIG. 7A to FIG. 7B, the method 100 includes block 110, wherein a first dielectric layer 232 is deposited on the workpiece 200 to substantially fill the trench 230. The first dielectric layer 232 may include a low-k dielectric material or a high-k dielectric material. In some embodiments, the first dielectric layer 232 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, a low-k dielectric material, other suitable materials, or combinations thereof, and may be deposited by CVD, PECVD, flow CVD, PVD, ALD, other suitable methods, or combinations thereof. In an embodiment, the first dielectric layer 232 is formed of silicon oxide deposited by FCVD. In another embodiment, the first dielectric layer 232 is formed of silicon nitride, and an ALD process is first performed to form a first silicon nitride layer at the bottom of the trench 230, and then an FCVD process is performed to form a second silicon nitride layer on the first silicon nitride layer. Since the first silicon nitride layer and the second silicon nitride layer are formed by different deposition processes, an interface may exist between the first silicon nitride layer and the second silicon nitride layer. The annealing process may be performed after the first dielectric layer 232 is formed. Figure 7B As shown, the top surface of the first dielectric layer 232 may include a concave surface due to the presence of the trench 230. More specifically, a portion of the top surface of the first dielectric layer 232 directly above the trench 230 may be concave and below the remaining portion of the top surface of the first dielectric layer 232.

[0116] Reference Figure 1 and FIG. 8A to FIG. 8B , the method 100 includes block 112, wherein the first dielectric layer 232 is selectively etched back. After depositing the first dielectric layer 232, the first dielectric layer 232 is etched back by an etching process 234. The etching process 234 may include a dry etching process, a wet etching process, and / or a combination thereof. In the present embodiment, the etching process 234 is performed using a fluorine-containing gas (e.g., SiF 4 and / or HF) or other suitable gases. In an embodiment, the etching process 234 uses SiF 4 , etching process 228 uses Cl 2 In the present embodiment, the portion of the first dielectric layer 232 formed on the segment 210 b′ and the segment 210 b″ and the portion of the first dielectric layer 232 formed in the upper portion 230 u of the trench 230 are selectively removed, so that the portion of the first dielectric layer 232 (also referred to as the first dielectric layer 236) is formed at the bottom of the trench 230. The portion of the first dielectric layer 232 at the bottom of the trench 230 is referred to herein as the first dielectric layer 236. Removing the portion of the first dielectric layer 232 formed in the trench 230 releases the upper portion 230 u of the trench 230, as shown in FIG. Figure 8BIn an embodiment, the top surface of the first dielectric layer 236 is located above the top surface of the isolation feature 204. The upper portion 230u of the trench 230 has a depth D1 along the direction Z.

[0117] Reference Figure 1 and FIG. 9A to FIG. 9B The method 100 includes block 114, forming a patterned mask layer 238 on the workpiece 200. The formation of the patterned mask layer 238 is similar to the formation of the patterned mask layer 222 (eg, Figure 5B As shown), and repeated descriptions are omitted for simplicity. The patterned mask layer 238 includes an opening 240 configured to facilitate removal of the partial segment 210b' and the segment 210b". In this embodiment, the opening 240 has a width W2 along the direction Y, and the width W2 is greater than the width W1. Fig. 9B As shown, the opening 240 exposes the upper portion 230 u of the trench 230 , and also exposes a portion of the segment 210 b ′ and a portion of the segment 210 b ″ adjacent to the upper portion 230 u of the trench 230 .

[0118] Reference Figure 1 and FIG. 10A to FIG. 10B , method 100 includes block 116, performing an etching process 242 to recess portions of segment 210b′ and segment 210b″ that are not covered by the patterned mask layer 238 to enlarge at least a portion of the upper portion 230u of the trench 230. While using the patterned mask layer 238 as an etching mask, the etching process 242 is performed to recess portions of segment 210b′ and segment 210b″ that are not covered by the patterned mask layer 222. More specifically, the execution of the etching process 242 selectively recesses the virtual gate electrode 214 of the segment 210b' and the segment 210b". The execution of the etching process 242 enlarges at least a portion of the upper portion 230u of the trench 230. The enlarged portion of the upper portion 230u of the trench 230 may be referred to as a trench 230e. In the present embodiment, the trench 230e has a depth D2 along the direction Z, and the depth D2 is less than the depth D1. That is, after the etching process 242 is performed, a portion of the segment 210b' and the segment 210b" adjacent to the lower portion of the upper portion 230u of the trench 230 is not substantially recessed. In some other embodiments, the depth D2 may be substantially equal to the depth D1. The etching process 242 may be a dry etching process, a wet etching process, and / or a combination thereof. In the present embodiment, the etching process 234 is a wet etching process, using a wet etchant solution, including, for example, H 3 PO 4 In some embodiments, the temperature of the wet etchant solution is higher than room temperature. After performing the wet etching process, Fig. 10BAs shown, the segment 210b' has a surface 210bs exposed in the trench 230e and is bent inwardly due to the wet etching process. Similarly, the segment 210b" also has a surface bent inwardly. The patterned mask layer 238 can be selectively removed after the trench 230e is formed.

[0119] Reference Figure 1 , FIG. 11A to FIG. 11B and Fig.12 , the method 100 includes block 118, wherein a second dielectric layer 244 is deposited on the first dielectric layer 236 to substantially fill the trench 230e and the remaining portion of the upper portion 230u of the trench 230. In the exemplary process, a dielectric material layer (not shown) is deposited on the workpiece 200 to substantially fill the remaining portion of the upper portion 230u and the trench 230e. For example, the dielectric material layer may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, doped silicon oxide, combinations thereof, or other suitable materials, and may be formed by any suitable method, including CVD, ALD, PVD, other methods, or combinations thereof. A planarization process (e.g., CMP) may then be performed to remove excess portions of the dielectric material layer formed directly on the segments 210b' and 210b". The dielectric material layer formed in the trench 230e and the remainder of the upper portion 230u is referred to as a second dielectric layer 244. The second dielectric layer 244 has a shape of the trench 230e and a shape of the upper portion 230u. That is, the second dielectric layer 244 includes a first portion 244a formed in the remainder of the upper portion 230u and in direct contact with the first dielectric layer 236, and a second portion 244b formed in the trench 230e. Along the direction Y, the width A of the second portion 244b in the second dielectric layer 244 is greater than the width B of the first portion 244a. Since the width A is greater than the width B, the distance between the upper portions of the segments 210b' and 210b" is increased, thereby reducing the total parasitic capacitance of the workpiece 200. The width A is substantially equal to the width W2 (e.g., Fig. 9B ), the width B is substantially equal to the width W1 (as shown Figure 5B In an embodiment, the ratio of the width A to the spacing S (as shown in Figure 5B244b) can be between about 0.4 and 0.8. If the ratio is greater than 0.8, the risk of damage to the fin structure 205b and the fin structure 205c may be greatly increased due to, for example, etching variations associated with the etching process 242 and / or coverage offsets associated with the formation of the patterned mask layer 238. If the ratio is less than 0.4, the second dielectric layer 244 formed may not significantly affect the parasitic capacitance of the semiconductor structure and therefore will not significantly affect the device speed. In an embodiment, the width B may be between about 10nm and about 15nm, and the width difference between the width A and the width B may be between about 3nm and about 10nm. The distance C between the bottom point of the surface 210bs of the second portion 244b of the second dielectric layer 244 and the top surface of the fin structure 205c is between about -5nm and about 5nm. That is, the bottom point of the surface 210bs may be above the top surface of the fin structure 205c, coplanar with the top surface of the fin structure 205c, or below the top surface of the fin structure 205c.

[0120] The first dielectric layer 236 and the second dielectric layer 244 may be collectively referred to as a gate isolation structure 246. In the present embodiment, since the etching process 242 is performed to enlarge at least a portion of the upper portion of the trench 230, in the embodiment shown in FIG. Fig. 11B In the cross-sectional view shown, the shape of the gate isolation structure 246 is similar to a T-shape. In the present embodiment, the gate isolation structure 246 includes a seam (gap or air gap) 248 formed in the second dielectric layer 244, and the first dielectric layer 236 may be substantially free of any seams / gaps. In the present embodiment, the distance D between the lowest point of the first dielectric layer 236 and the bottom surface of the isolation feature 204 is between about -20nm and about 20nm. That is, the gate isolation structure 246 may extend into the isolation feature 204 without extending into the substrate, may have a bottom surface coplanar with the bottom surface of the isolation feature 204, or may extend through the isolation feature 204 and further extend into the substrate 202.

[0121] In an embodiment, the composition of the second dielectric layer 244 is the same as the composition of the first dielectric layer 236. For example, the first dielectric layer 236 and the second dielectric layer 244 are both formed of silicon nitride. It should be noted that even though the first dielectric layer 236 and the second dielectric layer 244 may be formed of the same material, there is a physical interface between the first dielectric layer 236 and the second dielectric layer 244. In some other embodiments, the composition of the second dielectric layer 244 is different from the composition of the first dielectric layer 236. For example, the second dielectric layer 244 may be formed of a low-k dielectric material, and the first dielectric layer 236 may be formed of a high-k dielectric material.

[0122] Fig.12 Show Fig.11A and Fig. 11BA fragmentary top view of the workpiece 200 is shown. In the illustrated embodiment, the gate isolation structure 246 extends longitudinally along the direction X and is disposed between the fin structure 205b and the fin structure 205c. The gate isolation structure 246 can be formed in any suitable position to meet different design requirements. For example, the gate isolation structure 246 can be configured to provide isolation between the gate structures of two single-fin devices, or to provide isolation between the gate structures of a single-fin device and a multi-fin (e.g., dual-fin) device. In addition to dividing the virtual gate structure 210b into two electrically and physically isolated segments 210b' and segment 210b", the gate isolation structure 246 can further cut one or more remaining gate structures. For example, as Fig.12 As shown, the gate isolation structure 246 also cuts each of the dummy gate structures 210 a , 210 c , and 210 d into several parts.

[0123] Reference Figure 1 and FIG. 13A to FIG. 13B , method 100 includes block 120, wherein the dummy gate structure is replaced by a gate stack. After forming the gate isolation structure 246, one or more etching processes may be performed to selectively remove the dummy gate structure 210a, the dummy gate structure 210b, the dummy gate structure 210c, and the dummy gate structure 210d. Functional gate stacks 250a, gate stacks 250b', gate stacks 250b", gate stacks 250c, and gate stacks 250d are then formed. The gate stacks 250a, gate stacks 250b', gate stacks 250b", gate stacks 250c, and gate stacks 250d may be referred to individually or collectively as gate stacks 250. The gate stack 250 includes a gate dielectric layer and a gate electrode 254 on the gate dielectric layer. The gate dielectric layer may include an interface layer (not shown) and a high-k dielectric layer 252. In some cases, the interface layer may be formed by thermal oxidation and may include silicon oxide. The high-k dielectric layer 252 is formed of a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials for the high-k dielectric layer include hafnium oxide, titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), hafnium silicon oxide (HfSiO 4 )、ZrO 2 ), zirconium silicon oxide (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 )、ZrO、Yttrium oxide (Y 2 O 3)、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, Hafnium Lanthanum Oxide (HfLaO), Silicon Lanthanum Oxide (LaSiO), Silicon Aluminum Oxide (AlSiO), Hafnium Tantalum Oxide (HfTaO), Hafnium Titanium Oxide (HfTiO), (Ba, Sr)TiO 3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In an embodiment, the high-k dielectric layer is formed of hafnium oxide (HfO). The gate electrode 254 may include multiple layers, such as a work function layer, a glue layer / barrier layer, and / or a metal fill (or bulk) layer. The work function layer includes a conductive material adjusted to have a desired work function (e.g., an n-type work function or a p-type work function), such as an n-type work function material and / or a p-type work function material. The p-type work function material includes TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 , WN, other p-type work function materials or combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials or combinations thereof. The glue layer / barrier layer may include a material that promotes adhesion between adjacent layers (e.g., a work function layer and a metal filling layer) and / or a material that blocks and / or reduces diffusion between gate layers (e.g., a work function layer and a metal filling layer). For example, the glue layer / barrier layer includes a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals or combinations thereof), a metal oxide, a metal nitride (e.g., TiN) or a combination thereof. The metal filling layer may include a suitable conductive material, such as aluminum (Al), copper (Cu), tungsten (W), ruthenium (Ru), titanium (Ti), a suitable metal or a combination thereof. After the dielectric layer 252 and the gate electrode 254 are deposited, a chemical mechanical polishing (CMP) process may be performed to remove excess material on the gate isolation structure 246. In some embodiments, the gate electrode 254 is subjected to a higher CMP removal rate than the gate isolation structure 246. Therefore, after the CMP process, the gate stack 250 has a concave top surface, such as Fig. 13B shown.

[0124] Reference Figure 1, the method 100 includes a block 122, performing further processes to complete the manufacturing process. Such further processes may include forming a silicide layer (not shown) on the source / drain features 208 and forming a multi-layer interconnect (MLI) structure (not shown) on the workpiece 200. The MLI may include various interconnect features, such as vias and conductive lines disposed in dielectric layers (e.g., etch stop layers and ILD layers). In some embodiments, the vias are vertical interconnect features configured to interconnect device-level contacts, such as source / drain contacts formed on the source / drain features 208 and gate contacts (not shown) formed on the gate stack 250.

[0125] In reference Figures 1 to 13B In the above-mentioned embodiment, the T-shaped gate isolation structure 246 includes a first dielectric layer 236 filling the bottom of the trench 230 and a second dielectric layer 244 formed on the first dielectric layer 236. Each of the first dielectric layer 236 and the second dielectric layer 244 is a single-layer structure. In some embodiments, in order to provide different device speeds, at least one of the first dielectric layer 236 and the second dielectric layer 244 may include a multi-layer structure. Fig. 14B In the illustrated embodiment, the workpiece 200 includes a T-shaped gate isolation structure 246'. The gate isolation structure 246' is similar to the gate isolation structure 246. One of the differences between the gate isolation structure 246' and the gate isolation structure 246 is that instead of forming a single-layer first dielectric layer 236 at the bottom of the trench 230, the gate isolation structure 246' forms a multi-layer structure 236' at the bottom of the trench 230. Fig. 14BAs shown. In the present embodiment, the multilayer structure 236' includes an inner layer 236b and an outer layer 236a extending along the sidewall and bottom surface of the inner layer 236b. In the exemplary process, the formation of the multilayer structure 236' may include conformally depositing the outer layer 236a on the workpiece 200 to partially fill the trench 230, then depositing the inner layer 236b on the outer layer 236a to fill the remaining portion of the trench 230, and etching back the inner layer 236b and the outer layer 236a in a manner similar to the etching back of the first dielectric layer 232. The term "conformal" is used herein to facilitate describing a layer having a substantially uniform thickness on various regions of the workpiece 200. In an embodiment, the thickness of the outer layer 236a may be between about 1nm and about 3nm. The outer layer 236a may be formed of a high-k dielectric material to provide satisfactory protection for the inner layer 236b in a subsequent process (e.g., an etching process configured to selectively remove the dummy gate structure). Inner layer 236b may be formed of a low-k dielectric material or a high-k dielectric material. In embodiments where a higher device speed is required, inner layer 236b may be formed of a low-k dielectric material. In embodiments, second dielectric layer 244 is also formed of a high-k dielectric material. Thus, inner layer 236b formed of a low-k dielectric material is wrapped by a high-k dielectric material. Second dielectric layer 244 and outer layer 236a may be formed of different high-k dielectric materials or the same high-k dielectric material. In some embodiments, multilayer structure 236' may include more than two dielectric layers.

[0126] exist Fig. 14B In the illustrated embodiment, the gate isolation structure 246' includes a multilayer structure 236' formed at the bottom of the trench 230. In some other embodiments, the gate isolation structure 246' includes a first dielectric layer 236 formed at the bottom of the trench 230, and the second dielectric layer 244 may be replaced by a multilayer structure having a configuration similar to the multilayer structure 236'. In some other embodiments, the first dielectric layer 236 and the second dielectric layer 244 are replaced by a first multilayer structure and a second multilayer structure, respectively. The first multilayer structure and the second multilayer structure may be the same as or different from the multilayer structure 236'. In the above reference Figures 1 to 14B In some embodiments, the gate isolation structure 246 / gate isolation structure 246′ is formed after forming the dummy gate structure 210a, the dummy gate structure 210b, the dummy gate structure 210c, and the dummy gate structure 210d and before forming the functional gate stack 250. In some other embodiments, the gate isolation structure 246 / gate isolation structure 246′ may be formed after forming the functional gate stack 250.

[0127] In reference FIG. 3A to FIG. 11A , FIG. 3B to FIG. 11B , FIG. 13A to FIG. 14A and FIG. 13B to FIG. 14BIn the depicted embodiment, each of the fin structures 205a, 205b, 205c, and 205d comprises a uniform semiconductor composition along the direction Z, and the resulting structure of the workpiece 200 comprises a FinFET, such as FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14B In alternative embodiments, method 100 may be applied to fabricate semiconductor structures including MBC transistors. Fig.15 , Fig.16 and Fig.17 In the illustrated embodiment, the workpiece 200 may be fabricated to form an MBC transistor, and Fig.16 and Fig.17 The fin structure 205 a , the fin structure 205 b , the fin structure 205 c , and the fin structure 205 d in the workpiece 200 may include at least one nanostructure of an MBC transistor. Fig.15 The cross-sectional view of the workpiece 200 is shown in FIG. Figure 3B resemblance, Fig.16 The cross-sectional view of the workpiece 200 is shown in FIG. Fig. 14B resemblance, Fig.17 The cross-sectional view of the workpiece 200 is shown in FIG. Fig.14A are similar, so for simplicity, repeated descriptions are omitted. Figures 15 to 17 The embodiment shown is similar to FIG. 3A to FIG. 14B One of the differences is that the fin structures 205a, 205b, 205c and 205d in the alternative embodiments can be formed by patterning one or more epitaxial layers deposited on the substrate 202 (e.g., a vertical stack having alternating channel layers 206 and sacrificial layers 207, such as Fig.15 The channel layer 206 and the sacrificial layer 207 have different compositions. In an embodiment, the channel layer 206 includes silicon and the sacrificial layer 207 includes silicon germanium. Before forming the source / drain features 208, the sacrificial layer 207 may be laterally recessed along the direction X, and the recessed sacrificial layer 207 may be covered by the internal spacer 270 (as shown). Fig.17 shown). Figure 1 The operations of blocks 104 through 120 of method 100 may then be performed on Fig.15 The exemplary workpiece 200 shown is performed to form a gate isolation structure 246 ′ (or gate isolation structure 246 ) to form Fig.16 and Fig.17200 in the workpiece. It should be noted that after the dummy gate structure is selectively removed, the sacrificial layer 207 in the channel region of the fin structure 205a, the fin structure 205b, the fin structure 205c, and the fin structure 205d is then selectively removed to form the channel layer 206 into an overhead nanostructure to form a channel region. A functional gate stack 250 is then formed on the channel region and wrapped around each suspended nanostructure or channel layer 206.

[0128] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and methods of forming the same. For example, the present disclosure provides a gate isolation structure disposed between two gate structures and a method of forming the same. The gate isolation structure is configured in a T-shape. By providing a T-shaped gate isolation structure, the parasitic capacitance between the two gate structures can be advantageously reduced. Therefore, the device speed can be increased and the device performance can be improved. In various embodiments, the device speed can be adjusted or controlled by forming the gate isolation structure using different dielectric materials. The present disclosure is compatible with various semiconductor manufacturing processes and is compatible with various semiconductor structures (e.g., single-fin fin field effect transistors, dual-fin fin field effect transistors, transistors with nanostructures (e.g., full-gate transistors)).

[0129] The present disclosure provides many embodiments. Semiconductor structures and methods of forming the same are disclosed herein. In one exemplary aspect, the present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A workpiece is received, the workpiece including: a first semiconductor fin and a second semiconductor fin on a substrate and a gate structure that simultaneously joins the first semiconductor fin and the second semiconductor fin. A first etching process is performed to remove a first portion of the gate structure disposed between the first semiconductor fin and the second semiconductor fin to form a trench. A first dielectric layer is formed in a lower portion of the trench. After forming the first dielectric layer, a second etching process is performed to expand an upper portion of the trench that is not filled by the first dielectric layer. A second dielectric layer is formed on the first dielectric layer to substantially fill a remaining portion of the trench.

[0130] In some embodiments, forming a first dielectric layer in the lower portion of the trench includes: depositing a first material layer on the gate structure and in the trench and etching back the first material layer to remove multiple portions of the first material layer formed on the gate structure and in the upper portion of the trench. In some embodiments, the composition of the first dielectric layer is the same as the composition of the second dielectric layer. In some embodiments, the first dielectric layer includes: a dielectric filling layer and a dielectric liner extending along the side and bottom surfaces of the dielectric filling layer. In some embodiments, the first etching process includes a dry etching process, and the second etching process includes a wet etching process. In some embodiments, the workpiece also includes an isolation feature disposed between multiple bottoms of the first semiconductor fin and the second semiconductor fin and in direct contact with the first semiconductor fin and the second semiconductor fin, and wherein the trench extends into the isolation feature. In some embodiments, the method also includes: forming a first patterned mask layer on the gate structure, wherein the first patterned mask layer includes a first opening exposing a first portion of the gate structure. In some embodiments, the method further comprises: after forming the first dielectric layer, forming a second patterned mask layer on the gate structure, wherein the second patterned mask layer comprises a second opening, and the width of the second opening is greater than the width of the first opening. In some embodiments, the first dielectric layer comprises silicon oxide, and forming the first dielectric layer comprises performing a flowing chemical vapor deposition process. In some embodiments, the first dielectric layer comprises silicon nitride, and forming the first dielectric layer comprises performing an atomic layer deposition process to form a first silicon nitride layer and performing a flowing chemical vapor deposition process to form a second silicon nitride layer on the first silicon nitride layer.

[0131] In another exemplary aspect, the present disclosure also provides a method for forming a semiconductor structure. The method includes the following operations. A first fin-shaped active region and a second fin-shaped active region are formed on a substrate, wherein the first fin-shaped active region and the second fin-shaped active region extend longitudinally along a first direction. A gate structure is formed on multiple channel regions of the first fin-shaped active region and the second fin-shaped active region, wherein the gate structure extends longitudinally along a second direction substantially perpendicular to the first direction. A groove is formed to divide the gate structure into two sections, wherein the groove extends longitudinally along the first direction and is disposed between the first fin-shaped active region and the second fin-shaped active region when viewed from above. An etching process is performed to expand the upper portion of the groove. A gate isolation structure is formed in the groove, wherein in a cross section cutting through the first fin-shaped active region, the second fin-shaped active region and the gate structure, the gate isolation structure is a T-shaped structure.

[0132] In some embodiments, before performing the etching process, the upper portion of the trench has a first width along the second direction, so that after performing the etching process, the upper portion of the trench has a second width along the second direction, and the second width is greater than the first width. In some embodiments, the ratio of the first width to the second width is between about 0.3 and about 0.8. In some embodiments, forming the gate isolation structure includes: before performing the etching process, forming a first dielectric structure to fill the bottom of the trench, and after performing the etching process, forming a second dielectric structure on the first dielectric structure to fill the remaining portion of the trench. In some embodiments, one of the first dielectric structure and the second dielectric structure includes a first dielectric layer extending along the side and bottom surface of the second dielectric layer, and the dielectric constant of the first dielectric layer is different from the dielectric constant of the second dielectric layer. In some embodiments, the method also includes: after forming the gate isolation structure, replacing the two sections of the gate structure with two gate stacks, respectively, wherein each of the two gate stacks includes a high-k dielectric layer and a work function layer disposed on the high-k dielectric layer.

[0133] In another exemplary aspect, the present disclosure also provides a semiconductor structure including a first transistor, a second transistor, and a gate isolation structure. The first transistor includes: a first gate structure on a first channel region, and a plurality of first source / drain features coupled to the first channel region and disposed near the first gate structure. The second transistor includes: a second gate structure on a second channel region, and a plurality of second source / drain features coupled to the second channel region and disposed near the second gate structure. The gate isolation structure is used to provide isolation between the first gate structure and the second gate structure and to be in direct contact with the first gate structure and the second gate structure, wherein in a cross section cutting through the first gate structure, the second gate structure, the first channel region, and the second channel region, the shape of the gate isolation structure includes a T-shape.

[0134] In some embodiments, the gate isolation structure includes a lower portion formed of a first dielectric material and an upper portion formed of a second dielectric material, and the composition of the first dielectric material is different from the composition of the second dielectric material. In some embodiments, the bottom surface of the upper portion of the gate isolation structure is on the top surface of the first channel region. In some embodiments, the width of the top surface of the gate isolation structure is less than the distance between the first channel region and the second channel region. In some embodiments, the gate isolation structure includes a first dielectric layer located at the lower portion of the gate isolation structure and a second dielectric layer located at the upper portion of the gate isolation structure, and a physical interface exists between the first dielectric layer and the second dielectric layer.

[0135] The present disclosure provides a semiconductor structure characterized by including a first semiconductor fin and a second semiconductor fin on a substrate, a first gate structure on the first semiconductor fin, a second gate structure on the second semiconductor fin, and a gate isolation structure between the first semiconductor fin and the second semiconductor fin and between the first gate structure and the second gate structure, wherein the gate isolation structure includes a first dielectric layer located at a lower portion of the gate isolation structure and a second dielectric layer located at an upper portion of the gate isolation structure, and the width of the second dielectric layer is greater than the width of the first dielectric layer. In some embodiments, the first dielectric layer includes a dielectric filling layer and a dielectric liner extending along the side and bottom surfaces of the dielectric filling layer. In some embodiments, the semiconductor structure also includes an isolation feature disposed between multiple bottom portions of the first semiconductor fin and the second semiconductor fin and in direct contact with the first semiconductor fin and the second semiconductor fin, and wherein the gate isolation structure extends into the isolation feature.

[0136] The present disclosure also provides a semiconductor structure, characterized by including a first fin-shaped active region and a second fin-shaped active region on a substrate, a first gate structure on a channel region of the first fin-shaped active region, a second gate structure on a channel region of the second fin-shaped active region, and a gate isolation structure between the first gate structure and the second gate structure and between the first fin-shaped active region and the second fin-shaped active region. The first fin-shaped active region and the second fin-shaped active region extend longitudinally along a first direction. The first gate structure extends longitudinally along a second direction substantially perpendicular to the first direction. The second gate structure extends longitudinally along the second direction. The gate isolation structure extends longitudinally along the first direction, wherein in a cross section cutting through the first fin-shaped active region, the second fin-shaped active region, the first gate structure, and the second gate structure, the gate isolation structure is a T-shaped structure. In some embodiments, the gate isolation structure includes a first dielectric structure located at a lower portion of the gate isolation structure and a second dielectric structure located at an upper portion of the gate isolation structure, and one of the first dielectric structure and the second dielectric structure includes a low-k dielectric layer and a high-k dielectric layer extending along a side and bottom surface of the low-k dielectric layer. In some embodiments, each of the first gate structure and the second gate structure includes a high-k dielectric layer and a work function layer disposed on the high-k dielectric layer.

[0137] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can perform various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A first semiconductor fin and a second semiconductor fin on a substrate; a first gate structure on the first semiconductor fin; a second gate structure on the second semiconductor fin; and A gate isolation structure is between the first semiconductor fin and the second semiconductor fin and between the first gate structure and the second gate structure, wherein the gate isolation structure includes a first dielectric layer located at a lower portion of the gate isolation structure and a second dielectric layer located at an upper portion of the gate isolation structure, and a width of the second dielectric layer is greater than a width of the first dielectric layer.

2. The semiconductor structure according to claim 1, wherein: The first dielectric layer comprises: a dielectric filling layer; and A dielectric liner extends along a side surface and a bottom surface of the dielectric filling layer.

3. The semiconductor structure according to claim 1, wherein: Also included is an isolation feature disposed between the bottom portions of the first semiconductor fin and the second semiconductor fin and in direct contact with the first semiconductor fin and the second semiconductor fin, and wherein the gate isolation structure extends into the isolation feature.

4. A semiconductor structure, characterized in that: include: A first fin-shaped active region and a second fin-shaped active region are on a substrate, and the first fin-shaped active region and the second fin-shaped active region extend longitudinally along a first direction; A first gate structure is on a channel region of the first fin-shaped active region, the first gate structure longitudinally extending along a second direction substantially perpendicular to the first direction; A second gate structure is on a channel region of the second fin-shaped active region, and the second gate structure extends longitudinally along the second direction; and A gate isolation structure is between the first gate structure and the second gate structure and between the first fin-shaped active region and the second fin-shaped active region, and the gate isolation structure extends longitudinally along the first direction, wherein in a cross-section cutting through the first fin-shaped active region, the second fin-shaped active region, the first gate structure and the second gate structure, the gate isolation structure is a T-shaped structure.

5. The semiconductor structure according to claim 4, characterized in that The gate isolation structure includes a first dielectric structure located at a lower portion of the gate isolation structure and a second dielectric structure located at an upper portion of the gate isolation structure, and one of the first dielectric structure and the second dielectric structure includes a low-k dielectric layer and a high-k dielectric layer extending along the side and bottom of the low-k dielectric layer.

6. The semiconductor structure according to claim 4, characterized in that Each of the first gate structure and the second gate structure includes a high-k dielectric layer and a work function layer disposed on the high-k dielectric layer.

7. A semiconductor structure, characterized in that: include: A first transistor comprising: a first gate structure on a first channel region; and a plurality of first source / drain features coupled to the first channel region and disposed proximate the first gate structure; a second transistor, comprising: a second gate structure on a second channel region; and a plurality of second source / drain features coupled to the second channel region and disposed adjacent the second gate structure; and A gate isolation structure is used to provide isolation between the first gate structure and the second gate structure and to be in direct contact with the first gate structure and the second gate structure, wherein in a cross-section cutting through the first gate structure, the second gate structure, the first channel region and the second channel region, a shape of the gate isolation structure includes a T-shape.

8. The semiconductor structure according to claim 7, wherein: The gate isolation structure includes a first dielectric layer located at a lower portion of the gate isolation structure and a second dielectric layer located at an upper portion of the gate isolation structure, and a physical interface exists between the first dielectric layer and the second dielectric layer.

9. The semiconductor structure according to claim 8, characterized in that A bottom surface of the upper portion of the gate isolation structure is on a top surface of the first channel region.

10. The semiconductor structure according to claim 8, wherein: A width of a top surface of the gate isolation structure is smaller than a distance between the first channel region and the second channel region.

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