Display device

Abstract

The utility model relates to a display device. The display device may include: a substrate; a light emitting element on the substrate; a first pixel electrode on one region of the light emitting element and electrically connected to the light emitting element; and a second pixel electrode on another region of the light emitting element and electrically connected to the light emitting element. The light emitting element may include: a first semiconductor layer, an active layer, and second and third semiconductor layers sequentially arranged along a first direction; and an insulating film covering outer surfaces of the first semiconductor layer, the active layer, and the second and third semiconductor layers. The opening of the insulating film exposes at least one side surface of the second semiconductor layer to the outside while passing through the insulating film. The second pixel electrode may be in contact with the second semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0028018 filed in the Korean Intellectual Property Office on March 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device and a method of manufacturing the display device. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Utility Model Content

[0005] Embodiments of the present disclosure provide a display device and a method for manufacturing the display device, which can reduce the contact resistance between the light-emitting element and the pixel electrode caused by the shape of the broken surface of the light-emitting element or reduce the electrical short circuit between the light-emitting element and the pixel electrode caused by the arrangement direction of the light-emitting element.

[0006] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate; a light-emitting element on the substrate; a first pixel electrode on one region of the light-emitting element, the first pixel electrode being electrically connected to the light-emitting element; and a second pixel electrode on another region of the light-emitting element, the second pixel electrode being electrically connected to the light-emitting element, wherein the light-emitting element comprises: a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer, arranged sequentially along a first direction; and an insulating film covering outer surfaces of the first semiconductor layer, the active layer, the second semiconductor layer and the third semiconductor layer, wherein an opening of the insulating film exposes at least one side surface of the second semiconductor layer to the outside while passing through the insulating film, and wherein the second pixel electrode is in contact with the second semiconductor layer.

[0007] The opening of the insulating film may not overlap the active layer and the third semiconductor layer in a plan view.

[0008] The opening of the insulating film may be closer to the third semiconductor layer than to the active layer.

[0009] The opening of the insulating film may be closer to the active layer than to the third semiconductor layer.

[0010] The first semiconductor layer may be a semiconductor layer doped with a p-type dopant, the second semiconductor layer may be a semiconductor layer doped with an n-type dopant, and the third semiconductor layer may be an undoped semiconductor layer.

[0011] The light emitting element may include a first end portion and a second end portion opposite to the first end portion. The first semiconductor layer of the light emitting element may be adjacent to the first end portion, and the third semiconductor layer of the light emitting element may be adjacent to the second end portion. The light emitting element may also include a fourth semiconductor layer arranged on the third semiconductor layer in the first direction, the fourth semiconductor layer being at the second end portion.

[0012] The fourth semiconductor layer may be a semiconductor layer doped with an n-type dopant.

[0013] The insulating film may include: a first insulating film surrounding an area of ​​the second semiconductor layer, the first semiconductor layer, and an outer surface of the active layer; and a second insulating film surrounding another area of ​​the second semiconductor layer, the third semiconductor layer, and an outer surface of the fourth semiconductor layer. The opening may be between the first insulating film and the second insulating film.

[0014] The first pixel electrode may be electrically connected to the first semiconductor layer while being in contact with the first end portion of the light emitting element. The second pixel electrode may be electrically connected to the second semiconductor layer while being in contact with the second semiconductor layer exposed through the opening.

[0015] The third semiconductor layer may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second pixel electrode may contact the fourth semiconductor layer at a second end portion of the light emitting element.

[0016] The first pixel electrode may be an anode electrode, and the second pixel electrode may be a cathode electrode.

[0017] In a cross-sectional view, the light emitting element may be inclined relative to the substrate.

[0018] The display device may further include an insulating pattern on the light emitting element. In a plan view, the first pixel electrode and the second pixel electrode may cover both ends of the insulating pattern, respectively. The insulating pattern may include an organic material.

[0019] The opening of the insulating film may not overlap with the insulating pattern in a plan view.

[0020] In a plan view, the first pixel electrode and the insulating pattern may overlap a portion of the second semiconductor layer of the light emitting element.

[0021] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided, the method comprising: forming a first alignment electrode and a second alignment electrode separated from each other on a substrate; forming a first insulating layer over the first alignment electrode and the second alignment electrode; aligning a light emitting element on the first insulating layer between the first alignment electrode and the second alignment electrode by forming an electric field between the first alignment electrode and the second alignment electrode; forming an insulating pattern on a region of the light emitting element; forming an opening in an insulating film of the light emitting element by etching a portion of an outer surface of the light emitting element adjacent to the second pixel electrode; and forming a first pixel electrode in contact with a first end portion of the light emitting element and a second pixel electrode in contact with a second end portion of the light emitting element.

[0022] The second pixel electrode may be in contact with the second semiconductor layer of the light emitting element.

[0023] The light emitting element may include a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer sequentially arranged along a first direction. An insulating film may cover outer surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer. The first semiconductor layer may be a semiconductor layer doped with a p-type dopant, the second semiconductor layer may be a semiconductor layer doped with an n-type dopant, and the third semiconductor layer may be an undoped semiconductor layer. Forming the opening may include removing the insulating film surrounding at least one side surface of the second semiconductor layer.

[0024] The light emitting element may further include a fourth semiconductor layer arranged on the third semiconductor layer in the first direction, the fourth semiconductor layer being at the second end portion. In a plan view, the opening may not overlap with the insulating pattern. The fourth semiconductor layer may be a semiconductor layer doped with an n-type dopant.

[0025] In the display device and the method for manufacturing the display device according to the present disclosure, the light-emitting element and the pixel electrode are electrically connected to each other through an opening formed at the side surface portion of the light-emitting element, thereby reducing (or minimizing) the contact resistance between the light-emitting element and the pixel electrode caused by the shape of the broken surface of the light-emitting element.

[0026] In addition, in the display device and the method for manufacturing the display device according to the present disclosure, since another semiconductor layer is included for blocking the current between the semiconductor layers, an electrical short circuit phenomenon that may occur when the alignment direction of the light-emitting element is in the reverse direction (for example, the non-light-emitting state of the light-emitting element) can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Now, exemplary embodiments will be described more fully below with reference to the accompanying drawings. However, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always refer to the same elements.

[0029] Figure 1 is a perspective cross-sectional view showing a light emitting element according to one or more embodiments of the present disclosure.

[0030] Figure 2 It is shown Figure 1 sectional view of an example of a light emitting element shown in .

[0031] Figure 3 is a schematic plan view showing a display device according to one or more embodiments of the present disclosure.

[0032] Figure 4 It is shown that the Figure 3 A circuit diagram of an example of a sub-pixel in a display device shown in FIG.

[0033] Figure 5 It is shown that the Figure 3 A schematic plan view of an example of a sub-pixel in a display device shown in FIG.

[0034] Figure 6 It is shown along Figure 5 Schematic cross-sectional view of an example of a sub-pixel taken along line II′ shown in FIG.

[0035] Figure 7 and Figure 8 It shows that the setting Figure 3 A cross-sectional view of an example of a light emitting element in a display device shown in FIG.

[0036] Fig. 9 It is shown Figure 6 An enlarged view of an embodiment of region A is shown in FIG.

[0037] Fig.10 It is shown Figure 6 An enlarged view of another embodiment of area A is shown in FIG.

[0038] Fig.11 It is shown that the Figure 3A cross-sectional view of a pixel in the display device shown in FIG.

[0039] Figures 12 to 17 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In all drawings, the same reference numerals are given to the same elements, and their repeated description will be omitted.

[0041] Figure 1 is a perspective cross-sectional view showing a light emitting element according to one or more embodiments of the present disclosure. Figure 2 It is shown Figure 1 sectional view of an example of a light emitting element shown in .

[0042] refer to Figure 1 and Figure 2 The light emitting element LD is configured to emit light. For example, the light emitting element LD may be a light emitting diode including an inorganic material.

[0043] The light emitting element LD may include a first semiconductor layer SEC1, an active layer AL, a second semiconductor layer SEC2a, a third semiconductor layer SEC3, a fourth semiconductor layer SEC2b, and an electrode layer EL. For example, when it is assumed that the extension direction of the light emitting element LD is the length L direction, the light emitting element LD may be implemented as a light emitting stack structure (or stack pattern) in which the electrode layer EL, the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2a, the third semiconductor layer SEC3, and the fourth semiconductor layer SEC2b are sequentially stacked in the length L direction. The light emitting element LD may further include an insulating film INF.

[0044] In one or more embodiments, the electrode layer EL may be omitted. The light emitting element LD may include a first semiconductor layer SEC1, an active layer AL, a second semiconductor layer SEC2a, a third semiconductor layer SEC3, and a fourth semiconductor layer SEC2b sequentially stacked in a length L direction.

[0045] The light emitting element LD may be provided in a shape extending in one direction. The light emitting element LD may include a first end portion EP1 and a second end portion EP2 along a length L direction. The first semiconductor layer SEC1 may be adjacent to the first end portion EP1 of the light emitting element LD, and the fourth semiconductor layer SEC2b may be adjacent to the second end portion EP2. The electrode layer EL may be adjacent to the first end portion EP1.

[0046] The light emitting element LD can be arranged in various shapes. In the example, Figure 1As shown in , the light emitting element LD may have a rod-like shape, a stick-like shape, a column-like shape, etc. in which the length L direction thereof is long (or its aspect ratio is greater than 1). In another example, the light emitting element LD may have a rod-like shape, a stick-like shape, a column-like shape, etc. in which the length L direction thereof is short (or its aspect ratio is less than 1). In yet another example, the light emitting element LD may have a rod-like shape, a stick-like shape, a column-like shape, etc. in which the aspect ratio is 1.

[0047] The light emitting element LD may include, for example, a light emitting diode (LED) manufactured small enough to have a diameter D and / or a length L in the range of nanometer order (or nanometer) to micrometer order (micrometer).

[0048] When the light emitting element LD is long in the direction of its length L (i.e., when its aspect ratio is greater than 1), the diameter D of the light emitting element LD may be about 0.5 μm to about 6 μm, and the length L of the light emitting element LD may be about 1 μm to about 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto, and the size of the light emitting element LD may be changed according to the required conditions (or design conditions) of the lighting device or the self-luminous display device to which the light emitting element LD is applied.

[0049] In one or more embodiments, the electrode layer EL may include a metal or a conductive metal oxide, and may be formed using, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and any oxide or alloy thereof, one or a mixture thereof, a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). The electrode layer EL may be substantially transparent. Therefore, light generated in the light emitting element LD is transmitted through the electrode layer EL, thereby being emitted to the outside of the light emitting element LD.

[0050] In one or more embodiments, the electrode layer EL may include a lower surface on which the first semiconductor layer SEC1 is disposed and a first surface exposed to the outside in the length L direction. The electrode layer EL may be a first end portion EP1 (or top end portion) of the light emitting element LD and may be disposed on the first semiconductor layer SEC1.

[0051] The first semiconductor layer SEC1 may include, for example, at least one p-type semiconductor layer. For example, the first semiconductor layer SEC1 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a first conductive type dopant such as Mg. The first semiconductor layer SEC1 may include an upper surface in contact with the electrode layer EL in the length L direction of the light emitting element LD and a lower surface in contact with the active layer AL. The electrode layer EL may be disposed on the upper surface of the first semiconductor layer SEC1 at one end portion (or top portion) of the light emitting element LD.

[0052] The active layer AL may be disposed between the first semiconductor layer SEC1 and the second semiconductor layer SEC2a, and may be formed as a single quantum well structure or a multi-quantum well structure. In the example, when the active layer AL is formed as a multi-quantum well structure, the barrier layer, the strain enhancement layer, and the well layer constituting one unit may be periodically and repeatedly stacked in the active layer AL. The strain enhancement layer may have a lattice constant smaller than that of the barrier layer, thereby further enhancing strain, for example, compressive strain applied to the well layer. However, the structure of the active layer AL is not limited to the above-described embodiments.

[0053] A cladding layer doped with a conductive dopant and / or a tensile strain barrier reduction (TSBR) layer may be further disposed on the top and / or bottom of the active layer AL. For example, the cladding layer may be formed of an AlGaN layer or an AlInGaN layer. The TSBR layer may be a strain reduction layer disposed between semiconductor layers having different lattice structures to perform a reduction function for reducing the lattice constant difference. The TSBR layer may be configured with a p-type semiconductor layer such as p-GaInP, p-AlInP or p-AlGaInP, but the present disclosure is not limited thereto.

[0054] The active layer AL may emit light having a wavelength of about 400 nm to about 900 nm and use a double heterostructure. The active layer AL may include a first surface contacting the first semiconductor layer SEC1 and a second surface contacting the second semiconductor layer SEC2a.

[0055] The color (or luminescent color) of the light emitting element LD may be determined according to the wavelength of light emitted in the active layer AL. The color of the light emitting element LD may determine the color of the pixel corresponding thereto. For example, the light emitting element LD may emit red light, green light, or blue light.

[0056] When an electric field having an appropriate voltage (e.g., a predetermined voltage) or more is applied to both end portions of the light emitting element LD, the light emitting element LD emits light when electron-hole pairs are recombined in the active layer AL. By using this principle to control the light emission of the light emitting element LD, the light emitting element LD can be used as a light source (or light emitting source) of various light emitting devices including pixels of a display device.

[0057] The second semiconductor layer SEC2a (or the (2-1)th semiconductor layer) may be disposed on the second surface of the active layer AL, and may include a semiconductor layer having a type different from that of the first semiconductor layer SEC1. In the example, the second semiconductor layer SEC2a may include at least one n-type semiconductor layer. The second semiconductor layer SEC2a may include any semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN and InN, and may include an n-type semiconductor layer doped with a second conductive type dopant such as Si, Ge or Sn. However, the material used to form the second semiconductor layer SEC2a is not limited thereto. In addition, the second semiconductor layer SEC2a may be configured with various materials.

[0058] The second semiconductor layer SEC2 a may include an upper surface in contact with the second surface of the active layer AL and a lower surface in contact with the third semiconductor layer SEC3 .

[0059] The first semiconductor layer SEC1 and the second semiconductor layer SEC2a may have different thicknesses in the length L direction of the light emitting element LD. In an example, the second semiconductor layer SEC2a may have a relatively thicker thickness than the first semiconductor layer SEC1 along the length L direction of the light emitting element LD. Therefore, the active layer AL of the light emitting element LD may be positioned closer to the upper surface of the first semiconductor layer SEC1 than the lower surface of the second semiconductor layer SEC2a.

[0060] The third semiconductor layer SEC3 may be disposed between the second semiconductor layer SEC2a and the fourth semiconductor layer SEC2b. The third semiconductor layer SEC3 may prevent current from flowing from the second semiconductor layer SEC2a to the second end portion EP2. In addition, the third semiconductor layer SEC3 may prevent the current applied by the fourth semiconductor layer SEC2b at the second end portion EP2 from flowing into the second semiconductor layer SEC2a. The third semiconductor layer SEC3 may be a semiconductor layer not doped with a dopant. The third semiconductor layer SEC3 may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN or InN. The third semiconductor layer SEC3 may include a material having a higher band gap than each of the second semiconductor layer SEC2a and the fourth semiconductor layer SEC2b. Therefore, the electrons injected into the third semiconductor layer SEC3 may be prevented from flowing into the second semiconductor layer SEC2a and the fourth semiconductor layer SEC2b.

[0061] The third semiconductor layer SEC3 may include a first surface in contact with the second semiconductor layer SEC2 a and a second surface in contact with the fourth semiconductor layer SEC2 b .

[0062] The second semiconductor layer SEC2a and the third semiconductor layer SEC3 may have different thicknesses in the length L direction of the light emitting element LD. In an example, the second semiconductor layer SEC2a may have a thickness relatively thicker than that of the third semiconductor layer SEC3. In an example, the third semiconductor layer SEC3 may have substantially the same thickness as the first semiconductor layer SEC1 in the length L direction, but the present disclosure is not limited thereto.

[0063] The fourth semiconductor layer SEC2b (or the (2-2)th semiconductor layer) may include a first surface (upper surface) on which the third semiconductor layer SEC3 is disposed and a second surface (lower surface) exposed to the outside in the direction of the length L. The fourth semiconductor layer SEC2b may be the second end portion EP2 (or bottom end portion) of the light emitting element LD.

[0064] The fourth semiconductor layer SEC2b may include at least one n-type semiconductor layer. The fourth semiconductor layer SEC2b may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN and InN, and includes an n-type semiconductor layer doped with a second conductive type dopant such as Si, Ge or Sn. However, the material used to form the fourth semiconductor layer SEC2b is not limited thereto. In addition, the fourth semiconductor layer SEC2b can be configured with various materials.

[0065] The insulating film INF (or the insulating film INF of the light emitting element LD) may be disposed on the surface of the light emitting element LD. The insulating film INF may be disposed and / or formed around the outer surfaces (e.g., peripheral surfaces or outer circumferential surfaces) of the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2a, the third semiconductor layer SEC3, and the fourth semiconductor layer SEC2b (e.g., surrounding the outer surfaces (e.g., peripheral surfaces or outer circumferential surfaces) of the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2a, the third semiconductor layer SEC3, and the fourth semiconductor layer SEC2b).

[0066] The insulating film INF may expose each of the first end portion EP1 and the second end portion EP2 of the light emitting element LD. In an example, one region of the electrode layer EL corresponding to the first end portion EP1 may be exposed from the insulating film INF.

[0067] exist Figure 1 and Figure 2 In the above description, the outer surface (e.g., outer peripheral surface or outer circumferential surface) of the light emitting stack structure in which the insulating film INF completely surrounds the light emitting element LD is described. However, the present disclosure is not limited thereto. For example, one side surface of the second semiconductor layer SEC2a may be formed through an opening (e.g., Fig. 9 The opening OP1 shown in FIG. 1 is exposed to the outside.

[0068] The insulating film INF may include a transparent insulating material. For example, the insulating film INF may include a material selected from silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium dioxide (TiO 2 ), hafnium oxide (HfO x ), strontium titanium oxide (SrTiO x ), cobalt oxide (Co x O y ), magnesium oxide (MgO), zinc oxide (ZnO), ruthenium oxide (RuO x ), nickel oxide (NiO), tungsten oxide (WO x ), tantalum oxide (TaO x ), Gadolinium oxide (GdO x )、ZrO x ), gallium oxide (GaO x ), vanadium oxide (V x O y )、ZnO:Al、ZnO:B、In x O y:H, niobium oxide (Nb x O y ), magnesium fluoride (MgF x ), aluminum fluoride (AlF x ), aluminum cone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN x ), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), vanadium nitride (VN), etc. At least one insulating material selected from the group consisting of. However, the present disclosure is not limited thereto, and various materials having insulating properties may be used as the material of the insulating film INF.

[0069] Figure 3 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0070] exist Figure 3 , the structure of the display panel DP will be briefly illustrated based on the display area DA. However, in some embodiments, at least one driving circuit (e.g., at least one of a scan driver and a data driver), a line and / or a pad not shown may be further provided in the display panel DP.

[0071] The present disclosure can be applied as long as the display device DD is an electronic device in which a display surface is applied to at least one surface thereof, such as a smart phone, a TV, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a net-book computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device.

[0072] refer to Figure 3 , the display panel DP may include a substrate SUB (or base layer) and pixels PXL disposed on the substrate SUB.

[0073] The display panel DP may have various shapes. In an example, the display panel DP may be provided in a rectangular plate shape, but the present disclosure is not limited thereto. For example, the display panel DP may have a shape such as a circular shape or an elliptical shape. In addition, the display panel DP may include an angled corner and / or a curved corner. For convenience, in Figure 3 In FIG. 1 , it is shown that the display panel DP has a rectangular plate shape. Figure 3 In the embodiment, the extending direction of the short side of the display panel DP (eg, the transverse direction) is designated as the first direction DR1, and the extending direction of the long side of the display panel DP (eg, the longitudinal direction) is designated as the second direction DR2. The thickness direction of the display panel DP is designated as the third direction DR3.

[0074] The substrate SUB is used to constitute the basic component of the display panel DP, and can be a rigid substrate or film or a flexible substrate or film. In an example, the substrate SUB can be configured as a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one insulating layer. The material and / or properties of the substrate SUB are not particularly limited.

[0075] The substrate SUB (and the display panel DP) may include a display area DA for displaying an image and a non-display area NDA provided in addition to the display area DA and along an edge or periphery of the display area DA. The display area DA may constitute a screen on which an image is displayed, and the non-display area NDA may be located at least on one side of the display area DA. For example, the non-display area NDA may surround the display area DA, but the present disclosure is not limited thereto.

[0076] The pixels PXL may be disposed in the display area DA on the substrate SUB. The non-display area NDA may be disposed at the periphery of the display area DA. Various lines, pads, and / or built-in circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0077] In the embodiments of the present disclosure, the term "connection (or access)" may include meaning physical connection (or access) and / or electrical connection (or access). In addition, this may include meaning direct connection (or access) or indirect connection (or access) and integral connection (or access) or non-integrated connection (or access).

[0078] The pixel PXL may include sub-pixels SPXL1 to SPXL3. For example, the pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0079] Each of the sub-pixels SPXL1 to SPXL3 may emit light of a desired color (e.g., a predetermined color). In one or more embodiments, the sub-pixels SPXL1 to SPXL3 may emit light of different colors. In an example, the first sub-pixel SPXL1 may emit light of a first color, the second sub-pixel SPXL2 may emit light of a second color, and the third sub-pixel SPXL3 may emit light of a third color. For example, the first sub-pixel SPXL1 may be a red pixel that emits red light, the second sub-pixel SPXL2 may be a green pixel that emits green light, and the third sub-pixel SPXL3 may be a blue pixel that emits blue light. However, the present disclosure is not limited thereto.

[0080] The first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may have a light-emitting element of a first color, a light-emitting element of a second color, and a light-emitting element of a third color as light sources to emit light of a first color, light of a second color, and light of a third color, respectively. In one or more embodiments, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may have a light-emitting element that emits light of the same color, and include a color conversion layer and / or a color filter of different colors disposed above each light-emitting element to emit light of a first color, light of a second color, and light of a third color, respectively. However, the color, kind (or type), and / or number of the sub-pixels SPXL1 to SPXL3 constituting each pixel PXL are not particularly limited. That is, the color of the light emitted by each pixel PXL can be variously changed.

[0081] The sub-pixels SPXL1 to SPXL3 can be configured according to the stripe structure, The structure is arranged regularly. The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). is a registered trademark of Samsung Display Co., Ltd. of South Korea. For example, the sub-pixels SPXL1, SPXL2 and SPXL3 may be sequentially and repeatedly arranged along the first direction DR1. In addition, the first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 may be repeatedly arranged along the second direction DR2. At least one first sub-pixel SPXL1, at least one second sub-pixel SPXL2 and at least one third sub-pixel SPXL3 arranged adjacent to each other may constitute a pixel PXL capable of emitting light of various colors. However, the arrangement structure of the sub-pixels SPXL1 to SPXL3 is not limited thereto, and the sub-pixels SPXL1 to SPXL3 may be arranged in the display area DA in various structures and / or in various ways.

[0082] Each of the sub-pixels SPXL1 to SPXL3 can be configured as an effective pixel. For example, each of the sub-pixels SPXL1 to SPXL3 may include at least one light source (e.g., at least one light-emitting element) driven by an appropriate control signal (e.g., a predetermined control signal, such as a scan signal and a data signal) and / or an appropriate power supply (e.g., a predetermined power supply, such as a first power supply and a second power supply). However, the kind (or type), structure and / or driving method of the sub-pixels SPXL1 to SPXL3 that can be applied to the display device DD are not particularly limited.

[0083] Hereinafter, when the first subpixel SPXL1, the second subpixel SPXL2 and the third subpixel SPXL3 are inclusively specified, each of the first subpixel SPXL1, the second subpixel SPXL2 and the third subpixel SPXL3 or the first subpixel SPXL1, the second subpixel SPXL2 and the third subpixel SPXL3 will be referred to as a subpixel SPXL.

[0084] Figure 4 It is shown that the Figure 3 A circuit diagram of an example of a sub-pixel in a display device shown in FIG.

[0085] refer to Figures 1 to 4 The sub-pixel SPXL may include a light emitting unit EMU that generates light having brightness corresponding to the data signal. In addition, the sub-pixel SPXL may selectively further include a pixel circuit PXC for driving the light emitting unit EMU.

[0086] The light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2, the first power line PL1 being connected to a first driving power source VDD to which a voltage of the first driving power source VDD is applied, and the second power line PL2 being connected to a second driving power source VSS to which a voltage of the second driving power source VSS is applied. For example, the light emitting unit EMU may include a first connection electrode ELT1 connected to the first driving power source VDD via a pixel circuit PXC and the first power line PL1, a second connection electrode ELT2 connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel between the first connection electrode ELT1 and the second connection electrode ELT2 in the same direction. In one or more embodiments, the first connection electrode ELT1 may be an anode, and the second connection electrode ELT2 may be a cathode.

[0087] Each of the light emitting elements LD included in the light emitting unit EMU may include an end portion connected to a first driving power source VDD through a first connection electrode ELT1 and another end portion connected to a second driving power source VSS through a second connection electrode ELT2. The first driving power source VDD and the second driving power source VSS may have different potentials. In an example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. During the emission period of the sub-pixel SPXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0088] As described above, the light emitting element LD connected in parallel between the first connection electrode ELT1 and the second connection electrode ELT2 supplied with voltages having different potentials in the same direction (eg, forward direction) may form a corresponding effective light source.

[0089] In one or more embodiments, each of the light emitting elements LD of the light emitting unit EMU may emit light having a brightness corresponding to the driving current provided by the corresponding pixel circuit PXC. For example, the pixel circuit PXC may provide a driving current corresponding to the grayscale value of the corresponding frame data to the light emitting unit EMU during each frame period. The driving current provided to the light emitting unit EMU may be shunted to flow through each of the light emitting elements LD. Therefore, the light emitting unit EMU may emit light having a brightness corresponding to the driving current while each light emitting element LD emits light having a brightness corresponding to the current flowing therethrough.

[0090] Although the case where the two end portions of the light-emitting element LD are connected between the first driving power source VDD and the second driving power source VSS in the same direction has been described in the above-mentioned embodiments, the present disclosure is not limited thereto. In one or more embodiments, in addition to the light-emitting element LD forming the corresponding effective light source, the light-emitting unit EMU may further include at least one invalid light source, for example, a reverse light-emitting element LDr. The reverse light-emitting element LDr is connected in parallel with the light-emitting element LD forming the effective light source between the first connection electrode ELT1 and the second connection electrode ELT2, and may be connected between the first connection electrode ELT1 and the second connection electrode ELT2 in a direction opposite to the direction in which the light-emitting element LD is connected. Although a predetermined driving voltage (for example, a forward driving voltage) is applied between the first connection electrode ELT1 and the second connection electrode ELT2, the reverse light-emitting element LDr remains in an unactivated state, and therefore, substantially no current flows through the reverse light-emitting element LDr.

[0091] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the sub-pixel SPXL. In addition, the pixel circuit PXC may be connected to the control line CLi and the sensing line SENj of the sub-pixel SPXL. In an example, when the sub-pixel SPXL is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the sub-pixel SPXL may be connected to the i-th scan line Si, the j-th data line Dj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA.

[0092] The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0093] The first transistor T1 is a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between the first driving power supply VDD and the light emitting unit EMU. Specifically, the first terminal of the first transistor T1 may be connected (or coupled) to the first driving power supply VDD via the first power line PL1, the second terminal of the first transistor T1 may be connected to the second node N2, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light emitting unit EMU from the first driving power supply VDD via the second node N2 according to the voltage applied to the first node N1. In one or more embodiments, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode. However, the present disclosure is not limited thereto. In one or more embodiments, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0094] The second transistor T2 is a switching transistor that selects the sub-pixel SPXL in response to the scan signal and activates the sub-pixel SPXL, and can be connected between the data line Dj and the first node N1. The first terminal of the second transistor T2 can be connected to the data line Dj, the second terminal of the second transistor T2 can be connected to the first node N1, and the gate electrode of the second transistor T2 can be connected to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is a drain electrode, the second terminal can be a source electrode.

[0095] When a scan signal having a gate-on voltage (e.g., a high level voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj and the first node N1 to each other. The first node N1 is a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other, and the second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0096] The third transistor T3 connects the first transistor T1 to the sensing line SENj to obtain a sensing signal through the sensing line SENj, and detects the characteristics of the sub-pixel SPXL (including the threshold voltage of the first transistor T1, etc.) by using the sensing signal. Information about the characteristics of the sub-pixel SPXL can be used to convert image data, so that the characteristic deviation between the sub-pixels SPXL can be compensated. The second terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1 and the second node N2, the first terminal of the third transistor T3 can be connected to the sensing line SENj, and the gate electrode of the third transistor T3 can be connected to the control line CLi. In addition, the first terminal of the third transistor T3 can be connected to the initialization power supply. The third transistor T3 is an initialization transistor capable of initializing the second node N2. When a sensing control signal is provided from the control line CLi, the third transistor T3 can be turned on to transmit the voltage of the initialization power supply to the second node N2. Therefore, the second storage electrode of the storage capacitor Cst connected to the second node N2 can be initialized.

[0097] A first storage electrode of the storage capacitor Cst may be connected to the first node N1, and a second storage electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst charges a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0098] Although already Figure 4 , an embodiment in which all the light-emitting elements LD constituting the light-emitting unit EMU are connected in parallel is shown, but the present disclosure is not limited thereto. In one or more embodiments, the light-emitting unit EMU may be configured to include at least one series stage (or at least one stage), and at least one series stage (or at least one stage) includes a plurality of light-emitting elements LD connected in parallel to each other. That is, the light-emitting unit EMU may be configured as a series / parallel hybrid structure.

[0099] Although already Figure 4 , the transistors T1 to T3 included in the pixel circuit PXC are all n-type transistors, but the present disclosure is not necessarily limited thereto. For example, at least one of the transistors T1 to T3 may be changed to a p-type transistor.

[0100] In addition, the structure and driving method of the sub-pixel SPXL can be changed in various ways. Figure 4 In addition to the embodiment shown in , the pixel circuit PXC may be configured as a pixel circuit having various structures and / or various driving methods.

[0101] Figure 5 It is shown that the Figure 3 A schematic plan view of an example of a sub-pixel in a display device shown in FIG. Figure 5 is a view showing some components included in the sub-pixel SPXL.

[0102] refer to Figure 5 The sub-pixel SPXL may include a bank BNK, first and second pixel electrodes ELT1 and ELT2, first and second alignment electrodes ALE1 and ALE2, first and second connection electrodes CNL1 and CNL2, and a light emitting element LD.

[0103] The bank BNK may separate the sub-pixels SPXL, and the emission area EMA may correspond to an opening defined by the bank BNK. In an example, the bank BNK may form a space in which a fluid may be accommodated. For example, during a manufacturing process, ink including a light emitting element LD may be provided in the space in which a fluid may be accommodated.

[0104] The non-emission area NEA may be a region substantially corresponding to the bank BNK. When viewed on a plane (eg, in a plan view), the bank BNK may surround the emission area EMA.

[0105] The subpixel SPXL may include a first alignment electrode ALE1 and a second alignment electrode ALE2. In an example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be used as electrodes for aligning the light emitting element LD and electrodes for applying an appropriate voltage (eg, a predetermined voltage).

[0106] The first and second alignment electrodes ALE1 and ALE2 may extend in the second direction DR2 and may be disposed to be spaced apart from each other in the first direction DR1.

[0107] The first connection electrode CNL1 may be disposed in the same layer as the first alignment electrode ALE1 to be integrally formed. The second connection electrode CNL2 may be disposed in the same layer as the second alignment electrode ALE2 to be integrally formed.

[0108] The first alignment electrode ALE1 and the second alignment electrode ALE2 may serve as alignment electrodes of the light emitting element LD. For example, the light emitting element LD may be arranged based on an electrical signal supplied to the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0109] The light emitting elements LD may be arranged in a parallel structure along the second direction DR2. The arrangement structure of the light emitting elements LD is not limited thereto.

[0110] When viewed on a plane (eg, in a plan view), the light emitting element LD may be disposed between (or on) the first alignment electrode ALE1 and the second alignment electrode ALE2 .

[0111] In one or more embodiments, when viewed on a plane (e.g., in a plan view), the first pixel electrode ELT1 may be disposed on the first alignment electrode ALE1 to be electrically connected to the first alignment electrode ALE1. When viewed on a plane (e.g., in a plan view), the second pixel electrode ELT2 may be disposed on the second alignment electrode ALE2 to be electrically connected to the second alignment electrode ALE2.

[0112] The light emitting element LD may be electrically connected to the first alignment electrode ALE1 through the first pixel electrode ELT1 , and electrically connected to the second alignment electrode ALE2 through the second pixel electrode ELT2 .

[0113] The first end portion of the light emitting element LD (eg, Figure 1 , the first end portion EP1 (or the second end portion (eg, Figure 1 The second end portion EP2 shown in FIG. 1 may be electrically connected to the first pixel electrode ELT1. The second end portion EP2 (or the first end portion EP1) of the light emitting element LD may be electrically connected to the second pixel electrode ELT2.

[0114] The first semiconductor layer (eg, Figure 1 , the first semiconductor layer SEC1 (eg, via the electrode layer EL)) or the fourth semiconductor layer (eg, Figure 1 The fourth semiconductor layer SEC2b) shown in FIG. 4 may be electrically connected to the first pixel electrode ELT1.

[0115] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be electrically connected to the pixel circuit PXC and / or the power line. For example, the first alignment electrode ALE1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 through a first contact portion CNT1 formed to overlap the first connection electrode CNL1, and the second alignment electrode ALE2 may be electrically connected to the pixel circuit PXC and / or the second power line PL2 through a second contact portion CNT2 formed to overlap the second connection electrode CNL2.

[0116] exist Figure 5, it is shown that the first pixel electrode ELT1 is connected to the first power line PL1 through the first alignment electrode ALE1, and the second pixel electrode ELT2 is connected to the second power line PL2 through the second alignment electrode ALE2. However, the present disclosure is not limited thereto. For example, the first pixel electrode ELT1 is not connected to the first power line PL1 through the first alignment electrode ALE1, but can be directly connected to the first power line PL1 through a separate contact portion. In one or more embodiments, the second pixel electrode ELT2 is not connected to the second power line PL2 through the second alignment electrode ALE2, but can be directly connected to the second power line PL2 through a separate contact portion.

[0117] When the light emitting element LD is provided in the sub-pixel SPXL, the light emitting element LD may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the forward direction, or may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the reverse direction. When the light emitting element LD is arranged in the forward direction, the light emitting element LD may constitute an effective light source. When the light emitting element LD is arranged in the reverse direction, the light emitting element LD may constitute an ineffective light source.

[0118] In this specification, the state in which the light emitting element LD is arranged in the forward direction refers to the first semiconductor layer SEC1 (see Figure 1 ) (eg, via the electrode layer EL) is electrically connected to the first pixel electrode ELT1 and the fourth semiconductor layer SEC2b (see Figure 2 ) is electrically connected to the second pixel electrode ELT2, and a state in which the light emitting element LD is arranged in the reverse direction refers to a state in which the fourth semiconductor layer SEC2b is electrically connected to the first pixel electrode ELT1 and the first semiconductor layer SEC1 (for example, via the electrode layer EL) is electrically connected to the second pixel electrode ELT2.

[0119] Figure 6 It is shown along Figure 5 Schematic cross-sectional view of an example of a sub-pixel taken along line II′ shown in FIG.

[0120] refer to Figures 4 to 6 The sub-pixel SPXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL. Hereinafter, for the convenience of description, the first transistor T1 among the first to third transistors T1 to T3 will be mainly described.

[0121] The substrate SUB may constitute a base member of the display device DD. The substrate SUB may be a rigid substrate or film or a flexible substrate or film, but the present disclosure is not limited to a specific example. In an example, the substrate SUB may include polyimide. The substrate SUB may be provided as a base surface so that the pixel circuit layer PCL and the display element layer DPL are provided on the substrate SUB.

[0122] The pixel circuit layer PCL may be disposed on the substrate SUB. The pixel circuit layer PCL may include a lower electrode layer BML, a buffer layer BFL, a first transistor T1, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a bridge pattern BRP, a second power line PL2, a protection layer PSV, a first contact portion CNT1, and a second contact portion CNT2.

[0123] The lower electrode layer BML may be disposed on the substrate SUB to be covered by the buffer layer BFL. When viewed on a plane (eg, in a plan view) or in a thickness direction (eg, a third direction DR3) of the substrate SUB, a portion of the lower electrode layer BML may overlap the first transistor T1.

[0124] The lower electrode layer BML may include a conductive material so as to serve as a path through which an electrical signal provided to the pixel circuit layer PCL and the display element layer DPL moves. For example, the lower electrode layer BML may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0125] The buffer layer BFL may be disposed on the substrate SUB and cover the lower electrode layer BML. The buffer layer BFL may prevent impurities from diffusing from the outside. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ) is at least one of the metal oxides.

[0126] The first transistor T1 may be electrically connected to the light emitting element LD. The first transistor T1 may be electrically connected to the bridge pattern BRP. However, the present disclosure is not limited to the above example. The first transistor T1 may be directly connected to the first connection electrode CNL1 without passing through the bridge pattern BRP.

[0127] The first transistor T1 may include an active layer ACT, a first transistor electrode TE1, a second transistor electrode TE2, and a gate electrode GE.

[0128] The active layer ACT may be a semiconductor layer. The active layer ACT may be disposed on the buffer layer BFL. For example, the active layer ACT may include at least one of low temperature polysilicon (LTPS), polysilicon, amorphous silicon, and an oxide semiconductor.

[0129] The active layer ACT may include a first contact region contacting the first transistor electrode TE1 and a second contact region contacting the second transistor electrode TE2. The first contact region and the second contact region may correspond to a semiconductor pattern doped with impurities. The region between the first contact region and the second contact region may be a channel region. The channel region may correspond to an intrinsic semiconductor pattern not doped with impurities.

[0130] The gate electrode GE may be disposed on the gate insulating layer GI. The position of the gate electrode GE may correspond to the position of the channel region of the active layer ACT. For example, the gate electrode GE may be disposed on the channel region of the active layer ACT with the gate insulating layer GI interposed therebetween. In an example, the gate electrode GE may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0131] The gate insulating layer GI may be disposed on the active layer ACT and the buffer layer BFL. The gate insulating layer GI may include an inorganic material. In an example, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0132] The first interlayer insulating layer ILD1 may be located on the gate electrode GE and the gate insulating layer GI. Similar to the gate insulating layer GI, the first interlayer insulating layer ILD1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0133] The first transistor electrode TE1 and the second transistor electrode TE2 may be located on the first interlayer insulating layer ILD1. The first transistor electrode TE1 may contact the first contact region of the active layer ACT while passing through the gate insulating layer GI and the first interlayer insulating layer ILD1, and the second transistor electrode TE2 may contact the second contact region of the active layer ACT while passing through the gate insulating layer GI and the first interlayer insulating layer ILD1. In an example, the first transistor electrode TE1 may be a drain electrode, and the second transistor electrode TE2 may be a source electrode. However, the present disclosure is not limited thereto.

[0134] The second interlayer insulating layer ILD2 may be located over the first and second transistor electrodes TE1 and TE2 and the first interlayer insulating layer ILD1. Like the first interlayer insulating layer ILD1 and the gate insulating layer GI, the second interlayer insulating layer ILD2 may include an inorganic material. The inorganic material may include at least one of the materials exemplified as the materials constituting the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0135] The bridge pattern BRP may be disposed on the second interlayer insulating layer ILD2. The bridge pattern BRP may be connected to the first transistor electrode TE1 through a contact hole passing through the second interlayer insulating layer ILD2. The bridge pattern BRP may be electrically connected to the first connection electrode CNL1 through a first contact portion CNT1 formed in the protection layer PSV.

[0136] The second power line PL2 may be disposed on the second interlayer insulating layer ILD2. The second power line PL2 may be electrically connected to the second connection electrode CNL2 through a second contact portion CNT2 formed in the protective layer PSV. The second power line PL2 may provide a voltage of a second power source (or a cathode signal) to the light emitting element LD through the second pixel electrode ELT2.

[0137] The protective layer PSV may be located on the second interlayer insulating layer ILD2. The protective layer PSV may cover the bridge pattern BRP and the second power line PL2 and the second interlayer insulating layer ILD2. The protective layer PSV may be a through-hole layer. The protective layer PSV may be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer, but the present disclosure is not limited thereto.

[0138] A first contact portion CNT1 connected to one region of the bridge pattern BRP and a second contact portion CNT2 connected to one region of the second power line PL2 may be formed in the protection layer PSV.

[0139] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include first and second bank patterns BNP1 and BNP2, a bank BNK, first and second connection electrodes CNL1 and CNL2, first and second alignment electrodes ALE1 and ALE2, first and second pixel electrodes ELT1 and ELT2, a light emitting element LD, and first, second and third insulating layers INS1, INS2, and INS3.

[0140] The first bank pattern BNP1 and the second bank pattern BNP2 may be disposed on the protective layer PSV. The first bank pattern BNP1 and the second bank pattern BNP2 may have a shape protruding in a display direction (eg, a third direction DR3). In an example, the first bank pattern BNP1 and the second bank pattern BNP2 may include an organic material and / or an inorganic material, but the present disclosure is not limited thereto.

[0141] The first connection electrode CNL1 and the second connection electrode CNL2 may be disposed on the protection layer PSV. The first connection electrode CNL1 may be connected to the first alignment electrode ALE1. The first connection electrode CNL1 may be electrically connected to the bridge pattern BRP through the first contact portion CNT1. The first connection electrode CNL1 may electrically connect the bridge pattern BRP and the first alignment electrode ALE1 to each other. The second connection electrode CNL2 may be connected to the second alignment electrode ALE2. The second connection electrode CNL2 may be electrically connected to the second power line PL2 through the second contact portion CNT2. The second connection electrode CNL2 may electrically connect the second power line PL2 and the second alignment electrode ALE2 to each other.

[0142] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the protection layer PSV (or base layer). At least a portion of the first alignment electrode ALE1 may be disposed on the first bank pattern BNP1, ​​and at least a portion of the second alignment electrode ALE2 may be disposed on the second bank pattern BNP2, so that each of the first alignment electrode ALE1 and the second alignment electrode ALE2 serves as a reflective partition wall.

[0143] The first alignment electrode ALE1 may be electrically connected to the first pixel electrode ELT1 through a contact hole formed in the first insulating layer INS1. The first pixel electrode ELT1 may receive an anode signal of the light emitting element LD through the first alignment electrode ALE1.

[0144] The second alignment electrode ALE2 may be electrically connected to the second pixel electrode ELT2 through a contact hole formed in the first insulating layer INS1. The second pixel electrode ELT2 may receive a cathode signal (eg, a ground signal) of the light emitting element LD through the second alignment electrode ALE2.

[0145] The first alignment electrode ALE1 and the second alignment electrode ALE2 may include a conductive material. For example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may include at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the present disclosure is not limited to the above examples.

[0146] The first insulating layer INS1 may be disposed on the protection layer PSV, the first and second connection electrodes CNL1 and CNL2, and the first and second alignment electrodes ALE1 and ALE2. The first insulating layer INS1 may cover the first and second alignment electrodes ALE1 and ALE2. The first insulating layer INS1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0147] The bank BNK may be disposed on the first insulating layer INS1. The bank BNK may include an opening having a constant thickness in a display direction (eg, the third direction DR3) and corresponding to the emission area EMA. The bank BNK may include an organic material or an inorganic material, but the present disclosure is not limited thereto.

[0148] The light emitting element LD may be disposed on the first insulating layer INS1 between the first alignment electrode ALE1 and the second alignment electrode ALE2 to emit light based on electrical signals provided from the first pixel electrode ELT1 and the second pixel electrode ELT2.

[0149] The light emitting element LD may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the forward direction or the reverse direction. Fig. 9 and Fig.10 Describe this.

[0150] The second insulating layer INS2 (or insulating pattern) may be disposed on the light emitting element LD. The second insulating layer INS2 may cover a portion of the light emitting element LD. The second insulating layer INS2 may include an organic material. However, the present disclosure is not limited thereto, and the second insulating layer INS2 may include an inorganic material. At least a portion of the second insulating layer INS2 may fill a gap (or cavity) formed at the bottom of the light emitting element LD.

[0151] The first pixel electrode ELT1 and the second pixel electrode ELT2 may be disposed on the first insulating layer INS1 and the second insulating layer INS2. The first pixel electrode ELT1 may electrically connect the first alignment electrode ALE1 and the light emitting element LD to each other, and the second pixel electrode ELT2 may electrically connect the second alignment electrode ALE2 and the light emitting element LD to each other.

[0152] The first pixel electrode ELT1 may provide an anode signal to the light emitting element LD, and the second pixel electrode ELT2 may provide a cathode signal to the light emitting element LD.

[0153] The first pixel electrode ELT1 and the second pixel electrode ELT2 may include a conductive material. In an example, the first pixel electrode ELT1 and the second pixel electrode ELT2 may be formed by the same process and include the same material. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 may include a transparent conductive material including indium tin oxide (ITO), indium zinc oxide (IZO) and / or indium tin zinc oxide (ITZO), but the present disclosure is not limited thereto.

[0154] The third insulating layer INS3 may be disposed on the first pixel electrode ELT1 and the second pixel electrode ELT2 and the second insulating layer INS2 to protect components of the display element layer DPL from external influences (eg, influences of moisture, etc.). For example, the third insulating layer INS3 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0155] The structure of the sub-pixel SPXL is not limited to the above reference Figure 6 Examples are described, and various modified embodiments may be implemented.

[0156] Figure 7 and Figure 8 It shows that the setting Figure 3 A cross-sectional view of an example of a light emitting element in a display device shown in FIG.

[0157] Figure 7 2 is a view showing a state in which the light emitting element LD is obliquely disposed on the first insulating layer INS1 .

[0158] refer to Figures 5 to 7 In the manufacturing process of the display device, ink including the light emitting element LD may be provided in a space in which a fluid may be accommodated. The light emitting element LD may be obliquely disposed on the first insulating layer INS1 through a gap (or a step difference) formed between the first alignment electrode ALE1 and the second alignment electrode ALE2. The light emitting element LD may form an angle (e.g., a predetermined angle) θ with the first insulating layer INS1.

[0159] In a state in which the light emitting element LD is set to be inclined, the first pixel electrode ELT1 and / or the second pixel electrode ELT2 may not be normally deposited on the light emitting element LD. Therefore, when the first pixel electrode ELT1 and the second pixel electrode ELT2 are electrically connected to the light emitting element LD, a contact failure may be caused between the light emitting element LD and the first pixel electrode ELT1 and the second pixel electrode ELT2. When a contact failure is caused between the light emitting element LD and the first pixel electrode ELT1 and the second pixel electrode ELT2, the light emitting element LD corresponds to a fault state (e.g., a non-light emitting state), and therefore, the light emitting efficiency of the display device may be deteriorated.

[0160] Figure 8 1 is a view showing a fractured surface of the light emitting element LD provided on the plane of the first insulating layer INS1.

[0161] refer to Figure 1 , Figure 2 and Figure 8 In the manufacturing process of the display device, ink including the light emitting element LD may be provided in a space in which a fluid may be accommodated. The light emitting element LD may be stably mounted on the first insulating layer INS1. However, referring to the first area Area1, a fracture surface of the light emitting element LD forming the first end portion EP1 and / or the second end portion EP2 of the light emitting element LD may be in a faulty state. For example, in a state in which an uneven state is formed at the fracture surface of the light emitting element LD or in a state in which a portion of the insulating film INF adjacent to the first end portion EP1 and / or the second end portion EP2 is removed, the fracture surface of the light emitting element LD may be in a faulty state.

[0162] In a state where the fracture surface of the light emitting element LD fails, when the first pixel electrode ELT1 and the second pixel electrode ELT2 are electrically connected to the light emitting element LD through the first end portion EP1 and the second end portion EP2, a contact failure (or an increase in contact resistance) may be caused between the light emitting element LD and the first pixel electrode ELT1 and the second pixel electrode ELT2. When the contact failure is caused between the light emitting element LD and the first pixel electrode ELT1 and the second pixel electrode ELT2, the light emitting element LD corresponds to a failure state (e.g., a non-light emitting state), and therefore, the light emitting efficiency of the display device may be deteriorated.

[0163] Fig. 9 It is shown Figure 6 An enlarged view of an embodiment of region A is shown in FIG.

[0164] Fig. 9 The light emitting element LD is shown disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the forward direction. Fig. 9The light emitting element LD shown in FIG. Figure 3 The light emitting element LD shown in FIG. The light emitting element LD may be connected between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the forward direction to constitute an effective light source. The first semiconductor layer SEC1 of the light emitting element LD may be electrically connected to the first pixel electrode ELT1 (via the electrode layer EL), and the second semiconductor layer SEC2a of the light emitting element LD may be electrically connected to the second pixel electrode ELT2.

[0165] The electrode layer EL, the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2a, the third semiconductor layer SEC3, and the fourth semiconductor layer SEC2b may be sequentially disposed in the light emitting element LD in the first direction DR1.

[0166] The insulating film INF may include a first insulating film INF1 , a second insulating film INF2 , and an opening OP1 formed between the first insulating film INF1 and the second insulating film INF2 .

[0167] The first insulating film INF1 may cover the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the first semiconductor layer SEC1, the active layer AL, and a portion of the second semiconductor layer SEC2a. The first insulating film INF1 may completely cover the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the first semiconductor layer SEC1 and the active layer AL. The second semiconductor layer SEC2a surrounded by the first insulating film INF1 may be a portion corresponding to a region overlapping the second insulating layer INS2 and the first pixel electrode ELT1.

[0168] The second insulating film INF2 may cover a portion of the second semiconductor layer SEC2a, the outer surfaces (e.g., the outer peripheral surfaces or the outer circumferential surfaces) of the third semiconductor layer SEC3 and the fourth semiconductor layer SEC2b. The second insulating film INF2 may completely cover the outer surfaces (e.g., the outer peripheral surfaces or the outer circumferential surfaces) of the third semiconductor layer SEC3 and the fourth semiconductor layer SEC2b. Fig. 9 , it is shown that the second semiconductor layer SEC2a adjacent to the opening OP1 is covered by the second insulating layer INS2. However, the second semiconductor layer SEC2a may not be covered by the second insulating film INF2.

[0169] The first insulating film INF1 and the second insulating film INF2 may be disposed to be spaced apart from each other with the opening OP1 interposed therebetween. In an example, the first insulating film INF1 and the second insulating film INF2 may have a structure in which the first insulating film INF1 and the second insulating film INF2 are completely separated from each other by the opening OP1.

[0170] The length of the first insulating film INF1 in the first direction DR1 may be longer than the length of the second insulating film INF2 in the first direction DR1. That is, the region covered by the first insulating film INF1 may be wider than the region covered by the second insulating film INF2.

[0171] The opening OP1 may be provided at a side surface portion of the light emitting element LD. The side surface portion of the light emitting element LD may refer to a surface of the light emitting element LD other than the first end portion EP1 and the second end portion EP2 of the light emitting element LD. In an example, the opening OP1 may be provided to face the display direction (e.g., the third direction DR3). The insulating film INF may partially expose the second semiconductor layer SEC2a through the opening OP1. An area of ​​the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the second semiconductor layer SEC2a may be exposed through the opening OP1. The outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the second semiconductor layer SEC2a may include an area other than the first surface in contact with the active layer AL and the second surface in contact with the third semiconductor layer SEC3.

[0172] The second pixel electrode ELT2 may be disposed on the opening OP1. When viewed on a plane (eg, in a plan view) or in a third direction DR3, the opening OP1 may overlap the second semiconductor layer SEC2a.

[0173] The second pixel electrode ELT2 may contact the second semiconductor layer SEC2a through the opening OP1. When viewed on a plane (eg, in a plan view), the opening OP1 may overlap the second pixel electrode ELT2 and may not overlap the first pixel electrode ELT1 and the second insulating layer INS2.

[0174] The opening OP1 may be disposed to be spaced apart from the active layer AL by a first distance. The opening OP1 may be disposed to be spaced apart from the third semiconductor layer SEC3 by a second distance. The first distance may be longer than the second distance. That is, the opening OP1 may be formed closer to the third semiconductor layer SEC3 than the active layer AL.

[0175] A first power voltage (e.g., an anode signal) may be applied to the first pixel electrode ELT1 to be transmitted to the first end portion EP1, and a second power voltage (e.g., a cathode signal) may be applied to the second pixel electrode ELT2 to be transmitted to the opening OP1 and the second end portion EP2. Current may flow through the light emitting element LD by the first power voltage and the second power voltage.

[0176] The third semiconductor layer SEC3 can prevent the current applied through the fourth semiconductor layer SEC2b at the second end portion EP2 of the light emitting element LD from flowing into the second semiconductor layer SEC2a. The third semiconductor layer SEC3 may include a material having a higher energy band gap than each of the second semiconductor layer SEC2a and the fourth semiconductor layer SEC2b. Electrons injected into the third semiconductor layer SEC3 can be prevented from flowing into the second semiconductor layer SEC2a and / or the fourth semiconductor layer SEC2b. That is, no current can flow through the third semiconductor layer SEC3.

[0177] The light emitting element LD may provide light based on an anode signal supplied from the first pixel electrode ELT1 through the first end portion EP1 and a cathode signal supplied from the second pixel electrode ELT2 through the opening OP1 .

[0178] The cathode signal can be applied to the light emitting element LD from the second pixel electrode ELT2 through the opening OP1, regardless of the shape of the second end portion EP2 of the light emitting element LD (e.g., the shape of the fracture surface). Therefore, the contact resistance between the light emitting element LD and the pixel electrodes ELT1 and ELT2 caused by the shape of the fracture surface of the light emitting element LD can be reduced (or minimized). In addition, when observed on a plane (e.g., in a plan view), the degradation of the light emitting efficiency according to the alignment state of the light emitting element LD aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 can be reduced (or minimized).

[0179] Fig.10 It is shown Figure 6 An enlarged view of an embodiment of region A is shown in FIG.

[0180] Fig.10 The light emitting element LD is shown disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the reverse direction. Fig.10 The light emitting element LD shown in FIG. Figure 4 The reverse light emitting element LDr shown in FIG. The light emitting element LD may be connected between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the reverse direction to constitute an invalid light source. That is, the fourth semiconductor layer SEC2b of the light emitting element LD may be electrically connected to the first pixel electrode ELT1, and the first semiconductor layer SEC1 of the light emitting element LD may be electrically connected to the second pixel electrode ELT2 (e.g., via the electrode layer EL).

[0181] The fourth semiconductor layer SEC2 b , the third semiconductor layer SEC3 , the second semiconductor layer SEC2 a , the active layer AL, the first semiconductor layer SEC1 , and the electrode layer EL may be sequentially disposed in the light emitting element LD.

[0182] The insulating film INF may include a first insulating film INF1 ′, a second insulating film INF2 ′, and an opening OP1 ′ formed between the first insulating film INF1 ′ and the second insulating film INF2 ′.

[0183] The first insulating film INF1' may cover the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the first semiconductor layer SEC1, the active layer AL, and a portion of the second semiconductor layer SEC2a. The first insulating film INF1' may completely cover the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the first semiconductor layer SEC1 and the active layer AL. The second semiconductor layer SEC2a surrounded by the first insulating film INF1' may be a portion corresponding to an area overlapping with the second pixel electrode ELT2. Fig.10 , it is shown that the second semiconductor layer SEC2a adjacent to the opening OP1' is covered by the first insulating film INF1'. However, the second semiconductor layer SEC2a may not be covered by the first insulating film INF1'.

[0184] The second insulating film INF2' may cover a portion of the second semiconductor layer SEC2a, the outer surfaces (e.g., the peripheral surface or the outer circumferential surface) of the third semiconductor layer SEC3 and the fourth semiconductor layer SEC2b. The second insulating film INF2' may completely cover the outer surfaces (e.g., the peripheral surface or the outer circumferential surface) of the third semiconductor layer SEC3 and the fourth semiconductor layer SEC2b. The second semiconductor layer SEC2a surrounded by the second insulating film INF2' may be a portion corresponding to an area overlapping the second insulating layer INS2 and the first pixel electrode ELT1.

[0185] The first and second insulating films INF1' and INF2' may be disposed to be spaced apart from each other with the opening OP1' interposed therebetween. In an example, the first and second insulating films INF1' and INF2' may have a structure in which the first and second insulating films INF1' and INF2' are completely separated from each other by the opening OP1'.

[0186] The length of the second insulating film INF2' in the first direction DR1 may be longer than the length of the first insulating film INF1' in the first direction DR1. That is, the area covered by the second insulating film INF2' may be wider than the area covered by the first insulating film INF1'.

[0187] The opening OP1' may be provided at a side surface portion of the light emitting element LD. The opening OP1' may be provided to face the display direction (e.g., the third direction DR3). The insulating film INF may expose a side surface of the second semiconductor layer SEC2a through the opening OP1'. The second pixel electrode ELT2 may be provided on the opening OP1'. When viewed on a plane (e.g., in a plan view), the opening OP1' may overlap with the second semiconductor layer SEC2a. The second pixel electrode ELT2 may contact with the second semiconductor layer SEC2a through the opening OP1'. When viewed on a plane (e.g., in a plan view), the opening OP1' may overlap with the second pixel electrode ELT2, and may not overlap with the first pixel electrode ELT1 and the second insulating layer INS2.

[0188] The opening OP1' may be disposed at a first distance from the active layer AL. The opening OP1' may be disposed at a second distance from the third semiconductor layer SEC3. The second distance may be longer than the first distance. That is, the opening OP1' may be formed closer to the active layer AL than the third semiconductor layer SEC3.

[0189] In a state (non-luminescence) in which the light emitting element LD is connected between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the reverse direction, the light emitting element LD may become an ineffective light source. A cathode signal may be applied from the second pixel electrode ELT2 through the first end portion EP1 and the opening OP1' of the light emitting element LD. Although the second pixel electrode ELT2 is in contact with the first semiconductor layer SEC1 and the second semiconductor layer SEC2a, current may be blocked from moving to the second end portion EP2 of the light emitting element LD by the third semiconductor layer SEC3, and thus an electrical short circuit phenomenon may be prevented from occurring.

[0190] Fig.11 It is shown that the Figure 3 A cross-sectional view of a pixel in the display device shown in FIG.

[0191] Fig.11 The bank BNK, the color conversion layer CCL, the optical layer OPL and / or the color filter layer CFL disposed on the pixel circuit layer PCL of the sub-pixel SPXL are shown. Fig.11 , components of the pixel circuit layer PCL and components of the display element layer DPL except the bank BNK are omitted from the above-mentioned components.

[0192] Fig.11 A stack structure of a pixel PXL in relation to a color conversion layer CCL, an optical layer OPL, and a color filter layer CFL may be illustrated.

[0193] refer to Fig.10 and Fig.11, the bank BNK may be disposed between the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3, or at a boundary of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3, and include a space (or region) overlapping each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The space defined by the bank BNK may be a region in which the color conversion layer CCL may be disposed.

[0194] The color conversion layer CCL may be disposed above the light emitting element LD in a space surrounded by the bank BNK. The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first subpixel SPXL1, a second color conversion layer CCL2 disposed in the second subpixel SPXL2, and a light scattering layer LSL disposed in the third subpixel SPXL3.

[0195] The color conversion layer CCL may be disposed on the light emitting element LD. The color conversion layer CCL may be configured to change the wavelength of light. In one or more embodiments, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include a light emitting element LD that emits light of the same color. For example, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include a light emitting element LD that emits light of a third color (or blue). The color conversion layer CCL including color conversion particles is disposed on the light emitting element LD of each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3, so that a full-color image can be displayed.

[0196] The first color conversion layer CCL1 may include first color conversion particles for converting the third color light emitted from the light emitting element LD into the first color light. For example, the first color conversion layer CCL1 may include a plurality of first quantum dots QD1 dispersed in a suitable matrix material (eg, a predetermined matrix material) such as a base resin.

[0197] When the light emitting element LD is a blue light emitting element emitting blue light and the first sub-pixel SPXL1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 for converting the blue light emitted from the blue light emitting element into red light. The first quantum dot QD1 may absorb the blue light and emit red light by changing the wavelength of the blue light according to energy conversion. In one or more embodiments, when the first sub-pixel SPXL1 is a pixel of another color, the first color conversion layer CCL1 may include a first quantum dot QD1 corresponding to the color of the first sub-pixel SPXL1.

[0198] The second color conversion layer CCL2 may include second color conversion particles for converting the third color light emitted from the light emitting element LD into the second color light. For example, the second color conversion layer CCL2 may include a plurality of second quantum dots QD2 dispersed in a suitable matrix material (e.g., a predetermined matrix material) such as a base resin.

[0199] When the light emitting element LD is a blue light emitting element emitting blue light and the second sub-pixel SPXL2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 for converting the blue light emitted from the blue light emitting element into green light. The second quantum dot QD2 may absorb the blue light and emit green light by changing the wavelength of the blue light according to energy conversion. In one or more embodiments, when the second sub-pixel SPXL2 is a pixel of another color, the second color conversion layer CCL2 may include a second quantum dot QD2 corresponding to the color of the second sub-pixel SPXL2.

[0200] Blue light having a relatively short wavelength in the visible light band is incident on the first quantum dot QD1 and the second quantum dot QD2, so that the absorption coefficient of the first quantum dot QD1 and the second quantum dot QD2 can be improved. Therefore, the efficiency of the light finally emitted from the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can be improved, and excellent color reproduction can be ensured. In addition, the light-emitting unit EMU of each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 is configured by using a light-emitting element LD of the same color (for example, a blue light-emitting element), so that the manufacturing efficiency of the display device DD can be improved.

[0201] The light scattering layer LSL may be configured to effectively utilize the light of the third color (or blue) emitted from the light emitting element LD. In an example, when the light emitting element LD is a blue light emitting element emitting blue light and the third sub-pixel SPXL3 is a blue pixel, the light scattering layer LSL may include at least one kind (or type) of light scattering particles SCT to effectively utilize the light emitted from the light emitting element LD. In an example, the light scattering particles SCT of the light scattering layer LSL may include titanium oxide (TiO 2 ), barium sulfate (BaSO 4 ), calcium carbonate (CaCO 3 ), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2) and zinc oxide (ZnO). In one or more embodiments, the light scattering particles SCT are not only provided in the light scattering layer LSL, but may be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. In one or more embodiments, the light scattering particles SCT may be omitted so that a light scattering layer LSL configured with a transparent polymer is provided.

[0202] The first capping layer CPL1 may be disposed on the color conversion layer CCL. The first capping layer CPL1 may be disposed over the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The first capping layer CPL1 may cover the color conversion layer CCL. The first capping layer CPL1 may prevent the color conversion layer CCL from being damaged or contaminated due to the infiltration of impurities such as moisture or air from the outside.

[0203] The first capping layer CPL1 is an inorganic layer and may include silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Silicon Oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y )wait.

[0204] The optical layer OPL may be disposed on the first capping layer CPL1. The optical layer OPL may be used to improve light extraction efficiency by recycling light provided from the color conversion layer CCL through total reflection. To this end, the optical layer OPL may have a refractive index relatively lower than that of the color conversion layer CCL. For example, the refractive index of the color conversion layer CCL may be about 1.6 to about 2.0, and the refractive index of the optical layer OPL may be about 1.1 to about 1.3.

[0205] The second capping layer CPL2 may be disposed on the optical layer OPL. The second capping layer CPL2 may be disposed over the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3. The second capping layer CPL2 may cover the optical layer OPL. The second capping layer CPL2 may prevent the optical layer OPL from being damaged or contaminated due to infiltration of impurities such as moisture or air from the outside.

[0206] The second capping layer CPL2 is an inorganic layer and may include silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Silicon Oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y )wait.

[0207] The planarization layer PLL may be disposed on the second capping layer CPL2. The planarization layer PLL may be disposed over the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0208] The planarization layer PLL may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or benzocyclobutene (BCB). However, the present disclosure is not necessarily limited thereto, and the planarization layer PLL may include various kinds (or types) of inorganic insulating materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0209] The color filter layer CFL may be disposed on the planarization layer PLL. The color filter layer CFL may include color filters CF1, CF2, and CF3 corresponding to the color of each sub-pixel SPXL. The color filters CF1, CF2, and CF3 corresponding to the color of each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 are disposed so that a full-color image can be displayed.

[0210] The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, the first color filter CF1 being disposed in the first sub-pixel SPXL1 to allow light emitted from the first sub-pixel SPXL1 to selectively transmit therethrough, the second color filter CF2 being disposed in the second sub-pixel SPXL2 to allow light emitted from the second sub-pixel SPXL2 to selectively transmit therethrough, and the third color filter CF3 being disposed in the third sub-pixel SPXL3 to allow light emitted from the third sub-pixel SPXL3 to selectively transmit therethrough.

[0211] In one or more embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red filter, a green filter, and a blue filter, respectively, but the present disclosure is not necessarily limited thereto. Hereinafter, when any of the first color filter CF1, the second color filter CF2, and the third color filter CF3 is specified, or when two or more kinds (or types) of color filters are specified inclusively, the corresponding color filter is referred to as a "color filter CF".

[0212] The first color filter CF1 may overlap the first color conversion layer CCL1 in the thickness direction (e.g., the third direction DR3) of the substrate SUB. The first color filter CF1 may include a color filter material for allowing light of the first color (or red) to selectively transmit therethrough. For example, when the first sub-pixel SPXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0213] The second color filter CF2 may overlap the second color conversion layer CCL2 in the thickness direction (e.g., the third direction DR3) of the substrate SUB. The second color filter CF2 may include a color filter material for allowing light of the second color (or green) to selectively transmit therethrough. For example, when the second sub-pixel SPXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0214] The third color filter CF3 may overlap the light scattering layer LSL in the thickness direction (e.g., third direction DR3) of the substrate SUB. The third color filter CF3 may include a color filter material for allowing light of a third color (or blue) to selectively transmit therethrough. For example, when the third sub-pixel SPXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0215] The light blocking layer BM may be disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3. When the light blocking layer BM is formed between the first color filter CF1, the second color filter CF2, and the third color filter CF3 as described above, it is possible to prevent color mixing defects from being observed on the front or side of the display device DD. The material of the light blocking layer BM is not particularly limited, and the light blocking layer BM may be configured with various light blocking materials. In an example, the light blocking layer BM may include a black matrix, or the light blocking layer BM may be realized when the first color filter CF1, the second color filter CF2, and the third color filter CF3 are stacked on each other.

[0216] The overcoat layer OC may be disposed on the color filter layer CFL. The overcoat layer OC may be disposed over the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3. The overcoat layer OC may cover the lower component including the color filter layer CFL. The overcoat layer OC may prevent moisture or air from penetrating into the lower component. In addition, the overcoat layer OC may protect the lower component from foreign matter such as dust.

[0217] The overcoat layer OC may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and / or benzocyclobutene (BCB). However, the present disclosure is not necessarily limited thereto, and the overcoat layer OC may include an inorganic material.

[0218] The outer film layer OFL may be disposed on the outer coating layer OC. The outer film layer OFL may be disposed at an external portion of the display device DD to reduce external influences. The outer film layer OFL may be disposed throughout the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. In one or more embodiments, the outer film layer OFL may include one of a polyethylene terephthalate (PET) film, a low-reflection film, a polarizing film, and a transmittance-controlled film, but the present disclosure is not necessarily limited thereto. In one or more embodiments, the pixel PXL may include an upper substrate instead of the outer film layer OFL.

[0219] Figures 12 to 17 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0220] In the following, reference will be made to Figures 12 to 17 Describe the manufacturing Fig. 9 The method of display element layer DPL of the sub-pixel SPXL is shown.

[0221] In the present specification, although the manufacturing steps of the sub-pixel SPXL are described as being performed sequentially according to the cross-sectional views, without changing the spirit of the present disclosure, some steps shown as being performed continuously may be performed simultaneously, the order of the steps may be changed, some steps may be omitted, or another step may be further included between the steps.

[0222] exist Figures 12 to 17 In the present invention, parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0223] refer to Fig.12 , a first bank pattern BNP1 and a second bank pattern BNP2 may be formed on the base substrate BSL, a first alignment electrode ALE1 may be formed over the first bank pattern BNP1, ​​and a second alignment electrode ALE2 may be formed over the second bank pattern BNP2.

[0224] The base substrate BSL may constitute the basic component of the display device DD. The base substrate BSL may be a rigid substrate or film or a flexible substrate or film. For example, the base substrate BSL may be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of a plastic or metal material, or at least one insulating layer. The material and / or properties of the base substrate BSL are not particularly limited. In one or more embodiments, the base substrate BSL may be substantially transparent. The term "substantially transparent" may mean that light can be transmitted with a suitable transmittance (e.g., a predetermined transmittance) or greater. In another embodiment, the base substrate BSL may be translucent or opaque. In addition, in some embodiments, the base substrate BSL may include a reflective material. In the example, the base substrate BSL may be a substrate that constitutes Figure 6 A component of the pixel circuit layer PCL shown in FIG.

[0225] The first bank pattern BNP1 and the second bank pattern BNP2 may be formed to be spaced apart from each other in the first direction DR1. The first bank pattern BNP1 may be formed to overlap the first alignment electrode ALE1. The second bank pattern BNP2 may be formed to overlap the second alignment electrode ALE2.

[0226] refer to Fig.13 , a first insulating layer INS1 may be formed to cover the base substrate BSL, the first and second bank patterns BNP1 and BNP2 , and the first and second alignment electrodes ALE1 and ALE2 .

[0227] refer to Fig.14 , a light emitting element LD may be disposed on the first insulating layer INS1 between the first alignment electrode ALE1 and the second alignment electrode ALE2. The light emitting element LD may be dispersed in a solvent having fluidity to be ejected onto the first insulating layer INS1 by ink. The light emitting element LD may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0228] The light emitting element LD may be moved to a region where the light emitting element LD is to be disposed by a dielectrophoresis (DEP) force generated based on an electrical signal supplied to the first alignment electrode ALE1 and the second alignment electrode ALE2 .

[0229] In this step, an electric signal is supplied to the first alignment electrode ALE1 and the second alignment electrode ALE2 so that an electric field may be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0230] A first electrical signal may be provided to the first alignment electrode ALE1, and a second electrical signal may be provided to the second alignment electrode ALE2. In addition, the light emitting element LD may be arranged based on an electric field according to the first electrical signal and the second electrical signal. In an example, each of the first electrical signal and the second electrical signal may be any one of a sine wave, a triangle wave, a step wave, a square wave, a trapezoidal wave, and a pulse wave. However, the present disclosure is not limited to a specific example.

[0231] The light emitting element LD may be aligned in a forward direction between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0232] refer to Fig.15 , a second insulating layer INS2 may be formed on the light emitting element LD. The second insulating layer INS2 may be formed to overlap with the second semiconductor layer SEC2a of the light emitting element LD.

[0233] refer to Fig.16 , the opening OP1 may be formed by removing a portion of the insulating film INF. The opening OP1 may correspond to a region of the second semiconductor layer SEC2a overlapping with the second pixel electrode ELT2 disposed according to a subsequent process.

[0234] The photoresist pattern PR may be formed in other regions except the region where the insulating film INF is to be removed, and the photoresist pattern PR may not be formed in the region where the insulating film INF is to be removed (i.e., the region NPR where the photoresist pattern PR is not provided). Components provided in other regions except the region where the insulating film INF is to be removed may maintain their shapes by the photoresist pattern PR. The region where the insulating film INF is to be removed may be removed by a photolithography process.

[0235] refer to Fig.17 , a first pixel electrode ELT1 and a second pixel electrode ELT2 may be formed on the first insulating layer INS1 , the light emitting element LD, and the second insulating layer INS2 .

[0236] The first and second pixel electrodes ELT1 and ELT2 may be disposed according to profiles (or shapes) of the first and second bank patterns BNP1 and BNP2 , and the first and second insulating layers INS1 and INS2 .

[0237] The first pixel electrode ELT1 may be connected to the first end portion EP1 of the light emitting element LD (eg, to the first semiconductor layer SEC1 (eg, via the electrode layer EL)). The second pixel electrode ELT2 may be connected to the second semiconductor layer SEC2a through the opening OP1 of the light emitting element LD.

[0238] In a display device and a method for manufacturing a display device according to an embodiment of the present disclosure, a light-emitting element and a pixel electrode are electrically connected to each other through an opening formed at a side surface portion of the light-emitting element, thereby reducing (or minimizing) the contact resistance between the light-emitting element and the pixel electrode caused by the shape of the fracture surface of the light-emitting element.

[0239] In addition, since another semiconductor layer for blocking current between semiconductor layers is included, an electrical short circuit phenomenon that may occur when the alignment direction of the light emitting element is a reverse direction (eg, non-light emitting state of the light emitting element) can be prevented.

[0240] Exemplary embodiments have been disclosed herein, and although specific terms are used, the terms are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, at the time of filing this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, characterized in that The display device comprises: substrate; a light emitting element, on the substrate; a first pixel electrode on a region of the light emitting element, the first pixel electrode being electrically connected to the light emitting element; and a second pixel electrode, on another region of the light emitting element, the second pixel electrode being electrically connected to the light emitting element, Wherein, the light emitting element comprises: A first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer are sequentially arranged along a first direction; and an insulating film covering outer surfaces of the first semiconductor layer, the active layer, the second semiconductor layer and the third semiconductor layer, wherein the opening of the insulating film exposes at least one side surface of the second semiconductor layer to the outside while passing through the insulating film, and Wherein, the second pixel electrode is in contact with the second semiconductor layer.

2. The display device according to claim 1, characterized in that The opening of the insulating film is spaced apart from the active layer and the third semiconductor layer in a plan view.

3. The display device according to claim 2, characterized in that The opening of the insulating film is closer to the third semiconductor layer than to the active layer.

4. The display device according to claim 2, characterized in that The opening of the insulating film is closer to the active layer than to the third semiconductor layer.

5. The display device according to claim 2, characterized in that The light emitting element includes a first end portion and a second end portion opposite to the first end portion, wherein the first semiconductor layer of the light emitting element is adjacent to the first end portion, and the third semiconductor layer of the light emitting element is adjacent to the second end portion, and The light emitting element further includes a fourth semiconductor layer arranged on the third semiconductor layer in the first direction, and the fourth semiconductor layer is at the second end portion.

6. The display device according to claim 5, characterized in that The insulating film comprises: a first insulating film surrounding a region of the second semiconductor layer, the first semiconductor layer, and an outer surface of the active layer; and a second insulating film surrounding another region of the second semiconductor layer, the third semiconductor layer, and the outer surface of the fourth semiconductor layer, and The opening is between the first insulating film and the second insulating film.

7. The display device according to claim 6, characterized in that The first pixel electrode is electrically connected to the first semiconductor layer while being in contact with the first end portion of the light emitting element, and The second pixel electrode is electrically connected to the second semiconductor layer while being in contact with the second semiconductor layer exposed through the opening.

8. The display device according to claim 7, characterized in that The third semiconductor layer includes at least one of AlGaInN, GaN, AlGaN, InGaN, AlN and InN, and The second pixel electrode is in contact with the fourth semiconductor layer at the second end portion of the light emitting element.

9. The display device according to claim 1, characterized in that: The display device further includes an insulating pattern on the light emitting element, In a plan view, the first pixel electrode and the second pixel electrode respectively cover two ends of the insulating pattern.

10. The display device according to claim 9, characterized in that The opening of the insulating film is spaced apart from the insulating pattern in a plan view.

11. The display device according to claim 9, characterized in that In a plan view, the first pixel electrode and the insulating pattern overlap a portion of the second semiconductor layer of the light emitting element.

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