Vehicle-mounted data acquisition device

Abstract

The utility model relates to the technical field of remote data acquisition, in particular to a vehicle-mounted data acquisition device. An independent embedded core processor, a CAN controller and a CAN transceiver are adopted, wherein the CAN controller and the CAN transceiver are compatible with the core processor. The core processor receives the vehicle-mounted data through the CAN bus, the external expansion RAM connected with the core processor is used for storing the vehicle-mounted data, and the signal conditioning module is used for maintaining the signal strength and improving the acquisition precision. And then vehicle-mounted data is transmitted from the core processor to the GPRS module through the SCI module, and remote wireless transmission is realized by using the GPRS module. Therefore, the independent embedded core processor and the CAN bus, the CAN transceiver, the CAN controller, the core processor, the SCI module, the GPRS module, the external expansion RAM and the signal conditioning module which are matched are integrated into the vehicle-mounted data acquisition device, so that the sampling precision and reliability of vehicle-mounted data are improved, and the device can be separated from a PC (Personal Computer) to perform high-precision CAN signal acquisition.

Description

Technical Field

[0001] The utility model relates to the technical field of remote data acquisition, in particular to a vehicle-mounted data acquisition device. Background Art

[0002] Vehicles have functions such as intelligent driving and vehicle safety monitoring. To realize these functions, it is necessary to first obtain vehicle data, and then process and analyze the vehicle data through the vehicle computer. The collection and processing of vehicle data can be achieved by installing sensors. These devices can collect environmental information around the vehicle, vehicle status and other data.

[0003] However, the accuracy and stability of the sensor may be affected by environmental factors, resulting in low data accuracy; at the same time, new energy vehicles have a large amount of on-board data, and using sensors to collect and transmit them one by one will consume a lot of financial and material resources. Utility Model Content

[0004] In view of the shortcomings of the prior art, the utility model proposes a vehicle-mounted data acquisition device to solve the technical problems in the prior art that the accuracy of sensor data collection is not high and that collecting and transmitting data one by one will consume a lot of financial and material resources.

[0005] The technical solution adopted by the utility model is a vehicle-mounted data acquisition device.

[0006] In a first possible implementation, a vehicle-mounted data acquisition device includes:

[0007] The CAN bus, CAN transceiver, CAN controller, core processor, SCI module and GPRS module are connected in sequence;

[0008] The core processor is also connected to the external RAM and signal conditioning module.

[0009] In combination with the first implementable manner, in the second implementable manner, the core processor adopts the TMS320LF2407DSP chip.

[0010] In combination with the second implementable manner, in a third implementable manner, the clock connection method of the TMS320LF2407DSP chip includes an external clock and an internal clock.

[0011] In combination with the second implementable manner, in a fourth implementable manner, the TMS320LF2407DSP chip is connected to a clock oscillation circuit, and the clock oscillation circuit uses an active crystal oscillator combined with a phase-locked loop.

[0012] In combination with the first implementable manner, in a fifth implementable manner, the JTAG module uses a 14-pin JTAG interface, and a pull-up resistor with a resistance of 4.7KΩ is connected to two working mode selection pins EU0 and EM1 of the JTAG interface.

[0013] In combination with the first implementable manner, in a sixth implementable manner, the CAN transceiver adopts a PCA82C250 chip.

[0014] In combination with the first implementable manner, in a seventh implementable manner, the signal conditioning module includes two operational amplifiers, and each operational amplifier uses an LM358 chip.

[0015] In combination with the second implementable method, in the eighth implementable method, the CANH and CANL pins on the CAN transceiver are connected to the CANH and CANL pins on the TMS320LF2407DSP chip, and the TXD and RXD pins on the CAN transceiver are connected to the TXD and RXD pins of the TMS320LF2407DSP chip; a 120Ω resistor is connected between the CANH line and the CANL line.

[0016] In combination with the first possible implementation, in a ninth possible implementation, an optocoupler isolation device is connected between the CAN transceiver and the CAN controller.

[0017] In combination with the second implementable method, the tenth implementable method also includes a power module, the power module adopts a TPS7333 chip, the RESET pin on the TPS7333 chip is directly connected to the / RS_DSP pin on the DSP chip of the core processor; the output end of the power module is connected to two voltage-stabilizing capacitors with capacitances of 10μF and 0.1μF.

[0018] It can be seen from the above technical solution that the beneficial technical effects of the utility model are as follows:

[0019] 1. This solution uses an independent embedded core processor, as well as a CAN controller and CAN transceiver that are compatible with the core processor. The core processor receives vehicle data through the CAN bus, and the external RAM connected to the core processor is used to store the vehicle data. The signal conditioning module is used to maintain the signal strength and improve the acquisition accuracy. The vehicle data is then transmitted from the core processor to the GPRS module through the SCI module, and then the GRPS module is used to achieve remote wireless transmission. In this way, the independent embedded core processor and the above-mentioned supporting CAN bus, CAN transceiver, CAN controller, core processor, SCI module, GPRS module, external RAM and signal conditioning module are integrated into a vehicle data acquisition device to improve the sampling accuracy and reliability of vehicle data, so that the device can be separated from the PC for high-precision CAN signal acquisition.

[0020] 2. This solution uses CAN bus communication technology to collect vehicle data, and uses CAN bus as the communication tool between the internal control systems of new energy vehicles. It can effectively support distributed and real-time control serial communication. Compared with other field buses, CAN bus has a very high transmission rate, a stable transmission process, and no cumbersome connection is required, and it can obtain vehicle data more effectively and in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation of the utility model or the technical solution in the prior art, the following is a brief introduction to the drawings required for the specific implementation or the prior art description. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0022] Figure 1 A schematic diagram of the structure of a vehicle-mounted data acquisition device provided in this embodiment;

[0023] Figure 2 A circuit diagram of a CAN transceiver provided in this embodiment;

[0024] Figure 3 A schematic diagram of external pins of a PCA82C250 chip provided in this embodiment;

[0025] Figure 4 A functional block diagram of a PCA82C250 chip provided in this embodiment;

[0026] Figure 5 An internal structure diagram of a TMS320LF2407DSP chip provided in this embodiment;

[0027] Figure 6 A pin diagram of a TMS320LF2407DSP processor provided in this embodiment;

[0028] Figure 7 A structural diagram of a clock oscillation circuit provided in this embodiment;

[0029] Figure 8 A circuit diagram of an SCI module provided in this embodiment;

[0030] Fig. 9 A circuit diagram of an external expansion RAM provided in this embodiment;

[0031] Fig.10 A circuit diagram of a signal conditioning module provided in this embodiment;

[0032] Fig.11A circuit diagram of a JTAG module provided in this embodiment;

[0033] Fig.12 A circuit diagram of a power module provided in this embodiment;

[0034] Reference numerals:

[0035] 101-CAN bus, 102-CAN transceiver, 103-CAN controller, 104-core processor, 105-SCI module, 106-GPRS module, 107-external RAM, 108-signal conditioning module, 109-FLASH module, 110-JTAG module. DETAILED DESCRIPTION

[0036] The following embodiments of the technical solution of the utility model are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the utility model, and are therefore only used as examples, and cannot be used to limit the protection scope of the utility model.

[0037] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by technicians in the field to which the utility model belongs.

[0038] Combination Figure 1 As shown, this embodiment provides a vehicle-mounted data acquisition device, including: a CAN bus 101, a CAN transceiver 102, a CAN controller 103, a core processor 104, an SCI module 105 and a GPRS module 106 connected in sequence; the core processor is also connected to an external expansion RAM 107 and a signal conditioning module 108 respectively.

[0039] The working principle of Example 1 is described in detail below:

[0040] This solution uses an independent embedded core processor, as well as a CAN controller and CAN transceiver that are compatible with the core processor. The core processor receives vehicle data through the CAN bus, and the external RAM connected to the core processor is used to store the vehicle data. The signal conditioning module is used to maintain the signal strength and improve the acquisition accuracy. The vehicle data is then transmitted from the core processor to the GPRS module through the SCI module, and then the GRPS module is used to achieve remote wireless transmission. In this way, the independent embedded core processor and the above-mentioned supporting CAN bus, CAN transceiver, CAN controller, core processor, SCI module, GPRS module, external RAM and signal conditioning module are integrated into a vehicle data acquisition device to improve the sampling accuracy and reliability of vehicle data, so that the device can perform high-precision CAN signal acquisition without a PC.

[0041] Optionally, the core processor is also connected to the FLASH module 109 and the JTAG module 110 respectively.

[0042] Optionally, the CAN bus communication interface consists of a CAN transceiver, a dominant 3.5V CANH line and an invisible 1.5V CANL line.

[0043] Optionally, the CAN transceiver uses a PCA82C250 transceiver, and the circuit is as follows Figure 2 As shown in the figure, the CANH and CANL pins on the CAN transceiver are connected to the CANH and CANL pins on the TMS320LF2407DSP chip, and the TXD and RXD pins on the CAN transceiver are connected to the TXD and RXD pins on the TMS320LF2407DSP chip; a 120Ω resistor is connected between the CANH line and the CANL line. In this way, the CANH and CANL signals on the bus are converted into CANTX and CANRX signals by differential signaling, completing the transmission of signals between the bus and the core processor.

[0044] like Figure 2 As shown, the CANH and CANL pins on the transceiver are connected via a resistor BR3, the VCC pin is connected to one end of a capacitor BC1, the other end of the capacitor BC1 is connected to one end of a resistor BR4, and the other end of the resistor BR4 is connected to pin 8.

[0045] Optionally, an optical coupler isolation device is added between the transceiver and the controller to reduce electromagnetic interference, increase the anti-interference capability of the system, and reduce the bit error rate and the number of error retransmissions.

[0046] In some embodiments, the optocoupler isolation device is a HCNR200 high linearity analog optocoupler isolator.

[0047] Optionally, the CAN transceiver is used to convert binary codes into differential signals for transmission, and to convert differential signals into binary codes for reception. As a communication bridge between the CAN bus and the CAN controller, the CAN transceiver provides differential transmission function for the CAN bus and differential reception function for the CAN controller. Based on factors such as the acquisition site conditions and the compatibility of the entire hardware system, this solution selects the PCA82C250 chip as the CAN transceiver, with a maximum operating temperature of 125°C, extremely strong instantaneous anti-interference ability, and overheat protection and low current motor mode. The external pins of the PCA82C250 chip are as follows: Figure 3 As shown, the functional block diagram is as follows Figure 4 shown.

[0048] In some embodiments, the core processor uses the DPS digital signal processor TMS320LF2407 from Texas Instruments (TI). The TMS320LF2407 DSP chip embeds a 16-bit CAN controller module, which has two working modes: standard mode and extended mode, and receives and sends messages through six mailboxes. By default, mailboxes 0 and 1 can only receive messages, mailboxes 2 and 3 can both receive and send messages as needed, and mailboxes 4 and 5 can only send messages. The receive mask register (LAM) is located in the receive mailbox summary, which can mask some identifiers to a certain extent, providing diversity for subsequent address encoding. Its internal structure is as follows: Figure 5 shown.

[0049] The TMS320LF2407DSP processor consists of 144 pins, such as Figure 6 As shown, it includes 16 address bus pins (A0~A15) for addressing 64K space; 16 data bus pins (D0~D15) for parallel operation of 16-bit data; 12 control signal pins, including data memory, program memory and I / O space; 20 A / D conversion pins; 25 event manager pins; 8 CAN, SCI and SPI pins; 21 power signal pins (5V programming voltage / 3.3V working voltage) and 25 other pins (interrupt, clock, oscillator, etc.).

[0050] Optionally, the clock connection mode of the TMS320LF2407DSP chip includes an external clock and an internal clock.

[0051] Optionally, the TMS320LF2407DSP chip is connected to a clock oscillation circuit, and the clock oscillation circuit adopts a combination of an active crystal oscillator and a phase-locked loop.

[0052] Optionally, a clock oscillator circuit such as Figure 7 As shown, pin 123 of the DSP chip is respectively connected to the active crystal oscillator 1X1 and one end of the capacitor 1C1, pin 124 of the DSP chip is respectively connected to the other end of the active crystal oscillator 1X1 and one end of the capacitor 1C2, and the other end of the capacitor 1C1 is connected to the other end of the capacitor 1C2; pin 11 of the DSP chip is respectively connected to one end of the capacitor 1C3 and one end of the capacitor 1C4, pin 10 of the DSP chip is respectively connected to one end of the resistor 1R1 and the other end of the capacitor 1C3; the other end of the resistor 1R1 is connected to the other end of the capacitor 1C4.

[0053] Optionally, the SCI module is a serial communication interface module used for communication between the core processor and the GPRS module. The SCI module has an 8-bit register and supports serial digital communication between asynchronous peripherals. Its working mode is full-duplex. The circuit of the SCI module is as follows Figure 8As shown, pins 1 and 3 are connected through capacitor AC5, pins 4 and 5 are connected through capacitor AC2, pin 15 is connected to capacitor AC1, pin 6 is connected to capacitor AC4, pins 13 and 14 are respectively connected to interface No. 3 and interface No. 2 of AJI, and pins 2 and 16 are connected through capacitor AC3.

[0054] Optionally, the data transmission pin TX-232 and the data reception pin RX-232 of the GPRS module are respectively connected to the data reception pin SCIRXD and the data transmission pin SCITXD built into the DSP, and communicate through the serial communication interface.

[0055] Optionally, the address pins A0-A15, data pins D0-D15, write probe WE, read probe RD, program memory access probe PS, and data storage access probe DS of the external RAM are connected to the corresponding pins on the DSP chip of the core processor, and the coexistence of program RAM and data RAM is realized through a logic AND gate circuit. The circuit diagram is shown in FIG. Fig. 9 shown.

[0056] Optionally, the signal conditioning module includes dual operational amplifiers, both of which use LM358 chips. The LM358 internally includes two independent high-yield operational amplifiers with frequency compensation, which are suitable for single power supply with a wide power supply voltage range, and are also suitable for dual power supply working mode, which can improve the acquisition accuracy and maintain the signal strength.

[0057] The circuit diagram of the signal conditioning module is as follows: Fig.10 As shown, pins 1 and 2 of the first operational amplifier 5U1 are connected to capacitor 5C3, pin 3 is connected to one end of resistor 5R1 and resistor 5R2 respectively, and pin 4 is connected to the other end of resistor 5R2; pin 5 is connected to resistor 5R3 and resistor 5R4 respectively, pins 6 and 7 are connected to one end of capacitor 5C2, and the other end of capacitor 5C2 is connected to pin 8 through capacitor 5C1; pins 1 and 2 of the second operational amplifier 5U2 are connected to capacitor 5C6, pin 3 is connected to one end of resistor 5R5 and resistor 5R6 respectively, and pin 4 is connected to the other end of resistor 5R6; pin 5 is connected to resistor 5R7 and resistor 5R8 respectively, pins 6 and 7 are connected to one end of capacitor 5C5, and the other end of capacitor 5C5 is connected to pin 8 through capacitor 5C4.

[0058] Optionally, combined Fig.11As shown in the figure, the JTAG module uses a 14-pin JTAG interface. Each pin of the JTAG interface is connected to the corresponding pin on the DSP chip. The TMS pin is the test mode selection pin, which is used to program and debug the hardware device; the TID pin and the TDO pin are the data input and output pins; the TCK pin and the TRST pin are the clock input pin and the reset input pin respectively; EU0 and EM1 are the chip working mode selection pins, when pulled up, it means the chip is in simulation mode, and when pulled down, it means the chip is in boundary scan mode.

[0059] Optionally, a pull-up resistor with a resistance of 4.7KΩ is connected to the two working mode selection pins of EU0 and EM1, so as to be able to connect to the emulator for program burning and debugging.

[0060] Optionally, the vehicle-mounted data acquisition device further includes a power module. The circuit of the power module is as follows: Fig.12 As shown in the figure, the power module uses the TPS7333 chip. The RESET pin on the TPS7333 chip is directly connected to the / RS_DSP pin on the DSP chip of the core processor to complete the power-on reset of the core processor. At the same time, the output end of the power module is connected to two voltage-stabilizing capacitors with capacitances of 10μF and 0.1μF to obtain a stable 3.3V operating voltage.

[0061] In some embodiments, the assembly language is written and the communication parameters are set through the DSP's built-in integrated development tool CCS (Code Composer Studio) environment and DL6500-DL6700 setting and testing software to complete the software design of the CAN communication system and the communication between the GPRS module and the host computer. This solution integrates on-board data acquisition, transmission, reception, and processing, focusing on real-time acquisition of on-board data of various electric vehicles and remote transmission to the local end, so that the local monitoring center can monitor and analyze the vehicle's operating status in real time, facilitate the classification and sorting of the collected data, and establish a corresponding database. The database includes parameters that affect the economy and power of the vehicle during driving. Under the condition of meeting the driving power requirements, real-time adjustments are made according to the parameters in the database to ensure that the vehicle always runs in an efficient and economical state.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model, and they should all be included in the scope of the claims and specification of the utility model.

Claims

1. A vehicle-mounted data acquisition device, characterized in that: include: The CAN bus, CAN transceiver, CAN controller, core processor, SCI module and GPRS module are connected in sequence; The core processor is also connected to the external RAM and signal conditioning module.

2. The device according to claim 1, characterized in that The core processor uses TMS320LF2407DSP chip.

3. The device according to claim 2, characterized in that The clock connection methods of the TMS320LF2407DSP chip include external clock and internal clock.

4. The device according to claim 2, characterized in that The TMS320LF2407DSP chip is connected to a clock oscillation circuit, which uses an active crystal oscillator combined with a phase-locked loop.

5. The device according to claim 1, characterized in that The JTAG module uses a 14-pin JTAG interface. A 4.7KΩ pull-up resistor is connected to the two working mode selection pins EU0 and EM1 of the JTAG interface.

6. The device according to claim 1, characterized in that The CAN transceiver uses the PCA82C250 chip.

7. The device according to claim 1, characterized in that The signal conditioning module includes two operational amplifiers, each of which uses an LM358 chip.

8. The device according to claim 2, characterized in that The CANH and CANL pins on the CAN transceiver are connected to the CANH and CANL pins on the TMS320LF2407DSP chip, and the TXD and RXD pins on the CAN transceiver are connected to the TXD and RXD pins of the TMS320LF2407DSP chip; a 120Ω resistor is connected between the CANH line and the CANL line.

9. The device according to claim 1, characterized in that An optocoupler isolation device is connected between the CAN transceiver and the CAN controller.

10. The device according to claim 2, characterized in that It also includes a power module, which uses a TPS7333 chip. The RESET pin on the TPS7333 chip is directly connected to the / RS_DSP pin on the DSP chip of the core processor; the output end of the power module is connected to two voltage-stabilizing capacitors with capacitances of 10 μF and 0.1 μF.

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