Integrated chip

Abstract

The utility model provides an integrated chip. The integrated chip comprises a reference magnetic layer and a barrier layer which are arranged on the reference magnetic layer. A first free magnetic layer is over the barrier layer. The second free magnetic layer is over the first free magnetic layer. The spacer layer is between the first free magnetic layer and the second free magnetic layer. The spacer layer includes magnesium and a transition metal. The atomic ratio of magnesium to transition metal is in the range of 15% to 80%.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated circuit, and in particular to an integrated chip. Background Art

[0002] Many modern electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to store data without power, while volatile memory cannot. Some examples of next generation electronic memory include magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), and conductive bridging random access memory (CBRAM). Utility Model Content

[0003] According to an embodiment of the utility model, an integrated chip includes: a reference magnetic layer, a barrier layer, a first free magnetic layer and a second free magnetic layer. The barrier layer is above the reference magnetic layer. The first free magnetic layer is above the barrier layer. The second free magnetic layer is above the first free magnetic layer. A spacer layer is between the first free magnetic layer and the second free magnetic layer, and the spacer layer contains magnesium and a transition metal, wherein the atomic ratio of the magnesium to the transition metal is 15% to 80%.

[0004] According to an embodiment of the utility model, an integrated chip includes: a reference magnetic layer, a barrier layer, a first free magnetic layer and a second free magnetic layer. The barrier layer is above the reference magnetic layer. The first free magnetic layer is above the barrier layer. The second free magnetic layer is above the first free magnetic layer. A plurality of spacer films are disposed between the first free magnetic layer and the second free magnetic layer.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When reading the accompanying drawings, aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with industry practice, the various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view illustrating some embodiments of a memory device includes a magnetic tunneling junction (MTJ) including a spacer layer between a first free magnetic layer and a second free magnetic layer.

[0008] Figure 2 Show Figure 1A cross-sectional view of some embodiments of a memory device, wherein the spacer layer includes a first spacer film and a second spacer film.

[0009] Figure 3 Show Figure 2 A cross-sectional view of some embodiments of a memory device, wherein the spacer layer further includes a third spacer film.

[0010] Figure 4 Show Figure 1 A cross-sectional view of some embodiments of a memory device of the type shown in FIG. 1 , wherein atoms from a first free magnetic layer accumulate along an interface between the first free magnetic layer and a spacer layer.

[0011] Figure 5 Shown including Figure 1 Cross-sectional views of some embodiments of an integrated chip of a memory device.

[0012] Figure 6 Shown include Figure 1 Cross-sectional views of some other embodiments of integrated chips of memory devices.

[0013] Figure 7-Figure 13 Cross-sectional views of some embodiments of methods for forming a memory device including a magnetic tunneling junction (MTJ) including a spacer layer between a first free magnetic layer and a second free magnetic layer are shown.

[0014] Fig.14 A flow chart illustrating some embodiments of a method for forming a memory device including a magnetic tunneling junction (MTJ) including a spacer layer between a first free magnetic layer and a second free magnetic layer.

[0015] Description of Reference Numerals

[0016] 100, 200, 300, 400, 500, 600, 700, 700-1200, 700-1300, 800, 800-1000, 900, 1000, 1100, 1200, 1300: Sectional view

[0017] 102: First electrode layer

[0018] 104: Magnetic Tunneling Junction

[0019] 106: Reference magnetic layer

[0020] 108: Barrier layer

[0021] 110: First free magnetic layer

[0022] 110: Free magnetic layer

[0023] 112: Spacer layer

[0024] 114: Second free magnetic layer

[0025] 116: Top cover

[0026] 118: Second electrode layer

[0027] 202: First spacer film

[0028] 204: Second spacer film

[0029] 302: The third spacer film

[0030] 402: Atomic

[0031] 404: Accumulation Zone

[0032] 502: Substrate

[0033] 504: Transistor Device

[0034] 506: first source and drain region

[0035] 508: Second source and drain region

[0036] 510: Gate layer

[0037] 512: Source line

[0038] 514: Bit line

[0039] 516, 1306: Dielectric structure

[0040] 518, 520: Internal connection

[0041] 602: Write word line

[0042] 802, 804, 902, 904, 1002: Sputtering guns

[0043] 806, 906: magnesium target layer

[0044] 808, 908: Transition metal target layer

[0045] 810, 910: magnesium atom

[0046] 812, 912: Transition metal atoms

[0047] 1004: Target layer

[0048] 1202: Mask layer

[0049] 1302: Dielectric layer

[0050] 1304: Metal interconnect

[0051] 1400: Methods

[0052] 1402, 1404, 1404-1420, 1406, 1408, 1410, 1412: Box DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first and second features are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the utility model may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0054] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "above," and the like may be used herein to describe the relationship of one element or feature to another element(s) or feature(s), as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0055] The integrated chip includes a magnetic tunneling junction (MTJ) memory device. The magnetic tunneling junction includes a reference magnetic layer (e.g., a pinned magnetic layer or a fixed magnetic layer), a free magnetic layer above the reference magnetic layer, and a barrier layer directly between the reference magnetic layer and the free magnetic layer. The free magnetic layer includes a first free magnetic sublayer and a second free magnetic sublayer. The spacer layer is directly located in the free magnetic layer between the first free magnetic sublayer and the second free magnetic sublayer. The spacer layer includes a transition metal such as tungsten, molybdenum, tantalum, hafnium, etc. Back-end of line (BEOL) interconnects (e.g., metal lines, metal vias, etc.) are arranged on the MTJ.

[0056] During the formation of the BEOL interconnects, the MTJ is exposed to high temperatures (e.g., greater than 400 degrees Celsius). This high temperature exposure causes atoms to diffuse out of the first free magnetic sublayer. This diffusion can reduce the data retention capability of the MTJ. Therefore, the inclusion of a spacer layer above the first free magnetic sublayer can block atoms from diffusing out of the first free magnetic sublayer, thereby improving the thermal stability of the MTJ. The diffusion barrier capability of the spacer layer corresponds to the thickness of the spacer layer. For example, increasing the thickness of the spacer layer can improve the diffusion barrier capability of the spacer layer. However, as the thickness of the spacer layer increases, the magnetic coupling between the free magnetic sublayers decreases. The performance of the MTJ is thus reduced.

[0057] In various embodiments of the present invention, the spacer layer also includes magnesium to improve the thermal stability of the MTJ without substantially reducing the magnetic coupling between the free magnetic sublayers. For example, in addition to the transition metal, the spacer layer also includes magnesium, which has a smaller effect on the magnetic coupling between the free magnetic sublayers. Therefore, by adding magnesium to the spacer layer, the thickness of the spacer layer can be increased without reducing the magnetic coupling between the free magnetic sublayers. By increasing the thickness of the spacer layer, the diffusion barrier capability of the spacer layer can be improved. By improving the diffusion barrier capability of the spacer layer, the thermal stability of the MTJ can be improved.

[0058] Figure 1 A cross-sectional view 100 of some embodiments of a memory device is shown including a magnetic tunneling junction (MTJ) 104 that includes a spacer layer 112 between a first free magnetic layer 110 and a second free magnetic layer 114 .

[0059] The MTJ 104 is disposed between the first electrode layer 102 and the second electrode layer 118. The MTJ 104 includes a reference magnetic layer 106, a barrier layer 108, a first free magnetic layer 110, a spacer layer 112, a second free magnetic layer 114, and a cap layer 116. In some embodiments, the MTJ 104 is disposed on a substrate (e.g., Figure 5 and Figure 6 502) and one or more dielectric layers (e.g., Figure 5 and Figure 6 516). A reference magnetic layer 106 is on the first electrode layer 102. A first free magnetic layer 110 is on the reference magnetic layer 106. A barrier layer 108 is directly between the reference magnetic layer 106 and the first free magnetic layer 110. A second free magnetic layer 114 is on the first free magnetic layer 110. A spacer layer 112 is directly between the first free magnetic layer 110 and the second free magnetic layer 114. A cap layer 116 is on the second free magnetic layer 114. A second electrode layer 118 is on the cap layer 116. Back-end of line (BEOL) interconnects (e.g., Fig.13 1304 ) is above MTJ 104 .

[0060] The reference magnetic layer 106 has a fixed (e.g., fixed) magnetic orientation. The first free magnetic layer 110 and the second free magnetic layer 114 have a free (e.g., variable) magnetic orientation. The magnetic orientation of the free magnetic layers 110, 114 can be controlled by passing a current through the MTJ 104. The resistance of the MTJ 104 changes according to the magnetic orientation of the free magnetic layers 110, 114 relative to the magnetic orientation of the reference magnetic layer 106. The resistance of the MTJ 104 indicates the data (e.g., value) stored by the MTJ 104.

[0061] In some embodiments, the first free magnetic layer 110 includes cobalt-iron-boron (e.g., CoFeB) or some other suitable ferromagnetic material. In some cases, when the MTJ 104 is exposed to high temperatures (e.g., greater than 400 degrees Celsius) during the formation of BEOL interconnects on the MTJ 104, boron atoms diffuse out of the first free magnetic layer 110 (e.g., toward the top of the MTJ 104). As the boron atoms diffuse out of the first free magnetic layer 110, the crystallinity of the first free magnetic layer 110 increases. If the first free magnetic layer becomes too crystalline (e.g., if the crystallinity of the first free magnetic layer 110 exceeds a certain optimal crystallinity threshold), the data retention (e.g., perpendicular magnetic anisotropy (PMA) and / or energy barrier) of the MTJ 104 will be reduced. Therefore, the inclusion of the spacer layer 112 on the first free magnetic layer 110 can prevent boron from diffusing out of the first free magnetic layer 110. By preventing the diffusion of boron atoms out of the first free magnetic layer 110, the thermal stability of the MTJ 104 can be improved. For example, the amount of time that the MTJ 104 can be exposed to high temperatures (eg, during BEOL interconnect formation) without the MTJ 104 experiencing substantial data retention degradation can be increased.

[0062] The spacer layer 112 includes magnesium and one or more transition metals (e.g., tungsten, molybdenum, tantalum, hafnium, etc.). By including magnesium in the spacer layer 112, the ability of the spacer layer 112 to block the diffusion of boron atoms from the first free magnetic layer 110 can be improved (e.g., the rate at which boron atoms diffuse out of the first free magnetic layer 110 can be reduced) without substantially reducing the magnetic coupling between the first free magnetic layer 110 and the second free magnetic layer 114. For example, magnesium has a relatively small effect on the magnetic coupling between the free magnetic layers 110 and 114. Therefore, by adding magnesium to the spacer layer 112, the thickness of the spacer layer 112 can be increased without substantially reducing the magnetic coupling between the free magnetic layers 110 and 114. By increasing the thickness of the spacer layer 112, the diffusion barrier capability of the spacer layer 112 can be improved. By improving the diffusion barrier capability of the spacer layer 112, the thermal stability of the MTJ 104 can be improved. For example, the amount of time that the MTJ 104 can withstand high temperatures can be increased. Therefore, the number of BEOL interconnect layers that can be formed over the MTJ 104 may be increased.

[0063] Furthermore, by including transition metals and magnesium in the spacer layer 112, the magnesium in the spacer layer 112 has reduced oxidation sensitivity. Therefore, the performance of the MTJ 104 can be improved.

[0064] In some embodiments, the thickness of the spacer layer 112 ranges from 5% to 100% of the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114, the thickness of the spacer layer 112 ranges from 10% to 90% of the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114, or the thickness of the spacer layer 112 is some other suitable value. For example, in some embodiments, the thickness of the spacer layer 112 ranges from 0.1 nanometers to 1 nanometer, from 0.2 nanometers to 0.9 nanometers, or some other suitable range, and the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114 is 1 nanometer to 2 nanometers, 1.2 nanometers to 1.8 nanometers, or other suitable ranges. If the thickness of the spacer layer 112 is too small (e.g., less than 5% of the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114), the rate of boron diffusion of the first free magnetic layer 110 increases, and thus the thermal stability of the boron MTJ 104 decreases. If the thickness of the spacer layer 112 is too large (eg, greater than 100% of the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114 ), the magnetic coupling between the free magnetic layers 110 , 114 may be reduced and thus degrade the performance of the MTJ 104 .

[0065] In some embodiments, the atomic ratio of magnesium to transition metal in the spacer layer 112 is in a range of 10% to 90%, 15% to 80%, or some other suitable range. In some embodiments, if the atomic ratio of magnesium to transition metal is too high (e.g., greater than 90% magnesium, greater than 80% magnesium, or some other suitable value), the magnesium may be more easily oxidized and thus reduce the performance of the MTJ 104. If the atomic ratio of magnesium to transition metal is too low (e.g., greater than 90% transition metal, greater than 85% transition metal, or some other suitable value), the magnetic coupling between the free magnetic layers 110, 114 may be reduced.

[0066] In some embodiments, the first electrode layer 102 and the second electrode layer 118 include a metal, such as copper, aluminum, tungsten, ruthenium, or some other suitable material. In some embodiments, the reference magnetic layer 106, the first free magnetic layer 110, and the second free magnetic layer 114 include a ferromagnetic material, such as cobalt-iron-boron, or some other suitable material. In some embodiments, the barrier layer 108 and the cap layer 116 include a dielectric material, such as magnesium oxide, or some other suitable material.

[0067] Figure 2 Show Figure 1 A cross-sectional view 200 of some embodiments of a memory device, wherein the spacer layer 112 includes a first spacer film 202 and a second spacer film 204 .

[0068] The first spacer film 202 is on the first free magnetic layer 110. The second spacer film 204 is on the first spacer film 202. The second free magnetic layer 114 is on the second spacer film 204. The first spacer film 202 includes a first material, and the second spacer film 204 includes a second material, which is different from the first material.

[0069] In some embodiments, the first spacer film 202 includes magnesium, and the second spacer film 204 includes a transition metal (e.g., tungsten, molybdenum, tantalum, hafnium, etc.). In some other embodiments, the first spacer film 202 includes a transition metal (e.g., tungsten, molybdenum, tantalum, hafnium, etc.), and the second spacer film 204 includes magnesium. In some other embodiments, the first spacer film 202 includes magnesium and a first transition metal, and the second spacer film 204 includes magnesium and a second transition metal different from the first transition metal.

[0070] Figure 3 Show Figure 2 A cross-sectional view 300 of some embodiments of a memory device of the type shown in FIG. 1 , wherein the spacer layer further includes a third spacer film 302 .

[0071] The third spacer film 302 is interposed between the second spacer film 204 and the second free magnetic layer 114. The second spacer film 204 includes a material different from the first spacer film 202 and the third spacer film 302. For example, the first spacer film 202 includes a first material, the second spacer film 204 includes a second material, and the third spacer film 302 includes a third material, wherein the second material is different from the first material and the third material. In some embodiments, the third material is the same as the first material.

[0072] In some embodiments, the first spacer film 202 includes magnesium, the second spacer film 204 includes a transition metal (e.g., tungsten, molybdenum, tantalum, hafnium, etc.), and the third spacer film 302 includes magnesium. In some other embodiments, the first spacer film 202 includes a transition metal, the second spacer film 204 includes magnesium, and the third spacer film 302 includes a transition metal. In some other embodiments, the first spacer film 202 includes magnesium and a first transition metal, the second spacer film 204 includes magnesium and a second transition metal, and the third spacer film 302 includes magnesium and a third transition metal, wherein the second transition metal is different from the first transition metal and the third transition metal.

[0073] Figure 4 Show Figure 1 A cross-sectional view 400 of some embodiments of a memory device of FIG. 1 , wherein atoms 402 from the first free magnetic layer 110 accumulate along an interface between the first free magnetic layer 110 and the spacer layer 112 .

[0074] For example, a plurality of boron atoms 402 are within the first free magnetic layer 110 along a top surface of the first free magnetic layer 110, where the first free magnetic layer 110 borders the spacer layer 112. This region along the top surface of the first free magnetic layer 110 where the boron atoms 402 are accumulated may be referred to as a boron accumulation region 404. These atoms 402 may accumulate along the interface (e.g., at the accumulation region 404) due to being blocked by the spacer layer 112 at the interface. In some embodiments, the concentration of the boron atoms 402 in the first free magnetic layer 110 decreases as the distance increases from the interface between the first free magnetic layer 110 and the spacer layer 112.

[0075] In some embodiments, there are a plurality of boron atoms 402 within the spacer layer 112. These atoms have diffused from the first free magnetic layer 110 into the spacer layer 112. In some embodiments, the concentration of boron atoms in the spacer layer 112 decreases with increasing distance from the first free magnetic layer 110. Furthermore, in some embodiments where the spacer layer 112 includes a plurality of spacer films (e.g., Figure 2 and Figure 3), the concentration of boron atoms in the spacer layer 112 is higher in the spacer film closest to the first free magnetic layer 110 and decreases with increasing distance from the first free magnetic layer 110. For example, in some embodiments, the concentration of boron atoms in the first spacer film (e.g., Figure 2 and Figure 3 202) is greater than the concentration of boron atoms in the second spacer film (e.g., Figure 2 and Figure 3 204), and the concentration of boron atoms in the second spacer film (e.g. Figure 2 and Figure 3 204) is greater than the concentration of boron atoms in the third spacer film (e.g. Figure 3 302 in the above).

[0076] Figure 5 Shown including Figure 1 A cross-sectional view 500 of some embodiments of an integrated chip of a memory device.

[0077] Figure 6 Shown include Figure 1 A cross-sectional view 600 of some other embodiments of an integrated chip of a memory device.

[0078] In some embodiments (e.g., Figure 5 ), the integrated chip includes a spin transfer torque (STT) magnetoresistive random access memory (MRAM) device, wherein the MTJ 104 is coupled between the transistor device 504 and the bit line 514. For example, the transistor device 504 is arranged along the semiconductor substrate 502. The transistor device 504 includes a first source drain region 506, a second source drain region 508, and a gate layer 510. A dielectric structure 516 including one or more dielectric layers is on the substrate 502. The source line 512 is on the substrate 502 and within the dielectric structure 516. The source line 512 is coupled to the first source drain region 506 through an internal connection 518 (e.g., a metal contact, etc.). The MTJ 104 is on the substrate 502 and within the dielectric structure 516. The first electrode layer 102 is coupled to the second source drain region 508 through an internal connection 520 (e.g., a metal contact, etc.). The bit line 514 is above the MTJ 104 and within the dielectric structure 516. The second electrode layer 118 is coupled to the bit line 514. In some embodiments, the gate layer 510 forms a word line. In some other embodiments, the gate layer 510 is coupled to a word line (not shown).

[0079] In some embodiments (e.g., Figure 6), the integrated chip includes a spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device, wherein the MTJ 104 is coupled between the write word line 602 and the bit line 514. In some embodiments, the orientation of the MTJ 104 is reversed so that the reference magnetic layer 106 is above the free magnetic layers 110, 114. The write word line 602 is coupled to the second source drain region 508 and the second electrode layer 118. The bit line 514 is coupled to the first electrode layer 102. In some embodiments, the gate layer 510 forms a read word line. In some other embodiments, the gate layer 510 is coupled to a read word line (not shown).

[0080] In some embodiments, transistor device 504 is a metal oxide field effect transistor, a junction field effect transistor, a fin field effect transistor, a wrap-around gate field effect transistor, or some other suitable device. In some embodiments, the source drain region may refer to a source or a drain, either individually or collectively, depending on the context. In some embodiments, source line 512, bit line 514, and write word line 602 include metal (e.g., copper, tungsten, aluminum, etc.) or some other suitable material.

[0081] Figure 7-Figure 13 Cross-sectional views 700-1300 of some embodiments of methods for forming a memory device including a magnetic tunneling junction (MTJ) 104 including a spacer layer 112 between a first free magnetic layer 110 and a second free magnetic layer 114 are shown. Figure 7-Figure 13 is described in terms of methods, but it should be understood that Figure 7-Figure 13 The structure disclosed in is not limited to such a method, but can exist alone as a structure independent of the method.

[0082] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , a reference magnetic layer 106 is deposited on the first electrode layer 102. In some embodiments, the first electrode layer 102 includes copper, tungsten, aluminum, or some other suitable material. In some embodiments, the reference magnetic layer 106 includes cobalt-iron-boron or some other suitable material. In some embodiments, the reference magnetic layer 106 is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0083] In addition, a barrier layer 108 is deposited over the reference magnetic layer 106. In some embodiments, the barrier layer 108 includes magnesium oxide or some other suitable material. In some embodiments, the barrier layer 108 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0084] In addition, a first free magnetic layer 110 is deposited on the barrier layer 108. In some embodiments, the first free magnetic layer 110 includes cobalt-iron-boron or some other suitable material. In some embodiments, the first free magnetic layer 110 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0085] Figure 8 Some embodiments of a cross-sectional view 800 of a first method for forming a spacer layer 112 above a first free magnetic layer 110 are shown. Figure 8 As shown in the cross-sectional view 800 of , the spacer layer 112 is deposited by a co-sputtering process, in which two or more sputtering guns 802, 804 (e.g., magnetron cathodes) are used simultaneously. For example, the first sputtering gun 802 has a magnesium target layer 806, and the second sputtering gun 804 has a transition metal target layer 808. Atoms from the target layers 806, 808 are sputtered concurrently (e.g., simultaneously) on the first free magnetic layer 110 to form the spacer layer 112. Therefore, in some embodiments, the spacer layer 112 includes various arrangements of magnesium atoms 810 and transition metal atoms 812.

[0086] Fig. 9 Some embodiments of a cross-sectional view 900 of a second method for forming a spacer layer 112 on the first free magnetic layer 110 are shown. Fig. 9 As shown in the cross-sectional view 900 of , the spacer layer 112 is deposited by an alternating sputtering process in which two or more sputtering guns 902, 904 are used alternately. For example, a first sputtering gun 902 has a magnesium target layer 906 and a second sputtering gun 904 has a transition metal target layer 908. Atoms from the target layers 906, 908 are sputtered on the first free magnetic layer 110 in an alternating manner to form the spacer layer 112. For example, for a first time period, atoms from one of the target layers (e.g., 906) are sputtered onto the first free magnetic layer 110, and for a subsequent second time period, atoms from another of the target layers (e.g., 908) are sputtered onto the first free magnetic layer 110. First free magnetic layer 110. Therefore, in some embodiments, the spacer layer 112 includes alternating stacked or thin film magnesium atoms 910 and thin film or transition metal atoms 912.

[0087] Fig.10 A cross-sectional view 1000 of some embodiments of a third method for forming a spacer layer 112 on a first free magnetic layer 110 is shown. Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , the spacer layer 112 is deposited by a direct sputtering process using a single sputtering gun 1002. For example, a sputtering gun 1002 having a target layer 1004 containing magnesium and a transition metal is used. Atoms in the target layer 1004 are sputtered onto the first free magnetic layer 110.

[0088] The spacer layer 112 is formed such that the atomic ratio of magnesium to transition metal in the spacer layer 112 is in a range of 10% to 90%, 15% to 80%, or some other suitable range. In addition, the spacer layer 112 is formed such that the thickness of the spacer layer 112 is in a range of 5%-100% of the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114, 10% to 90% of the sum, or some other suitable percentage sum. For example, in some embodiments, the thickness of the spacer layer 112 ranges from 0.1±nm to 1±nm, from 0.2±nm to 0.9±nm, or some other suitable range and the sum of the thickness of the first free magnetic layer 110 and the thickness of the second free magnetic layer 114 ranges from 1nm to 2nm, from 1.2nm to 1.8nm, or some other suitable range.

[0089] In some embodiments, multiple spacer films (e.g., Figure 2 and Figure 3 The first spacer film 202, the second spacer film 204, and the third spacer film 302 are deposited on the first free magnetic layer 110. For example, the first spacer film including a first material is deposited on the first free magnetic layer 110, the second spacer film including a second material different from the first material is deposited on the first spacer film, and the third spacer film including a third material different from the second material is deposited on the second spacer film. In some embodiments, the stack of spacer films is formed in an alternating sputtering process.

[0090] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , the second free magnetic layer 114 is deposited on the spacer layer 112. In some embodiments, the second free magnetic layer 114 includes cobalt-iron-boron or some other suitable material. In some embodiments, the second free magnetic layer 114 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0091] A cap layer 116 is deposited on the second free magnetic layer 114. In some embodiments, the cap layer 116 includes magnesium oxide or some other suitable material. In some embodiments, the cap layer 116 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0092] The second electrode layer 118 is deposited on the cap layer 116. In some embodiments, the second electrode layer 118 includes copper, tungsten, aluminum, or some other suitable material. In some embodiments, the second electrode layer 118 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0093] like Fig.12As shown in the cross-sectional view 1200 of , the second electrode layer 118, the cap layer 116, the second free magnetic layer 114, the spacer layer 112, the first free magnetic layer 110, the barrier layer 108, the reference magnetic layer 106 and the first electrode layer 102 are etched to define the MTJ 104. In some embodiments, a mask layer 1202 is formed above the second electrode layer 118, and etching is performed according to the mask layer 1202. In some embodiments, the mask layer 1202 may, for example, include a photoresist mask, a hard mask, etc. In some embodiments, etching includes one or more dry etching processes (e.g., plasma etching, reactive ion etching, ion beam etching, etc.) or some other suitable etching processes. In some embodiments, the mask layer 1202 is removed during and / or after etching.

[0094] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a dielectric layer 1302 is deposited over the MTJ 104 and on opposite sides of the MTJ 104. In addition, a plurality of metal interconnects 1304 are formed over the MTJ 104 within the dielectric structure 1306. During the formation of the metal interconnects 1304, the MTJ 104 is exposed to an elevated temperature (e.g., a temperature greater than 400 degrees Celsius) for a prolonged period of time (e.g., greater than 5 hours, greater than 6 hours, greater than 7 hours, or other suitable time).

[0095] In some embodiments, some of the boron atoms from the first free magnetic layer 110 diffuse out of the first free magnetic layer 110 during the formation of the metal interconnect 1304 (e.g., when the MTJ 104 is exposed to high temperatures). By including the spacer layer 112 on the first free magnetic layer 110, the rate at which boron diffuses out of the first free magnetic layer 110 can be reduced. In some embodiments, the boron atoms are arranged in the spacer layer 112 after the BEOL interconnect is formed due to diffusion. In some embodiments, during the BEOL formation, the boron atoms are arranged along the interface between the first free magnetic layer 110 and the spacer layer 112 (e.g., as shown in FIG. 1 ). Figure 4 shown) cumulatively.

[0096] In some embodiments, after exposure to high temperature, the data retention of MTJ 104 is substantially the same as before exposure due to improved thermal stability provided by spacer layer 112. For example, in some embodiments, MTJ 104 has a first energy barrier (e.g., the energy required to change the state of MTJ from a parallel magnetic state to an antiparallel magnetic state or vice versa) before forming BEOL interconnect 1304. It has a second energy barrier after forming BEOL interconnect 1304 (e.g., after an extended period of exposure to high temperature), where the first energy barrier is approximately equal to the second energy barrier. In some embodiments, the difference between the first energy barrier and the second energy barrier is less than 10%, less than 5%, or some other suitable value. Thus, spacer layer 112 can prevent data retention of MTJ 104 from being degraded during high temperature exposure.

[0097] Fig.14 A flowchart of some embodiments of a method 1400 for forming a memory device including a magnetic tunneling junction (MTJ) is shown, the MTJ including a spacer layer between a first free magnetic layer and a second free magnetic layer. Although method 1400 is illustrated and described below as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those shown and / or described herein. In addition, all illustrated actions may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0098] At block 1402 , a magnetic tunneling junction is formed on a substrate. Figure 7-Figure 12 Cross-sectional views 700-1200 are shown corresponding to some embodiments of block 1402. In some embodiments, block 1402 includes blocks 1404-1420.

[0099] At block 1404, a first electrode layer is deposited on a substrate. Figure 7 A cross-sectional view 700 corresponding to some embodiments of block 1404 is shown.

[0100] At block 1406 , a reference magnetic layer is deposited over the first electrode layer. Figure 7 A cross-sectional view 700 corresponding to some embodiments of block 1406 is shown.

[0101] At block 1408 , a barrier layer is deposited over the reference magnetic layer. Figure 7 A cross-sectional view 700 corresponding to some embodiments of block 1408 is shown.

[0102] At block 1410 , a first free magnetic layer is deposited over the barrier layer. Figure 7A cross-sectional view 700 corresponding to some embodiments of block 1410 is shown.

[0103] At block 1412 , a spacer layer comprising magnesium and a transition metal is deposited on the first free magnetic layer. Figure 8-10 Cross-sectional views 800-1000 of various embodiments corresponding to block 1412 are shown. For example, in some embodiments, a spacer layer (e.g., such as Figure 8 In some other embodiments, the spacer layer is deposited using an alternating sputtering process (e.g., as shown in FIG. Fig. 9 In other embodiments, the spacer layer is deposited using a direct sputtering process (e.g., as shown in FIG. Fig.10 In some embodiments, depositing a spacer layer includes depositing a plurality of spacer films (e.g., Figure 2 and Figure 3 shown).

[0104] At block 1414 , a second free magnetic layer is deposited over the spacer layer. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of block 1414 .

[0105] At block 1416 , a cap layer is deposited over the second free magnetic layer. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of block 1416 .

[0106] At block 1418, a second electrode layer is deposited over the cap layer. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of block 1418 .

[0107] At block 1420, the second electrode layer, the cap layer, the second free magnetic layer, the spacer layer, the first free magnetic layer, the barrier layer, the reference magnetic layer, and the first electrode layer are etched. The etching defines a magnetic tunneling junction. Fig.12 A cross-sectional view 1200 is shown corresponding to some embodiments of block 1420 .

[0108] At block 1422, a plurality of back-end metal interconnects are formed over the magnetic tunneling junction. In some embodiments, the magnetic tunneling junction is exposed to high temperatures during BEOL interconnect fabrication. Because the spacer layer improves the thermal stability of the magnetic tunneling junction, the magnetic tunneling junction can withstand BEOL interconnect fabrication without suffering substantial performance degradation. Fig.13 A cross-sectional view of some embodiments corresponding to block 1422 is shown. Fig.13 .

[0109] Therefore, the present invention relates to a magnetic tunneling junction including a spacer layer and a method of forming a magnetic tunneling junction, wherein the spacer layer contains magnesium and a transition metal to reduce diffusion in the magnetic tunneling junction.

[0110] Therefore, in some embodiments, the utility model relates to an integrated chip, including a reference magnetic layer and a barrier layer on the reference magnetic layer. A first free magnetic layer is on the barrier layer. A second free magnetic layer is on the first free magnetic layer. A spacer layer is between the first free magnetic layer and the second free magnetic layer. The spacer layer contains magnesium and a transition metal. The atomic ratio of magnesium to the transition metal is in the range of 15% to 80%.

[0111] In an embodiment of the present invention, the spacer layer includes a first spacer film on the first free magnetic layer and a second spacer film on the first spacer film, the first spacer film includes magnesium, and the second spacer film includes the transition metal. In an embodiment of the present invention, the spacer layer also includes a third spacer film on the second spacer film, and the third spacer film includes magnesium. In an embodiment of the present invention, the spacer layer includes a first spacer film on the first free magnetic layer and a second spacer film on the first spacer film, the first spacer film includes the transition metal, and the second spacer film includes magnesium. In an embodiment of the present invention, the spacer layer also includes a third spacer film on the second spacer film, and the third spacer film includes the transition metal. In an embodiment of the present invention, the first free magnetic layer has a first thickness, the second free magnetic layer has a second thickness, the spacer layer has a third thickness, and the third thickness ranges from 5% to 100% of the sum of the first thickness and the second thickness. In an embodiment of the present invention, the first free magnetic layer includes boron, and the spacer layer also includes boron. In an embodiment of the present invention, the first free magnetic layer includes boron, wherein the first free magnetic layer borders the spacer layer along an interface, and wherein a concentration of boron atoms in the first free magnetic layer decreases with increasing distance from the interface.

[0112] In other embodiments, the utility model relates to an integrated chip, comprising: a reference magnetic layer, a barrier layer, a first free magnetic layer and a second free magnetic layer. The barrier layer is above the reference magnetic layer. The first free magnetic layer is above the barrier layer. The second free magnetic layer is above the first free magnetic layer. A plurality of spacer films are interposed between the first free magnetic layer and the second free magnetic layer.

[0113] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present disclosure.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated chip, characterized in that: include: Reference magnetic layer; a barrier layer on the reference magnetic layer; a first free magnetic layer on the barrier layer; a second free magnetic layer, on the first free magnetic layer; as well as A plurality of spacer layers are disposed between the first free magnetic layer and the second free magnetic layer, wherein the first free magnetic layer has a first thickness, the second free magnetic layer has a second thickness, the spacer layer has a third thickness, and wherein the third thickness ranges from 5% to 100% of the sum of the first thickness and the second thickness.

2. The integrated chip according to claim 1, characterized in that: The spacer layer comprises: a first spacer film on the first free magnetic layer; a second spacer film on the first spacer film; and a third spacer film, on top of the second spacer film, The first spacer film and the third spacer film include the same material, and the second spacer film includes a material different from that of the first spacer film and the third spacer film.

3. The integrated chip according to claim 1, characterized in that: The first free magnetic layer includes boron.

4. The integrated chip according to claim 3, characterized in that: The first free magnetic layer borders the spacer layer along an interface, and a concentration of boron atoms in the first free magnetic layer decreases with increasing distance from the interface.

Images