PGaN gate GaN power device structure with gate-last process
By etching PGaN of the periodically arranged long and short gate regions on the epitaxial of the GaN channel layer, and combining the periodically arranged gate metal, the rear gate process is realized, solving the problem that the back gate process is difficult to achieve in short-gate long PGaN gate GaN power devices, and improving the reliability and performance of the device.
Patent Information
- Application Number
- CN202420735411.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-10
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-04-10
AI Technical Summary
In short gate length PGaN gate GaN power devices, the rear gate process is difficult to achieve because the gate area PGaN length is small and it is impossible to directly etch the hole after ohmic contact.
By etching the PGaN of the periodically arranged long gate long region and short gate long region on the epitaxial of the GaN channel layer, and combining the periodically arranged gate metal, the channels under the gate are turned on and off, thereby realizing the rear gate process.
It effectively avoids gate Schottky contact degradation caused by ohmic contact high temperature annealing, reduces gate leakage current, improves device reliability, and is suitable for low-voltage GaN power devices.
Smart Images
Figure CN222602897U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a PGaN gate GaN power device structure with a gate-last process. Background Art
[0002] Gallium nitride is one of the representatives of the third-generation semiconductor materials. Compared with traditional semiconductor power devices such as Si-based ones, power devices based on gallium nitride materials have significant advantages such as higher breakdown voltage, lower on-resistance, and higher thermal conductivity.
[0003] The core structure of GaN power devices is AlGaN / GaN heterojunction. Due to piezoelectric polarization and spontaneous polarization, a two-dimensional electron gas with high concentration and high electron mobility will be generated at the interface of AlGaN / GaN heterojunction. Ordinary GaN power devices are depletion type, but in practical applications, in order to reduce the difficulty of drive design and ensure the safe operation of the device, the device needs to be designed as enhancement type. The solutions for GaN power devices to achieve enhancement type can be mainly divided into PGaN gate, groove gate, ultra-thin barrier layer, F ion implantation, etc. At present, PGaN gate structure is the mainstream enhancement type implementation solution, and PGaN gate structure has been commercialized on a large scale.
[0004] PGaN gate GaN power devices can be divided into two types according to the order of gate metal process: gate-first process and gate-last process. The gate-first process is to make the gate metal before the ohmic contact process, while the gate-last process is to make the gate metal after the ohmic contact process. The advantage of the gate-first process is that it can achieve self-alignment, so it is suitable for PGaN gate GaN power devices with shorter gate lengths, which are generally used in low-voltage fields. The advantage of the gate-last process is that it avoids the influence of ohmic contact annealing on the gate metal and can obtain better gate Schottky contact. It is very difficult to have a gate-last process in PGaN gate GaN power devices with short gate lengths because the PGaN length in the gate area is small, so it is impossible to etch holes directly after the ohmic contact. Utility Model Content
[0005] In view of the above problems, the utility model provides a PGaN-gate GaN power device structure with a gate-last process.
[0006] The technical solution adopted is a PGaN gate GaN power device structure with a gate-last process, including a substrate layer, a buffer layer, a GaN channel layer, an AlGaN barrier layer and an insulating dielectric layer, wherein PGaN is also included, and the PGaN is etched on the epitaxy of the GaN channel layer;
[0007] The PGaN includes a long gate length region and a short gate length region, and the long gate length region and the short gate length region are periodically arranged;
[0008] A gate metal is disposed on the PGaN, and a source ohmic metal and a drain ohmic metal are disposed on both sides of the PGaN respectively.
[0009] Optionally, a first gate through hole is arranged above the gate metal, and a first layer of gate interconnection metal is arranged above the first gate through hole.
[0010] Optionally, a gate second through hole is arranged above the gate first layer interconnection metal, and a gate second layer interconnection metal is arranged above the gate second through hole, and the gate second layer interconnection metal forms a gate pad.
[0011] Optionally, a source first through hole is arranged above the source ohmic metal, and a source first layer interconnection metal is arranged above the source first through hole.
[0012] Optionally, a source second through hole is arranged above the source first layer interconnection metal, and a source second layer interconnection metal is arranged above the source second through hole, and the source second layer interconnection metal forms a source pad.
[0013] Optionally, a drain first through hole is arranged above the drain ohmic metal, and a drain first layer interconnection metal is arranged above the drain first through hole.
[0014] Optionally, a drain second through hole is arranged above the drain first layer interconnection metal, and a drain second layer interconnection metal is arranged above the drain second through hole, and the drain second layer interconnection metal forms a drain pad.
[0015] The beneficial effects of the present utility model include at least one of the following:
[0016] 1. By setting periodically arranged long gate length regions and short gate length regions, the gate metal is also arranged periodically, and the opening and closing of the channel under the gate is controlled by the periodically arranged gate metal, thereby having a gate-last process.
[0017] 2. It can effectively avoid the gate Schottky contact degradation caused by high temperature annealing of the ohmic contact, thereby effectively reducing the gate leakage current and improving the device reliability. This structure is more suitable for low-voltage GaN power devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 A schematic diagram of the structure of a PGaN-gate GaN power device with a gate-last process;
[0019] Figure 2 It is a schematic diagram of the structure of the long gate length region;
[0020] Figure 3 It is a schematic diagram of the structure of the short gate length region;
[0021] The reference numerals are: 101 is PGaN, 101-1 is a long gate length region, 101-2 is a short gate length region, 102 is a gate metal, 103 is a first gate through hole, 104 is a first layer of gate interconnection metal, 105 is a source ohmic metal, 106 is a first source through hole, 107 is a first layer of source interconnection metal, 108 is a second source through hole, 109 is a second layer of source interconnection metal, 110 is a second gate through hole, 111 is 112 is the gate pad, 113 is the drain ohmic metal, 114 is the drain first through hole, 115 is the drain first layer interconnection metal, 116 is the drain second through hole, 117 is the drain second layer interconnection metal, 118 is the drain pad, 119 is the ion implantation isolation region, 120 is the substrate layer, 121 is the buffer layer, 122 is the GaN channel layer, 123 is the AlGaN barrier layer, and 124 is the insulating dielectric layer. DETAILED DESCRIPTION
[0022] The following describes the implementation of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0023] It should be noted that the illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0024] like Figures 1 to 3 As shown, a PGaN gate GaN power device structure with a gate-last process includes a substrate layer 120, a buffer layer 121, a GaN channel layer 122, an AlGaN barrier layer 123 and an insulating dielectric layer 124, wherein the PGaN 101 is also included, and the PGaN 101 is etched on the epitaxy of the GaN channel layer 122;
[0025] The PGaN 101 includes a long gate length region 101 - 1 and a short gate length region 101 - 2 , and the long gate length region 101 - 1 and the short gate length region 101 - 2 are periodically arranged;
[0026] A gate metal 102 is disposed above the PGaN 101 , and a source ohmic metal 105 and a drain ohmic metal 113 are disposed on both sides of the PGaN 101 .
[0027] The purpose of this design is to arrange the long gate length region and the short gate length region periodically so that the gate metal is also arranged periodically, and the opening and closing of the channel under the gate is controlled by the periodically arranged gate metal, so as to have a gate-last process. It can effectively avoid the degradation of the gate Schottky contact caused by the high temperature annealing of the ohmic contact, thereby effectively reducing the gate leakage current and improving the reliability of the device.
[0028] At the same time, in the present embodiment, a first gate through hole 103 is arranged above the gate metal 102, and a first gate layer interconnection metal 104 is arranged above the first gate through hole 103, a second gate through hole 110 is arranged above the first gate layer interconnection metal 104, and a second gate layer interconnection metal is arranged above the second gate through hole 110, and the second gate layer interconnection metal forms a gate pad 111.
[0029] At the same time, a first source through hole 106 is arranged above the source ohmic metal 105, and a first source layer interconnection metal 107 is arranged above the first source through hole 106, a second source through hole 108 is arranged above the first source layer interconnection metal 107, and a second source layer interconnection metal 109 is arranged above the second source through hole 108, and the second source layer interconnection metal 109 forms a source pad 112.
[0030] Furthermore, a first drain through hole 114 is arranged above the drain ohmic metal 113, and a first drain layer interconnection metal 115 is arranged above the first drain through hole 114, a second drain through hole 116 is arranged above the first drain layer interconnection metal 115, and a second drain layer interconnection metal 117 is arranged above the second drain through hole 116, and the second drain layer interconnection metal 117 forms a drain pad 118.
[0031] It should be noted that, in order to implement the unique structure provided by this embodiment, this embodiment provides an implementation method, including the following steps:
[0032] S1. First, PgaN101 is etched on the GaN epitaxy to form a shape;
[0033] S2. Then, a surface passivation layer is grown and the surface passivation layer is etched to open holes, source and drain ohmic metals are deposited in the surface passivation layer etched opening regions, and the ohmic metals are etched to form source ohmic metal 105 and drain ohmic metal 113;
[0034] S3. High temperature annealing is performed on the ohmic metal to form an ohmic contact, ion implantation is performed outside the ion implantation isolation region 119 to achieve device isolation, a first insulating dielectric layer is grown and the layer is etched to expose the gate metal 102 region;
[0035] S4. Depositing gate metal and etching the gate metal to retain the gate metal in the region, growing a second insulating dielectric layer and etching it to form a first gate through hole 103, a first source through hole 106 and a first drain through hole 114, and filling the first gate through hole 103, the first source through hole 106 and the first drain through hole 114 with W metal;
[0036] S5. Depositing a first layer of interconnect metal and etching it to form a first layer of gate interconnect metal 104, a first layer of source interconnect metal 107 and a first layer of drain interconnect metal 115;
[0037] S6. growing a third insulating dielectric layer and etching it to form a second source through hole 108, a second gate through hole 110 and a second drain through hole 116, and filling the second through hole 108, the second gate through hole 110 and the second drain through hole 116 with W metal;
[0038] S7 . Deposit a second layer of interconnect metal and etch it to form a second layer of interconnect metal 109 , a gate pad 111 , a source pad 112 , a drain second layer of interconnect metal 117 , and a drain pad 118 .
[0039] In this way, a PGaN-gate GaN power device structure with a gate-last process is obtained. The PGaN is formed into a shape with a part long and a part short by photolithography and dry etching. The longer part of the PGaN can be used to etch and open the medium above the PGaN, and then the gate metal is deposited. After metal etching, part of the gate metal is retained to form the gate metal, and the gate metal is periodically arranged along the gate width direction. In this structure, the shorter part of the PGaN is used to reduce the channel resistance under the gate, and the longer part of the PGaN is used to make the gate metal etching opening. The opening and closing of the channel under the gate is controlled by the periodically arranged gate metal, so that the structure provided in this embodiment can have a gate-last process.
[0040] Finally, holes are etched above the long gate length area of PGaN and gate metal is deposited. The periodically arranged gate metals are interconnected through the first layer of interconnect metal to achieve equal potential. In the specific manufacturing, the source and drain ohmic metals are formed first, and then the gate metal is formed. The gate metal forms a Schottky contact with PGaN.
[0041] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A PGaN gate GaN power device structure with a gate-last process, comprising a substrate layer (120), a buffer layer (121), a GaN channel layer (122), an AlGaN barrier layer (123) and an insulating dielectric layer (124), characterized in that: It also includes PGaN (101), and the PGaN (101) is etched on the epitaxy of the GaN channel layer (122); The PGaN (101) comprises a long gate length region (101-1) and a short gate length region (101-2), and the long gate length region (101-1) and the short gate length region (101-2) are arranged periodically; A gate metal (102) is disposed above the PGaN (101), and a source ohmic metal (105) and a drain ohmic metal (113) are disposed on both sides of the PGaN (101).
2. The PGaN gate GaN power device structure with gate-last process according to claim 1, characterized in that: A first gate through hole (103) is arranged above the gate metal (102), and a first layer of gate interconnection metal (104) is arranged above the first gate through hole (103).
3. The PGaN-gate GaN power device structure with a gate-last process according to claim 2, characterized in that: A gate second through hole (110) is arranged above the gate first layer interconnection metal (104), and a gate second layer interconnection metal is arranged above the gate second through hole (110), and the gate second layer interconnection metal forms a gate pad (111).
4. The PGaN gate GaN power device structure with gate-last process according to claim 1, characterized in that: A source first through hole (106) is arranged above the source ohmic metal (105), and a source first layer interconnection metal (107) is arranged above the source first through hole (106).
5. The PGaN gate GaN power device structure with gate-last process according to claim 4, characterized in that: A source second through hole (108) is arranged above the source first layer interconnection metal (107), and a source second layer interconnection metal (109) is arranged above the source second through hole (108), and the source second layer interconnection metal (109) forms a source pad (112).
6. The PGaN gate GaN power device structure with gate-last process according to claim 1, characterized in that: A drain first through hole (114) is arranged above the drain ohmic metal (113), and a drain first layer interconnection metal (115) is arranged above the drain first through hole (114).
7. The PGaN-gate GaN power device structure with a gate-last process according to claim 6, characterized in that: A drain second through hole (116) is arranged above the drain first layer interconnection metal (115), and a drain second layer interconnection metal (117) is arranged above the drain second through hole (116), and the drain second layer interconnection metal (117) forms a drain pad (118).