Semiconductor structure

Abstract

The utility model provides a semiconductor structure which comprises a substrate and a metal layer arranged in the substrate. The semiconductor structure includes a dielectric layer disposed over the metal layer. The semiconductor structure also includes a semiconductor layer disposed over the dielectric layer, wherein the metal layer extends through the semiconductor layer. The semiconductor layer includes a two-dimensional grating coupler and a pair of tapered structures extending laterally from the two-dimensional grating coupler, the two-dimensional grating coupler including a plurality of scattering elements disposed in the semiconductor layer.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor structure. Background Art

[0002] Silicon photonics technology is emerging as an important player in high-speed optical data communications. For example, optical transceiver modules including high-speed phase modulators, grating couplers, and waveguides are used in high-speed optical communication systems. The optical transceiver modules comply with various international standard specifications, and the communication speed is up to 100Gbps or more. The performance of the optical transceiver module is determined by the coupling efficiency of the grating coupler module with the optical transceiver module. Although the existing grating coupler structures for optical transceiver modules are generally adequate, they are not completely satisfactory in all aspects. For example, the input provided to the grating coupler from the optical fiber may pass through the semiconductor layer on which the grating coupler is formed, which may impair the overall coupling efficiency of the grating coupler. Utility Model Content

[0003] A semiconductor structure of an embodiment of the utility model includes a substrate, a metal layer, a dielectric layer and a semiconductor layer. The metal layer is arranged in the substrate. The dielectric layer is arranged on the metal layer. The semiconductor layer is arranged on the dielectric layer. The metal layer extends across the semiconductor layer. The semiconductor layer includes a two-dimensional grating coupler and a pair of conical structures. The two-dimensional grating coupler includes a plurality of scattering elements arranged in the semiconductor layer. The pair of conical structures extend laterally from the two-dimensional grating coupler.

[0004] A semiconductor structure of an embodiment of the utility model includes a first semiconductor layer, a metal layer, a dielectric layer and a second semiconductor layer. The metal layer is embedded in the first semiconductor layer. The dielectric layer is arranged on the metal layer. The second semiconductor layer is arranged above the dielectric layer and overlaps with the metal layer. The second semiconductor layer includes a grating coupler, a pair of conical structures and a pair of waveguides. The grating coupler has a plurality of scattering elements arranged in an apodization pattern. A pair of conical structures extend from the grating coupler. Each conical structure couples the grating coupler to a corresponding waveguide.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be increased or reduced at will.

[0007] Figure 1 is a block diagram of an example optical transceiver according to some embodiments of the present invention.

[0008] Figure 2 is a top view of an example photonic die with a two-dimensional (2D) grating coupler according to some embodiments of the present invention.

[0009] Figure 3 According to some embodiments of the present invention Figure 2 A cross-sectional view of an example photonic die along line AA'.

[0010] Figure 4 is an example two-dimensional grating coupler (such as Figure 2 and Figure 3 A top view of a portion of an example photonic crystal grain.

[0011] Figure 5 According to some embodiments of the present invention Figure 4 Top view of the grating pattern of an example two-dimensional grating coupler.

[0012] Figure 6 According to some embodiments of the present invention Figure 4 Top view of an example of a scattering element of a two-dimensional grating coupler.

[0013] Figure 7 and Figure 8 Each is according to some embodiments of the present invention Figure 6 Cross-sectional view of the scattering element along line BB'.

[0014] Fig. 9 is an example two-dimensional grating coupler (such as Figure 2 and Figure 3 A top view of a portion of an example photonic crystal grain.

[0015] Fig.10 According to some embodiments of the present invention Fig. 9 Top view of an example of a scattering element of a two-dimensional grating coupler.

[0016] Fig.11 is an example two-dimensional grating coupler (such as Figure 2 and Figure 3 A top view of a portion of an example photonic crystal grain.

[0017] Fig.12 and Fig.13 Each is according to some embodiments of the present invention Fig.11 Top view of an example of a scattering element of a two-dimensional grating coupler.

[0018] Fig.14 According to some embodiments of the present invention, the manufacturing method of Figure 2 and Figure 3 A flow chart of an example method of fabricating a semiconductor structure of an example photonic grain.

[0019] Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 and Fig.29 is based on Fig.14 A cross-sectional view of a semiconductor structure during an intermediate stage of an exemplary method of some embodiments of the present invention. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the second feature. The first and second features, so that the first and second features may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0022] Figure 1A block diagram of an example optical transceiver 100 is shown. The optical transceiver 100 may include an optical modulator 117, a monitoring photodiode 113, grating couplers 115 and 121. The optical transceiver 100 may also include electrical devices and circuits, including amplifiers 105 and 123, a digital converter circuit 111, a digital control circuit 101, a photodiode 107, and a control section 109. For example, the amplifiers 105 and 123 may include transimpedance and limiting amplifiers (TIA / LA). In some embodiments, the optical transceiver 100 also includes a photonic die 103 having a laser assembly. In some embodiments, the laser assembly includes one or more laser 131 lenses, a rotator for directing one or more continuous wave (CW) optical signals, and one or more laser drivers 129.

[0023] In further embodiments, the optical transceiver 100 includes an input waveguide 137 configured to receive an optical signal from a laser 131 and an optical splitter 133 configured to split the optical signal into four optical signals of approximately equal power. In various embodiments, the separated power signals are transmitted from the optical splitter 133 to the optical modulator 117 through the optical waveguide. In some embodiments, the optical splitter 133 is coupled to the input waveguide 137 and at least four output waveguides 102. In some embodiments, the optical splitter 133 includes a low-loss Y-junction power divider. In some embodiments, the input waveguide 137 includes a single polarization grating coupler (SPGC). In some embodiments, the SPGC is a one-dimensional (1D) grating coupler.

[0024] In some embodiments, the optical modulator 117 includes, for example, a Mach-Zehnder interferometer or a ring modulator and is capable of modulating a CW laser input signal. The optical modulator 117 may also include high-speed and low-speed phase modulation sections and is controlled by the control section 109. In some embodiments, at least one of the outputs of each optical modulator 117 is optically coupled to the optical output 120 via a grating coupler 115, such as an optical fiber. In some embodiments, the grating coupler 115 includes an SPGC. The other output of the optical modulator 117 may be optically coupled to a monitoring photodiode 113, which is configured to provide a feedback path from the output of the optical modulator 117 to the control section 109.

[0025] In addition, the optical transceiver 100 can also use the grating coupler 121 to receive the optical signal from the optical input 119, wherein the optical input 119 can be from the optical fiber 201 (see Figure 2) or an array of optical fibers 201. In this embodiment, the grating coupler 121 includes a polarization separation grating coupler (PSGC), which transmits the received optical signal to the photodiode 107 using two waveguides (or output waveguides) 122 and 124. In some embodiments, the optical transceiver 100 includes a plurality of grating couplers 121.

[0026] In some embodiments, the optical transceiver 100 employs a photodiode 107, which can be implemented using an epitaxial germanium (Ge) / silicon germanium (SiGe) film deposited directly on silicon (Si). In some embodiments, the photodiode 107 may include, for example, a high-speed heterojunction phototransistor, and may include Ge in the collector and base regions for absorption in the wavelength range of 1200nm to 1600nm (e.g., in the range of 1310nm to 1550nm), and may be integrated on a complementary metal oxide semiconductor (CMOS) silicon on insulator (SOI) wafer. The photodiode 107 may be configured to convert an optical signal received from the grating coupler 121 into an electrical signal, which is transmitted to a receiver (Rx) 123, which may be configured to combine data streams and de-code the received optical signal. In addition, the received optical signal, for example, may be amplified by a transimpedance amplifier 125 and then transmitted to a small form factor pluggable (SFP) interface circuit 127. In some embodiments, the optical transceiver 100 further includes a digital control circuit 101 coupled to the serial interface 135 and configured to transmit received optical data through the serial interface 135 .

[0027] like Figure 1 As shown, grating couplers 115 and 121 of optical transceiver 100 enable light to be coupled into and out of an integrated circuit including optical transceiver 100. In some embodiments, geometric parameters of grating couplers 115 and 121 can be parameterized during routing and layout of a photonic-enabled integrated circuit and optimized based on performance metrics.

[0028] Figure 2 A top view of a photonic die 200 is shown, which includes a photonic die 200 configured to receive a photon from an optical fiber 201 (or an array thereof; see Figure 3 ) receives and modulates the optical input by a grating coupler 224, and the modulated optical input is then transmitted to waveguides 228 and 238 through tapered structures 226 and 236, respectively. As shown, the optical input from the optical fiber 201 can be applied within a range of about 5° to about 15° (e.g., about 12°). In some embodiments, the photonic die 200 corresponds to a portion of the optical transceiver 100, such as Figure 1In this regard, the grating coupler 224 corresponds to the grating coupler 121, and the waveguides 228 and 238 correspond to the waveguides 122 and 124, respectively. The tapered structures 236 and 236 are symmetrically arranged to extend away from the grating coupler 224 and toward the waveguides 228 and 238, respectively.

[0029] Grating coupler 224, tapered structure 226 / 236 and waveguide 228 / 238 are arranged on (or in) semiconductor layer 206, and semiconductor layer 206 is also referred to as photonic device region. In the present embodiment, grating coupler 224 is a two-dimensional (2D) grating coupler formed by two single polarization grating couplers arranged substantially perpendicular to each other. Each single polarization grating coupler includes a group of arc-shaped grating lines, and its major axis is substantially parallel to the azimuth of optical fiber 201. In certain embodiments, the arc-shaped grating lines are all configured as elliptical. The arc-shaped grating lines of the first single polarization grating coupler are arranged along a first direction, and the arc-shaped grating lines of the second single polarization grating coupler are arranged along a second direction substantially perpendicular to the first direction.

[0030] The grating coupler 224 includes scattering elements located at the intersection of the grating lines and the 2D grating pattern. Different designs of the scattering elements are configured to reduce polarization-dependent losses and improve the efficiency of light coupling from the optical fiber 201 to the grating coupler 224. In this embodiment, the geometric parameters of the scattering elements (e.g., the shape of each scattering element, the spacing between adjacent scattering elements, the depth of such spacing, etc.) can be varied along a given direction so that the 2D grating pattern includes apodization structures. More details of the grating coupler 224 will be referred to Figure 4 The grating coupler 224 may be formed by etching the semiconductor layer 206 using a photolithography process, resulting in scattering elements arranged in a 2D grating pattern.

[0031] The photonic die 200 also includes a metal layer (or alternatively referred to as a metal reflector reflective layer or metal mirror) 218 ​​disposed below the semiconductor layer 206. For illustrative purposes, the metal layer 218 is depicted as a border region surrounding the grating coupler 224. In the present embodiment, the metal layer 218 is configured to reflect (i.e., recycle) any optical input (or optical signal) that tunnels through the semiconductor layer 206 (and the underlying dielectric layer 204), thereby improving the coupling efficiency of the grating coupler 224. For at least this reason, the metal layer 218 includes an optically reflective material. For example, the metal layer 218 may include copper (Cu), aluminum (Al), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. or a combination thereof. In some embodiments, the metal layer 218 includes a seed layer (e.g., seed layer 216).

[0032] Reference Figure 3 , which is along Figure 2 2. The photonic die 200 is a cross-sectional view of the photonic die 200 taken along line A-A' (i.e., in the A1-Z plane), the photonic die 200 includes a semiconductor substrate 212, a metal layer 218 disposed over the semiconductor substrate 212, a dielectric layer 204 disposed over the metal layer 218, and a semiconductor layer 206 disposed over the dielectric layer 204. In this regard, the metal layer 218 is embedded between the semiconductor substrate 212 and the dielectric layer 204, and extends over (e.g., overlaps) a region of the semiconductor layer 206 corresponding to at least the location of the grating coupler 224. In some embodiments, as Figure 3 As shown, the metal layer 218 extends over the entire area on which the grating coupler 224, the tapered structures 226 / 236, and the waveguides 228 / 238 are arranged.

[0033] Figure 4 A portion of the GC of the photonic die 200 (eg, a portion of the grating coupler 224) is shown, wherein the portion of the GC includes a plurality of scattering elements 310-n arranged in a 2D grating pattern 300. Referring to FIG. Figure 5 , the 2D grating pattern 300 in a plan view is defined by first curved (e.g., arc-shaped or elliptical) grating lines 304 spaced apart from each other and arranged along a first direction A1 and second arc-shaped grating lines 306 spaced apart from each other and arranged along a second direction A2, wherein the second direction A2 is substantially perpendicular to the first direction A1. The first arc-shaped grating lines 304 intersect with the second arc-shaped grating lines 306 to form an arc-shaped grid 308, wherein each scattering element 310-n is located at the intersection of each first arc-shaped grating line 304 and each second arc-shaped grating line 306, and is located in the arc-shaped grid 308, thereby forming the 2D grating pattern 300.

[0034] In some embodiments, the first arcuate grating lines 304 correspond to the grating lines of a first single polarization (or 1D) grating coupler and the second arcuate grating lines 306 correspond to the grating lines of a second single polarization grating coupler. In this regard, the first arcuate grating lines 304 are arranged substantially perpendicular to the second arcuate grating lines to form an arcuate grid 308 corresponding to a two-dimensional (2D) grating coupler (e.g., grating coupler 224).

[0035] Figure 4 The area of ​​the 2D grating pattern 300 enclosed by the dashed line is Figure 6 Shown in an enlarged view, Figure 6Various details of the scattering elements 310-n are shown. The scattering elements 310-1, 310-2, 310-3 and 310-4 are arranged along the third direction A3. Each scattering element 310-n includes a first dimension ALn, where n is a natural number greater than or equal to 1, such as AL1, AL2, AL3 and AL4, along the third direction A3 and a second dimension CLn, such as CL1, CL2, CL3 and CL4, along a fourth direction A4, wherein two adjacent scattering elements 310-n along the third direction A3 are separated by a spacing BLn, such as BL1, BL2, BL3 and BL4. The sum of the first dimension ALn and the spacing BLn is the pitch Pn, such as P1, P2. In this embodiment, the third direction A3 and the fourth direction A4 are not parallel to each other. For example, the third direction A3 and the fourth direction A4 may be substantially perpendicular to each other, such as Figure 6 In other words, the angle α between the third direction A3 and the fourth direction A4 is approximately 90°.

[0036] In the present embodiment, the second dimension CLn is greater than the first dimension ALn. In this regard, the third direction A3 is considered to be the short axis of the scattering element 310-n, and the fourth direction A4 is considered to be the long axis of the scattering element 310-n. The top surface of each scattering element 310-n is configured to have a polygonal shape having a first dimension ALn along the third direction A3 and a second dimension CLn along the fourth direction A4. In some embodiments, the scattering elements 310-n are each a polygon having four or more connected straight sides, wherein each scattering element 310-n is configured to have a polygonal shape having at least four side walls. In the present embodiment, the scattering elements 310-n are all octagons elongated along the fourth direction A4, such as Figure 6 As shown in the figure, side walls S1, S2, S3, S4, S5, S6, S7 and S8 are connected in sequence, wherein side walls S1 and S5 are substantially parallel to each other along the third direction A3 and have substantially equal lengths; side walls S2 and S8 are substantially symmetrical about the fourth direction A4 and have substantially equal lengths; side walls S3 and S7 are substantially parallel to each other along the fourth direction A4 and have substantially equal lengths. Side walls S4 and S6 are substantially symmetrical about the fourth direction A4 and have substantially equal lengths.

[0037] In the depicted embodiment, the sizes of the first dimension ALn and the spacing BLn gradually change along the first direction A1 and along the second direction A2. For example, along the first direction A1 and along the second direction A2 toward the tapered structure 226 / 236, the first dimension ALn gradually increases, while the spacing BLn gradually decreases (see Figure 2). On the contrary, the first dimension ALn gradually decreases away from the tapered structure 226 / 236 along the first direction A1 and along the second direction A2, respectively, and the pitch BLn gradually increases. Therefore, it is considered that the 2D grating pattern 300 has a trace-changing structure. In the present embodiment, such a trace-changing structure increases the mode field matching of the grating coupler 224 and the optical fiber 201, thereby improving the coupling efficiency of the grating coupler 224. In some embodiments, the second dimension CLn of the scattering element 310-n remains substantially constant along the first direction A1, the second direction A2, the third direction A3, and the fourth direction A4. In some embodiments, the pitch Pn varies along the first direction A1 and the second direction A2 in a manner similar to the first dimension ALn.

[0038] In some embodiments, the first dimension ALn and the second dimension CLn are each in the range of about 100 nm to about 1 μm. For example, the first dimension ALn and the second dimension CLn may each be in the range of about 200 nm to about 1 μm. In some embodiments, the pitch BLn ranges from about 200 nm to about 500 nm. For example, the pitch BLn may be in the range of from about 250 nm to about 500 nm. In some embodiments, the pitch Pn varies according to the wavelength of the light input (e.g., light input 119) applied to the grating coupler 224. For example, for the absorption of light at a wavelength in the range of 1310 nm to 1550 nm, the pitch Pn is less than about 1 μm. For example, for the absorption of light input with a wavelength of 1310 nm, the pitch Pn is less than about 600 nm.

[0039] Reference Figure 7 , Figure 7 It is along Figure 6 In a cross-sectional view of the 2D grating pattern 300 (e.g., in the A3-Z plane) along line BB' shown, the scattering elements 310-n are defined by recesses into the semiconductor layer 206. The recesses can have a depth DTn, such as DT1, DT2, and DT3, where n corresponds to the same number as the scattering elements 310-n. The depth DTn can range from about 70nm to about 270nm, but is less than the total thickness CT of the semiconductor layer 206, which can range from about 250nm to about 350nm. In some embodiments, the depth DTn remains substantially the same within the 2D grating pattern 300. For example, DT1~DT2~DT3…~DTn. In some embodiments, the depth DTn can vary between adjacent scattering elements 310-n. For example, referring to Figure 8 , between scattering elements 310-2 and 310-3, depth DT2 is less than depth DT3. In some embodiments, the depths of adjacent scattering elements are adjusted to have a value such as Figure 8 The stepped profile shown may increase the area that the grating coupler 224 is able to accommodate the light input 119 .

[0040] Fig. 9 The photonic die 200 of a portion of a GC (e.g., a portion of a grating coupler 224) is shown, wherein the portion of the GC includes a plurality of scattering elements 410-n arranged in a 2D grating pattern 400. Although not shown for simplicity, the 2D grating pattern 400 in the top view is also defined by two sets of arcuate grating lines arranged substantially perpendicular to each other (e.g., along a first direction A1 and a second direction A2, respectively), similar to the arcuate grating lines 308 formed as shown in FIG. Figure 5 In this regard, each scattering element 410 - n is located at each intersection of two sets of arc-shaped grating lines, thereby forming a 2D grating pattern 400 .

[0041] Various details of the exemplary scattering element 410-n are as follows: Fig.10 As shown in the enlarged view in . In some embodiments, the scattering element 410-n includes a first dimension ALn along the third direction A3, such as AL1, AL2, AL3 and AL4, and a second dimension CLn along the fourth direction A4, such as CL1, CL2, CL3 and CL4, wherein two adjacent scattering elements 410-n are spaced apart by a first spacing BLn along the third direction A3, such as BL1, BL2, BL3 and BL4, and are spaced apart by a second spacing DLn along the fourth direction A4, such as DL1, DL2, DL3 and DL4. The sum of the first dimension ALn and the first spacing BLn is a first pitch Pn along the third direction A3, and the sum of the second dimension CLn and the second spacing DLn is a second pitch En along the fourth direction A4, such as E1, E2. In this embodiment, the third direction A3 and the fourth direction A4 are not parallel to each other and may be formed as shown in the figure. Fig.10 In other words, the angle α is greater than about 90° and less than about 180°.

[0042] In some embodiments, the first dimension ALn and the second dimension CLn are different in size. Fig.10As shown, the second dimension CLn is greater than the first dimension ALn. In this regard, the third direction A3 is considered to be the short axis of the scattering element 410-n, and the fourth direction A4 is considered to be the long axis of the scattering element 410-n. In some embodiments, the lengths of the first dimension ALn and the second dimension CLn may be substantially the same. In some embodiments, the scattering elements 410-n are each polygons having four or more connected straight sides. In this embodiment, each scattering element 410-n has four side walls connected into a rhombus, wherein two adjacent side walls are not parallel and have unequal lengths, and two non-adjacent side walls are parallel and have equal lengths. As shown, the side walls T1, T2, T3 and T4 are connected in this order, wherein the side walls T1 and T3 are substantially parallel to each other and have substantially equal lengths, and the side walls T2 and T4 are substantially parallel to each other and have substantially equal lengths. The scattering element 410-n may also be defined by a depth DTn, which is similar to Figure 7 and Figure 8 In the present embodiment, the diamond shape of each scattering element 410-n provides improvements in reducing coupling loss and polarization crosstalk of the grating coupler 224 as compared to scattering elements with a circular (eg, cylindrical) shape.

[0043] Similar to the scattering elements 310-n, the first dimension ALn and the first spacing BLn of the scattering elements 410-n gradually change across the arc-shaped grid along each of the first direction A1 and the second direction A2. For example, along the first direction A1 and along the second direction A2 toward the tapered structure 226 / 236 (see Figure 2 ), the first dimension ALn gradually increases, and the first spacing BLn gradually decreases. On the contrary, along the first direction A1 and along the second direction A2 away from the tapered structure 226 / 236, the first dimension ALn gradually decreases, and the first spacing BLn gradually increases. At this point, the 2D grating pattern 400 is also considered to have a trace structure configured to improve the coupling efficiency of the grating coupler 224 provided herein. In some embodiments, the second dimension CLn and the second spacing DLn of the scattering element 410-n each remain substantially constant along the first direction A1, the second direction A2, the third direction A3, and the fourth direction A4. In some embodiments, the pitch Pn varies along the first direction A1 and the second direction A2 in a manner similar to the first dimension ALn.

[0044] Similar to the size of the scattering element 310-n, the first dimension ALn and the second dimension CLn of the scattering element 410-n are each in the range of about 100nm to about 1μm. For example, the first dimension ALn and the second dimension CLn can each be in the range of about 200nm to about 1μm. In some embodiments, the first spacing BLn and the second spacing are each in the range of about 10nm to about 500nm. In some embodiments, the first pitch Pn and the second pitch En each vary according to the wavelength of the light input (e.g., the light input 119) applied to the grating coupler 224. For example, for absorption of light at wavelengths in the range of 1310nm to 1550nm, the first pitch Pn and the second pitch En are each less than about 1000nm (e.g., less than 600nm for absorption of light input having a wavelength of 1310nm).

[0045] Fig.11 A portion of the GC of the photonic die 200 (e.g., a portion of the grating coupler 224) is shown, wherein the portion of the GC includes a plurality of scattering elements 510-n arranged in a 2D grating pattern 500. Although not shown for simplicity of illustration, the 2D grating pattern 500 in the top view is also defined by two groups of arc-shaped grating lines arranged substantially perpendicular to each other (e.g., along the first direction A1 and the second direction A2, respectively), similar to the first arc-shaped grating lines 304 and the second arc-shaped grating lines 306, as shown in FIG. Figure 5 As shown, an arcuate grid 308 is formed. At this point, each scattering element 510-n is located at the intersection of two sets of arcuate grating lines, thereby forming a 2D grating pattern 500.

[0046] Various details of the exemplary scattering element 510-n are as follows: Fig.12. Similar to the scattering element 410-n, the scattering element 510-n includes a first dimension ALn, such as AL1, AL2, AL3, and AL4, along the third direction A3, and a second dimension CLn, such as CL1, CL2, CL3, and CL4, along the fourth direction A4, wherein two adjacent scattering elements 410-n are spaced apart by a first spacing BLn, such as BL1, BL2, BL3, and BL4, along the third direction A3, and are spaced apart by a second spacing DLn, such as DL1, DL2, DL3, and DL4, along the fourth direction A4. The sum of the first dimension ALn and the first spacing BLn is the first spacing Pn along the third direction A3, and the sum of the second dimension CLn and the second spacing DLn is the second spacing En along the fourth direction A4. The changes of the first dimension ALn, the first spacing BLn, the second dimension CLn, and the second spacing DLn of the scattering element 510-n along the first direction A1 and the second direction A2 of the scattering element 510-n are similar to those of the scattering element 410-n, and therefore are not repeated for the purpose of brevity. Therefore, the 2D grating pattern 500 is also considered to have an apodization structure configured to improve the coupling efficiency of the grating coupler 224 provided herein.

[0047] In some embodiments, unlike the scattering element 410-n, the third direction A3 and the fourth direction A4 form an acute angle, such as Fig.12 In other words, the angle α is less than about 90°. Fig.13 , which depicts the Fig.12 Similarly, for the scattering element 510-n, the third direction A3 and the fourth direction A4 form an obtuse angle, wherein the angle α is greater than about 90° and less than about 180°. In this regard, when the scattering element 510-n is positioned on the arc-shaped grid to form the 2D grating pattern 500, the scattering element 510-n may be slightly rotated.

[0048] In addition, similar to the scattering element 410-n, the first size ALn and the second size CLn of the scattering element 510-n are different. Fig.12 As shown, the second dimension CLn is greater than the first dimension ALn. In this regard, the third direction A3 is considered to be the short axis of the scattering element 410-n, and the fourth direction A4 is considered to be the long axis of the scattering element 410-n. In some embodiments, the lengths of the first dimension ALn and the second dimension CLn can be substantially the same. The scattering element 510-n can also be defined by a depth DTn, which is similar to Figure 7 or Figure 8 Similar to that described with respect to scattering elements 310 - n.

[0049] However, unlike scattering element 410-n, scattering element 510-n includes four sidewalls connected to form a modified diamond shape, wherein each sidewall is not a completely straight sidewall, but includes a portion having an elliptical curve 520 that is connected to two substantially straight portions on each side. As shown, sidewalls U1, U2, U3, and U4 are connected in this order and each includes an elliptical curve 520, wherein the straight portions of sidewalls U1 and U3 are substantially parallel to each other and have substantially equal lengths, and the straight portions U4 and U4 of sidewall U2 are substantially parallel to each other and have substantially equal lengths. In some embodiments, the elliptical curve 520 in each sidewall U1-U4 of scattering element 510-n further reduces the coupling loss and polarization crosstalk of grating coupler 224 compared to those without elliptical curve 520 (e.g., scattering element 410-n).

[0050] Fig.14 1 is a flowchart of a method 600 for forming a semiconductor structure 700 according to one or more embodiments of the present invention. The semiconductor structure 700 may include (or provide) a photonic grain 200. It should be noted that the method 600 is only an example and is not intended to limit the present invention. Therefore, it should be understood that the method 600 may be used in the following embodiments. Fig.14 Additional operations are provided before, during, and after the method 600, and some other operations may only be briefly described here. In some embodiments, as Figure 15-Figure 29 As shown, the operations of method 600 may be associated with a cross-sectional view of semiconductor structure 700 at various stages of fabrication, which will be discussed in further detail below. For the purpose of brevity, method 600 is described with reference to forming tapered structure 226 and waveguide 228, thereby omitting a description of forming their symmetrical counterparts, tapered structure 236 and waveguide 238, respectively.

[0051] Reference Fig.15, the method 600 at operation 602 provides a semiconductor wafer W including a semiconductor substrate 202, a dielectric layer 204 disposed on the semiconductor substrate 202, and a semiconductor layer 206 disposed on the dielectric layer 204. The semiconductor wafer W may be a silicon-on-insulator (SOI) wafer, which includes a silicon substrate (e.g., semiconductor substrate 202), a silicon dioxide (SiO2) layer (e.g., dielectric layer 204) disposed on the silicon substrate, and a silicon layer (e.g., semiconductor layer 206) disposed on the silicon dioxide layer, wherein the silicon layer may be a doped layer. The dielectric layer 204 may completely cover the top surface (or front side) of the semiconductor substrate 202. The semiconductor layer 206 may completely cover the top surface of the dielectric layer 204. The thickness of the semiconductor substrate 202 may be in the range of about 50 μm to about 760 μm, the thickness of the dielectric layer 204 may be in the range of about 0.5 μm to about 5 μm, and the thickness of the semiconductor layer 206 may be in the range of about 100 nm to about 5 μm. For example, semiconductor substrate 202 may be approximately 100 μm thick, dielectric layer 204 may be approximately 2 μm thick, and semiconductor layer 206 may be approximately 270 nm thick. Semiconductor wafer W may include other types of semiconductor materials and dielectric materials arranged in the configurations described herein.

[0052] refer to Fig.16 and Fig.17 , the method 600 patterns the semiconductor layer 206 at operation 604 to define a photonic device region of the semiconductor structure 700. Fig.16 , a patterned photoresist layer 250 is formed over the semiconductor wafer W to cover a portion of the semiconductor layer 206. The semiconductor layer 206 may include a photonic device region covered by the patterned photoresist layer 250. In some embodiments, the semiconductor layer 206 also includes an electronic device region for forming a semiconductor device (not shown), such as a metal oxide semiconductor field effect transistor (MOSFET), a capacitor, an inductor, a resistor, etc. or a combination thereof. The patterned photoresist layer 250 may be formed on the semiconductor layer 206 by a photolithography process, which may include spin coating of a photoresist material, baking of the photoresist material, exposure of the baked photoresist material, and development of the exposed photoresist material.

[0053] Reference Fig.17 , a patterning process is performed to remove portions of the semiconductor layer 206 that are not covered by the patterned photoresist layer 250, so that the semiconductor layer 206 is formed above the dielectric layer 204. The patterning process of the semiconductor layer 206 may be an etching process for removing portions of the semiconductor layer 206 until portions of the dielectric layer 204 are exposed. After the patterning process is performed, the patterned photoresist layer 250 is removed from the semiconductor layer 206 by any suitable process (e.g., plasma ashing, resist stripping, etc.).

[0054] refer to Figure 18-Figure 20 The method 600 further patterns the semiconductor layer 206 at operation 606 to form a grating coupler 224, a tapered structure 226, and a waveguide 228. Fig.18 and Fig.19 , a patterned photoresist layer 252 is formed to cover the semiconductor layer 206 and the dielectric layer 204. The patterned photoresist layer 252 may be formed on the semiconductor layer 206 and the dielectric layer 204 by the photolithography process provided herein.

[0055] In this embodiment, the patterned photoresist layer 252 includes a slit pattern corresponding to the 2D grating pattern 300 / 400 / 500 of the grating coupler 224. In one example, the slit pattern defined in the patterned photoresist layer 252 may correspond to the arrangement of the scattering elements 310-n in the 2D grating pattern 300, such as Figure 4 In another example, the slit pattern defined in the patterned photoresist layer 252 may correspond to the arrangement of the scattering elements 410 - n in the 2D grating pattern 400 , as shown in FIG. Fig. 9 In yet another example, the slit pattern defined in the patterned photoresist layer 252 may correspond to the arrangement of the scattering elements 510 - n in the 2D grating pattern 500 , as shown in FIG. Fig.11 In addition, the shape, position and / or size of the scattering elements 310 - n / 410 - n / 510 - n correspond to the shape, position and / or size of the slits formed in the semiconductor layer 206 by a subsequent patterning process.

[0056] Reference Fig. 20 , a patterning process is performed to remove the portion of the semiconductor layer 206 not covered by the patterned photoresist layer 252, so that the semiconductor layer 206 including the grating coupler 224, the tapered structure 226 and the waveguide 228 is formed above the top surface of the dielectric layer 204. The patterning process may include an etching process for removing the portion of the semiconductor layer 206 not covered by the patterned photoresist layer 252. The etching depth of the removal process may be less than the thickness of the semiconductor layer 206. In the present embodiment, the etching depth of the patterning process may be about 70 nm to about 270 nm, which corresponds to the depth DTn defined herein (see Figure 7 ). In some embodiments, the patterning process may include multiple etching processes.

[0057] After the patterning process, the semiconductor layer 206 includes a grating coupler 224 connected to a tapered structure 226, which is further connected to a waveguide 228, all of which are formed over the portion of the semiconductor layer 206 that overlaps the dielectric layer 204. Fig.19 As shown, in each semiconductor layer 206, the grating coupler 224 is formed by a slit pattern corresponding to the 2D grating pattern 300 / 400 / 500. Fig. 20After performing the patterning process, the patterned photoresist layer 252 is removed from the semiconductor layer 206 and the dielectric layer 204 by any suitable process provided herein.

[0058] Reference Fig.21 , a patterned photoresist layer 254 may then be formed by the photolithography process provided herein to cover the semiconductor layer 206 and portions of the dielectric layer 204. In some embodiments, the semiconductor layer 206 is completely covered by the patterned photoresist layer 254.

[0059] Reference Fig. 22 , a patterning process is performed to remove portions of the dielectric layer 204 that are not covered by the patterned photoresist layer 254, resulting in the dielectric layer 204 having a predetermined pattern over the semiconductor substrate 202. The patterning process can be an etching process for removing portions of the dielectric layer 204 until portions of the semiconductor substrate 202 are exposed. After the patterning process is performed, the patterned photoresist layer 254 is removed from the semiconductor layer 206 and the dielectric layer 204 by any suitable process provided herein. In some embodiments, the patterning process for removing portions or the dielectric layer 204 is omitted.

[0060] refer to Fig.23 , method 600 bonds semiconductor structure 700 to carrier 262 at operation 608 using adhesive layer 260 formed over carrier 262. Carrier 262 may include a glass carrier, and adhesive layer 260 may be a light-to-heat conversion (or light-transfer heat conversion, or LTHC) layer adhered to a surface of carrier 262. The resulting semiconductor wafer W1 includes semiconductor substrate 202, dielectric layer 204, and semiconductor layer 206, which are temporarily bonded to carrier 262 via adhesive layer 260. After semiconductor wafer W1 is temporarily bonded to carrier 262, semiconductor layer 206 contacts adhesive layer 260. In other words, carrier 262 and semiconductor wafer W1 are located at opposite sidewalls of adhesive layer 260.

[0061] Reference Fig.24 , the method 600 removes the semiconductor substrate 202 from the back side (or bottom surface) of the dielectric layer 204 at operation 610, so that the front side (or top surface) of the semiconductor structure 700 is temporarily supported by the carrier 262, and the back side of the semiconductor structure 700 is temporarily supported by the carrier 262. The dielectric layer 204 is exposed. In some embodiments, the semiconductor substrate 202 is removed from the dielectric layer 204 by a laser lift-off process, a backside etching process, a grinding process, etc. The grinding process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, etc. or a combination thereof.

[0062] Reference Fig.25, the method 600 patterns the semiconductor substrate 212 at operation 612 to form a trench 214. In some embodiments, the semiconductor substrate 212 is a wafer of a silicon substrate. A patterned photoresist layer 264 can then be formed by a photolithography process provided herein to cover the front side (or top surface) of the semiconductor substrate 212. A patterning process is performed to remove portions of the semiconductor substrate 212 that are not covered by the patterned photoresist layer 264, thereby forming a trench 214 in the semiconductor substrate 212. The patterning process of the semiconductor substrate 212 can be an etching process for removing a portion or the semiconductor substrate 212. After performing the patterning process, the patterned photoresist layer 264 is removed from the semiconductor substrate 212 using a suitable process provided herein.

[0063] refer to Fig.26 , method 600 forms a metal layer 218 at the trench 214 at operation 614. In some embodiments, a seed layer 216 can be formed in the trench 214 before forming the metal layer 218. The seed layer 216 may include a titanium / copper (Ti / Cu) layer formed by a sputtering process. The seed layer 216 may be sputtered (e.g., by a physical vapor deposition or PVD process) to completely cover the front side of the semiconductor substrate 212, thereby filling the trench 214. The metal layer 218 may include copper (Cu) formed by any suitable process, such as PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, etc. or a combination thereof. In some examples, the thickness of the seed layer 216 ranges from about 10 nm to about 500 nm, the thickness of the metal layer 218 ranges from about 10 nm to about 10 μm, and the depth of the trench 214 ranges from about 100 nm to about 100 μm. Referring to Fig. 27 A polishing (or planarization) process such as a CMP process may be performed to remove portions of the seed layer 216 and the metal layer 218 until the top surface of the semiconductor substrate 212 is exposed. In some embodiments, the seed layer 216 is omitted from the semiconductor structure 700.

[0064] refer to Fig.28 , the method 600 bonds the front side of the semiconductor substrate 212 (i.e., the metal layer 218) to the back side of the dielectric layer 204 at operation 616. In some embodiments, the front side of the semiconductor substrate 212 (the first substrate) is bonded to the back side of the dielectric layer 204 (the second substrate) by a wafer-to-wafer fusion bonding process, a hybrid bonding process, etc. The bonding temperature of the wafer-to-wafer fusion bonding process may be in the range of about 200° C. to about 600° C.

[0065] Reference Fig.29, method 600 performs a separation process at operation 618 to remove carrier 262 and adhesive layer 260 from semiconductor structure 700. Carrier 262 and adhesive layer 260 may be released from semiconductor layer 206 by irradiating semiconductor structure 700 with a laser, which heats and subsequently releases adhesive layer 260 and carrier 262 from semiconductor layer 206.

[0066] The method 600 may perform additional operations at operation 620. For example, the semiconductor structure 700 may be separated along the scribe lines SL to obtain the photonic crystal 200, which includes the semiconductor substrate 212, the dielectric layer 204 on the semiconductor substrate 212, and the semiconductor layer 206 on the dielectric layer 204, as shown in FIG. Figure 2 and Figure 3 As shown. The semiconductor substrate 212 also includes a metal layer 218 above the seed layer 216. The dielectric layer 204 extends throughout the semiconductor layer 206 and covers at least a portion of the metal layer 218. The semiconductor layer 206 includes a grating coupler 224 connected (or coupled) to a tapered structure 226, which is further connected (or coupled) to a waveguide 228. In some embodiments, the metal layer 218 is partially exposed by the dielectric layer 204 near the edge of the photonic die 200. The grating coupler 224 includes scattering elements 310-n / 410-n / 510-n arranged in the 2D grating pattern 300 / 400 / 500, respectively. The photonic die 200 can be further packaged, integrated with other die (e.g., electrical die, photonic die, etc.), or otherwise processed to form a semiconductor device.

[0067] In one aspect, the utility model provides a semiconductor structure, which includes a substrate and a metal layer disposed in the substrate. The semiconductor structure includes a dielectric layer disposed above the metal layer. The semiconductor structure also includes a semiconductor layer disposed above the dielectric layer, wherein the metal layer extends through the semiconductor layer. The semiconductor layer includes a two-dimensional grating coupler, the two-dimensional grating coupler includes a plurality of scattering elements disposed in the semiconductor layer and a pair of conical structures extending laterally from the two-dimensional grating coupler.

[0068] In another aspect, the utility model provides a semiconductor structure, comprising a first semiconductor layer and a metal layer embedded in the first semiconductor layer. The semiconductor structure comprises a dielectric layer disposed above the metal layer. The semiconductor structure further comprises a second semiconductor layer disposed above the dielectric layer and overlapping the metal layer. The second semiconductor layer comprises a grating coupler having a plurality of scattering elements arranged in an apodization pattern, a pair of tapered structures extending from the grating coupler, and a pair of waveguides, wherein each tapered structure couples the grating coupler to a corresponding waveguide.

[0069] In yet another aspect, the utility model provides a method, the method comprising providing a first semiconductor layer above a dielectric layer, the dielectric layer having a bottom surface. The method comprises forming a grating coupler in the first semiconductor layer, the grating coupler comprising a plurality of scattering elements arranged in an apodization pattern. The method comprises providing a second semiconductor layer having a first top surface. The method comprises forming a metal layer in the second semiconductor layer, wherein the metal layer comprises a second top surface coplanar with the first top surface. The method further comprises bonding the bottom surface to the second top surface.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A metal layer is disposed in the substrate; A dielectric layer is disposed on the metal layer; as well as The semiconductor layer is disposed on the dielectric layer, the metal layer extends across the semiconductor layer, and the semiconductor layer comprises: A two-dimensional grating coupler comprising a plurality of scattering elements disposed in the semiconductor layer; as well as A pair of tapered structures extend laterally from the two-dimensional grating coupler.

2. The semiconductor structure according to claim 1, characterized in that: The scattering elements are arranged in an apodization pattern, the apodization pattern comprising first arcuate grating lines extending along a first direction and second arcuate grating lines extending along a second direction in a top view, the first direction and the second direction being perpendicular to each other, wherein a top surface of each scattering element is configured to have a polygonal shape having a first dimension along a third direction and a second dimension along a fourth direction, each of the third direction and the fourth direction being different from the first direction and the second direction, and wherein the first dimension gradually changes along each of the first direction and the second direction.

3. The semiconductor structure according to claim 2, characterized in that: The first dimension gradually increases along each of the first direction and the second direction toward each of the tapered structures.

4. The semiconductor structure according to claim 2, characterized in that: The spacing between adjacent scattering elements gradually decreases toward each of the tapered structures along each of the first direction and the second direction.

5. The semiconductor structure according to claim 2, characterized in that: The second dimension remains constant along each of the first direction and the second direction.

6. The semiconductor structure according to claim 1, characterized in that The top surface of each scattering element is configured in a polygonal shape having at least four side walls, wherein the at least four side walls each include a straight line portion and an elliptical portion.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor layer also includes a pair of waveguides, each waveguide extending laterally from a corresponding tapered structure.

8. A semiconductor structure, characterized in that: include: a first semiconductor layer; A metal layer is embedded in the first semiconductor layer; A dielectric layer is disposed on the metal layer; as well as A second semiconductor layer is disposed above the dielectric layer and overlaps the metal layer, the second semiconductor layer comprising: a grating coupler having a plurality of scattering elements arranged in an apodization pattern; a pair of tapered structures extending from the grating coupler; and A pair of waveguides, wherein each tapered structure couples the grating coupler to a corresponding waveguide.

9. The semiconductor structure according to claim 8, characterized in that: The apodization pattern comprises first arcuate grating lines arranged along a first direction and second arcuate grating lines arranged along a second direction perpendicular to the first direction, and wherein each scattering element is located at the intersection of each of the first arcuate grating lines and each of the second arcuate grating lines, wherein the spacing between two adjacent scattering elements varies along each of the first direction and the second direction.

10. The semiconductor structure according to claim 8, characterized in that The top surface of each scattering element is configured in a diamond shape, wherein each sidewall of the diamond shape includes a curved portion.

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