Level shifter, source driver, display panel and display device

Abstract

The utility model discloses a level shifter, a source driver, a display panel and a display device, which comprise an output node, an input unit connected between the output node and a first driving voltage end and used for controlling the corresponding output node in a first output node and a second output node to be conducted with the first driving voltage end, and an output unit connected between the first output node and the second output node and used for controlling the corresponding output node to be conducted with the second driving voltage end. The input unit is connected between the output node and a second driving voltage end and used for controlling the corresponding output node to be connected with the second driving voltage end, a first output signal is output at the first output node, a second output signal is output at the second output node, and the control unit is used for disconnecting the input unit from the output node in a pre-operation stage. A current path between the output node and the second driving voltage end is provided in at least part of the time of the pre-operation stages, so that the output node is pre-charged, and each pre-operation stage corresponds to the level flipping action of the input signal. And the output node is pre-charged, so that the level converter can be smoothly overturned.

Description

Technical Field

[0001] The utility model relates to the technical field of display driving, in particular to a level converter, a source driver, a display panel and a display device. Background Art

[0002] With the rapid development of display technology, a large number of driving circuits are needed to improve the color depth, resolution and other performance of display devices. On the one hand, in order to make the display device thinner and lighter, it is necessary to reduce the size of the driving circuit in the display device. On the other hand, in order to reduce the power consumption of the display device, it is necessary to set the driving voltage to a lower level. However, the scanning signal line driving circuit and the data signal line driving circuit in the display device require a higher operating voltage. Due to the reduction of the driving voltage, the low voltage signal input by the peripheral circuit cannot make the scanning signal line driving circuit and the data signal line driving circuit in the display device work normally. Therefore, it is necessary to use a level shifter to raise the low voltage signal input by the peripheral circuit to the high operating voltage required by the driving circuit.

[0003] When the display driver drives the display panel with a single driver chip, at high resolution (such as 3552RGBx3840), the source driver needs to output 10656 (3552*3) grayscale voltages. At this time, the required level converters (LevelShift, LSH) will also reach 106560 (each grayscale voltage is 10 bits). In terms of design, when the 106560 level converters flip at the same time, the instantaneous current is too large, causing the level converters to fail to flip smoothly, resulting in display abnormalities.

[0004] like Figure 1 As shown, in the level converter in the prior art, the output voltage provided by the output nodes Q and QB is controlled by the switch tube M1, the switch tube M2, the switch tube M3 and the switch tube M4, and the control signals VIP and VIN received by the control ends of the switch tubes M1 and M2 are inversely proportional. When the control signal VIP is in a valid state, the switch tube M1 is turned on and the switch tube M2 is turned off. At this time, due to the simultaneous flipping of multiple level converters, the instantaneous current flowing through the switch tube M1 may be too large, so that the output node QB voltage cannot be pulled down by the ground terminal GND. When the control signal VIN is in a valid state, the switch tube M2 is turned on and the switch tube M1 is turned off. At this time, due to the simultaneous flipping of multiple level converters, the instantaneous current flowing through the switch tube M2 may be too large, so that the output node Q voltage cannot be pulled down by the ground terminal GND, so that the level converter cannot be flipped, thereby affecting the display effect. Utility Model Content

[0005] In view of the above problems, an object of the present invention is to provide a display driving technology field, and in particular to a level converter, a source driver and a display device, so that the level converter can be effectively flipped.

[0006] According to one aspect of the utility model, a level converter is provided, which includes: at least one output node, and an input unit connected between the at least one output node and a first driving voltage terminal, used to control the first output node, the corresponding output node in the second output node and the first driving voltage terminal to be turned on according to an input signal, the output unit connected between the at least one output node and the second driving voltage terminal, used to control the corresponding output node to be turned on according to the potential of the first output node and the second output node, output a first output signal at the first output node, and output a second output signal at the second output node, a control unit connected to the at least one output node, used to disconnect the input unit from the at least one output node in a pre-operation stage, and provide a current path between the at least one output node and the second driving voltage terminal during at least part of the pre-operation stage, so as to pre-charge the at least one output node, and each of the pre-operation stages corresponds to a level flipping action of the input signal.

[0007] Optionally, each of the pre-operation stages starts before the level flipping action of the input signal and ends before the level flipping action of the input signal or between the level flipping action and the next level flipping action of the input signal, and the time interval between two adjacent pre-operation stages is greater than the duration of each of the pre-operation stages.

[0008] Optionally, the control unit includes: a first pre-charging control unit, connected between the at least one output node and the input unit, and used to control the input unit to be disconnected from the at least one output node according to a first pre-charging control signal; a second pre-charging control unit, connected in parallel with the output unit between the at least one output node and the second driving voltage terminal, and used to control the conduction of the connection between the at least one output node and the second driving voltage terminal according to a second pre-charging control signal, wherein the first pre-charging control signal is valid in the pre-operation stage, and the second pre-charging control signal is valid for at least part of the time in the pre-operation stage.

[0009] Optionally, the input unit includes a first transistor and a second transistor, the first transistor and the second transistor are connected between a first driving voltage terminal and the at least one output node, the control terminal of the first transistor receives a first input signal, and the first conduction terminal is connected to the first driving voltage terminal to receive the first driving voltage; the control terminal of the second transistor receives a second input signal, and the first conduction terminal is connected to the first driving voltage terminal to receive the first driving voltage, wherein the first input signal is inverted with the second input signal.

[0010] Optionally, the output unit includes a third transistor and a fourth transistor, the third transistor is connected between the second driving voltage terminal and the second output node, and the control terminal of the third transistor is connected to the first output node; the fourth transistor is connected between the second driving voltage terminal and the first output node, and the control terminal of the fourth transistor is connected to the second output node.

[0011] Optionally, the first pre-charging control unit includes a fifth transistor and a sixth transistor, the fifth transistor is connected between the first transistor and the second output node, and the control end receives the first pre-charging control signal; the sixth transistor is connected between the second transistor and the first output node, and the control end receives the first pre-charging control signal.

[0012] Optionally, the second pre-charging control unit includes a seventh transistor and an eighth transistor, the seventh transistor is connected in parallel with the third transistor and the fourth transistor between the second driving voltage terminal and the second output node, and the eighth transistor is connected in parallel with the third transistor and the fourth transistor between the second driving voltage terminal and the first output node, wherein the control terminals of the seventh transistor and the eighth transistor respectively receive the second pre-charging control signal.

[0013] Optionally, it also includes: a first bias unit, connected between the second driving voltage terminal and the output unit, and receiving a first bias voltage, for controlling the voltage drop between the second driving voltage terminal and the output unit according to the first bias voltage; a second bias unit, connected between the at least one output node and the input unit, and receiving a second bias voltage, for controlling the voltage drop between the at least one output node and the input unit according to the second bias voltage.

[0014] Optionally, the first bias unit includes a ninth transistor and a tenth transistor, the ninth transistor is connected between the second driving voltage terminal and the third transistor, and the control terminal receives the first bias voltage; the tenth transistor is connected between the second driving voltage terminal and the fourth transistor, and the control terminal receives the first bias voltage.

[0015] The second bias unit includes an eleventh transistor and a second transistor, the eleventh transistor is connected between the first transistor and the second output node, and the control end receives a second bias voltage; the twelfth transistor is connected between the second transistor and the first output node, and the control end receives the second bias voltage.

[0016] Optionally, the first transistor and the second transistor are NPN transistors, and the third transistor and the fourth transistor are PNP transistors.

[0017] According to another aspect of the present invention, a source driver is provided, comprising any one of the level converters described above.

[0018] According to another aspect of the utility model, a display panel is provided, which includes: a pixel array; a timing controller for providing a timing signal and a first pre-charge control signal and a second pre-charge control signal; the above-mentioned source driver is connected to the timing controller and the pixel array, and inputs a source drive signal to the pixel array according to the control of the timing controller.

[0019] Optionally, the display panel is any one of an OLED display panel, an LCD display panel, and a micrOLED display panel.

[0020] According to another aspect of the present invention, a display device is provided, comprising the above-mentioned display panel.

[0021] The level converter provided in the present application turns off the connection between the output node and the second driving voltage terminal GND in advance and precharges the output node, so that the level converter can be flipped smoothly.

[0022] In a preferred embodiment, by setting a bias unit and reasonably setting the first bias voltage and the second bias voltage, the voltage output from the first bias unit and the second bias unit can be smaller than the breakdown voltage of the transistors in the input unit and the output unit, thereby achieving circuit protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 A circuit diagram of a level converter according to the prior art is shown.

[0025] Figure 2 A circuit diagram of a level converter according to an embodiment of the utility model is shown.

[0026] Figure 3 The figure shows a signal timing diagram of a level converter according to an embodiment of the present utility model.

[0027] Figure 4 A schematic diagram showing voltages at each node or current flowing through the level converter of the present application and the prior art is shown.

[0028] Figure 5 A schematic diagram of a display device according to an embodiment of the utility model is shown. DETAILED DESCRIPTION

[0029] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0030] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0031] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0032] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0033] Figure 2 A circuit diagram of a level converter according to an embodiment of the utility model is shown.

[0034] like Figure 2 As shown, the level converter of the embodiment of the present utility model includes an input unit 10, an output unit 20, and a control unit.

[0035] The input unit 10 is connected between the first output node Q, the second output node QB and the first driving voltage terminal, and is used to control the corresponding output node among the first output node Q and the second output node QB to be conductive with the first driving voltage terminal GND according to the input signal.

[0036] The input unit 10 includes a first transistor M1 and a second transistor M2. The control terminal of the first transistor M1 receives a first input signal VIP, and the first conduction terminal is connected to the first driving voltage terminal GND to receive the first driving voltage; the control terminal of the second transistor M2 receives a second input signal VIN, and the first conduction terminal is connected to the first driving voltage terminal GND to receive the first driving voltage. The second input signal VIN may be inverted with the first input signal VIP.

[0037] In one embodiment, the first driving voltage may be a ground voltage, for example, the first driving voltage is 0V.

[0038] The output unit 20 is connected between the first output node Q, the second output node QB and the second driving voltage terminal AVDD, and is used to control the corresponding output node to be connected to the second driving voltage terminal AVDD according to the potential of the first output node Q and the second output node QB, thereby outputting the first output signal through the first output node Q and the second output signal through the second output node QB. The second driving voltage is higher than the first driving voltage.

[0039] The output unit 20 includes a third transistor M3 and a fourth transistor M4. The third transistor M3 is connected between the second driving voltage terminal AVDD and the second output node QB, the first conduction terminal of the third transistor M3 is connected to the second output node QB to output the second output signal at the second output node QB, and the control terminal is connected to the first output node Q. The fourth transistor M4 is connected between the second driving voltage terminal AVDD and the first output node Q, the first conduction terminal of the fourth transistor M4 is connected to the first output node Q to output the first output signal at the first output node Q, and the control terminal is connected to the second output node QB.

[0040] In one embodiment, the first transistor M1 and the second transistor M2 are NPN transistors, and the third transistor M3 and the fourth transistor M4 are PNP transistors.

[0041] The conventional working principle of the circuit is that when the first input signal VIP is at a high level (e.g., 1.8V), the first transistor M1 is turned on, and since the second input signal VIN is inverted with the first input signal VIP, the second input signal VIN is at a low level, the second transistor M2 is turned off, and the potential of the second output node QB is the first driving voltage (low potential). The potential of the control terminal of the fourth transistor M4 is pulled down, thereby making the second driving voltage terminal AVDD conductive with the first output node Q, and outputting the first output signal driven by the second driving voltage terminal AVDD at the first output node Q, the first output signal is a high voltage first output signal converted by the level converter, and the second output node QB outputs a low voltage second output signal inverted with the first output node Q.

[0042] When the first input signal VIP is at a low level, the first transistor M1 is turned off. Since the second input signal VIN is in phase opposition to the first input signal VIP, the second input signal VIN is at a low level, the second transistor M2 is turned on, and the potential of the first output node Q is the first driving voltage (low potential). The potential of the control terminal of the third transistor M3 is pulled down, thereby causing the second driving voltage terminal AVDD to be turned on with the second output node QB, and the second output node QB outputs a second output signal driven by the second driving voltage terminal AVDD, the second output signal being a high voltage second output signal converted by the level converter, and the first output node Q outputs a low voltage first output signal in phase opposition to the second output node QB.

[0043] In this process, when the first input signal VIP is flipped to a high level, the first transistor M1 is turned on and the second transistor M2 is turned off. At this time, due to the fact that multiple level converters are flipped at the same time, the instantaneous current flowing through the switch tube M1 is too large, so that the voltage of the second output node QB cannot be pulled down by the ground terminal GND. When the second input signal VIN is flipped to a high level, the second transistor M2 is turned on and the first transistor M1 is turned off. At this time, due to the fact that multiple level converters are flipped at the same time, the instantaneous current flowing through the second transistor M2 is too large, so that the voltage of the output node Q cannot be pulled down by the ground terminal GND, so that the level converter cannot be flipped, thereby affecting the display effect.

[0044] Based on this, the level converter provided in the present application also includes a control unit, which is connected to at least one output node, and is used to disconnect the input unit 10 from the at least one output node in the pre-operation stage, and provide a current path between the at least one output node and the second driving voltage terminal AVDD during at least part of the pre-operation stage to facilitate pre-charging of the at least one output node. Each pre-operation stage corresponds to a level flipping action of the input signal.

[0045] The control unit includes: a first pre-charge control unit 30, connected between at least one output node and the input unit 10, and used to control the input unit 10 to be disconnected from at least one output node according to a first pre-charge control signal LSH_EN; a second pre-charge control unit 40, connected in parallel with the output unit 20 between at least one output node and the second driving voltage terminal AVDD, and used to control the conduction of the connection between at least one output node and the second driving voltage terminal AVDD according to a second pre-charge control signal LSH_PCH, wherein the first pre-charge control signal LSH_EN is valid in the pre-operation stage, and the second pre-charge control signal LSH_PCH is valid for at least part of the time in the pre-operation stage.

[0046] Specifically, the first pre-charging control unit 30 is connected between the first output node Q, the second output node QB and the input unit 10, and is used to control the conduction and disconnection of the first output node Q, the second output node QB and the input unit 10 according to the first pre-charging control signal LSH_EN.

[0047] The second pre-charging control unit 40 is connected between the first output node Q, the second output node QB and the second driving voltage terminal AVDD, and is used to pre-charge the first output node Q and the second output node QB according to a second pre-charging control signal LSH_PCH.

[0048] The first pre-charge control unit 30 includes a fifth transistor M5 and a sixth transistor M6, wherein the fifth transistor M5 is connected between the first transistor M1 and the second output node QB, and the control terminal receives the first pre-charge control signal LSH_EN, and the sixth transistor M6 is connected between the second transistor M2 and the first output node Q, and the control terminal receives the first pre-charge control signal LSH_EN. The first pre-charge control unit 30 controls the on-off of the first transistor M1 and the second output node QB and the on-off of the second transistor M2 and the first output node Q through the fifth transistor M5 and the sixth transistor M6.

[0049] The second pre-charge control unit 40 includes a seventh transistor M7 and an eighth transistor M8, wherein the seventh transistor M7 is connected between the second driving voltage terminal AVDD and the second output node QB, and the control terminal receives the second pre-charge control signal LSH_PCH, and the eighth transistor M8 is connected between the second driving voltage terminal AVDD and the first output node Q, and the control terminal receives the second pre-charge control signal LSH_PCH. The second pre-charge control unit 40 provides a pre-charge path to the first output node Q and the second output node QB through the seventh transistor M7 and the eighth transistor M8.

[0050] The fifth transistor M5 and the sixth transistor M6 are, for example, NPN transistors, and the seventh transistor M7 and the eighth transistor M8 are, for example, PNP transistors.

[0051] Figure 3 The figure shows a signal timing diagram of a level converter according to an embodiment of the present utility model.

[0052] like Figure 3 As shown, time t1 is the falling edge of the first control signal LSH_EN, time t2 is the falling edge of the second control signal LSH_PCH, time t3 is the rising edge of the second control signal LSH_PCH, and time t4 is the rising edge of the first control signal LSH_EN, wherein the time period t1-t4 corresponds to the above-mentioned pre-operation stage, and times t2 and t3 are within the time period t1-t4.

[0053] Each pre-operation stage starts before the level flip action of the input signal VIP and ends before the level flip action of the input signal VIP or between the level flip action and the next level flip action of the input signal VIP, and the time interval between two adjacent pre-operation stages is greater than the duration of each pre-operation stage.

[0054] Here, it is taken as an example that each pre-operation stage starts before the level flipping action of the input signal VIP and ends between the level flipping action and the next level flipping action of the input signal VIP.

[0055] At time t1 before the first input signal VIP flips, the first control signal LSH_EN flips to a low level, controlling the current path between the first transistor M1 and the second output node QB and the second transistor M2 and the first output node Q to be disconnected. At time t2 before the first input signal VIP flips, the second precharge control signal LSH_PCH flips to a low level, providing a precharge path to the first output node Q and the second output node QB, at which time the first output signal flips from a low level to a high level. At time t3 when the first input signal VIP flips, the first input signal VIP flips from a low level to a high level, and the switch tube M1 is turned on. At time t4, the first control signal LSH_EN flips from a low level to a high level, and the current path between the first transistor M1 and the second output node QB and the second transistor M2 and the first output node Q is turned on, at which time the second output signal flips from a high level to a low level.

[0056] It can be understood that if the start and end of each pre-operation phase are both before the level flipping action of the input signal VIP, the falling edge of the output signal of the first output node Q is controlled by the falling edge of the first input signal VIP.

[0057] By precharging the output node before the input signal is flipped, and cutting off the current path between the first output node Q and the second output node QB and the first drive voltage terminal GND, the problem of instantaneous large current charging the load of the first drive voltage terminal GND, resulting in flip failure, is avoided.

[0058] In addition, the present application also includes a first bias unit 50 and a second bias unit 60. The first bias unit 50 is connected between the second driving voltage terminal AVDD and the output unit 20, and receives a first bias voltage VBP, and is used to control the voltage drop between the second driving voltage terminal AVDD and the output unit 20 according to the first bias voltage VBP; the second bias unit 60 is connected between the output node and the input unit 10, and receives a second bias voltage VBN, and is used to control the voltage drop between the output node and the input unit 10 according to the second bias voltage VBN.

[0059] In one embodiment, the first bias unit 50 includes a ninth transistor M9 and a tenth transistor M10, the ninth transistor M9 is connected between the second driving voltage terminal AVDD and the third transistor M3, and the control terminal receives the first bias voltage VBP, the tenth transistor M10 is connected between the second driving voltage terminal AVDD and the fourth transistor M4, and the control terminal receives the first bias voltage VBP.

[0060] In one embodiment, the second bias unit 60 includes an eleventh transistor M11 and a twelfth transistor M12, the eleventh transistor M11 is connected between the first transistor M1 and the second output node QB, and the control end receives the second bias voltage VBN, the twelfth transistor M12 is connected between the second transistor M2 and the first output node Q, and the control end receives the second bias voltage VBN.

[0061] By properly setting the first bias voltage VBP and the second bias voltage VBN, the voltage output from the first bias unit 50 and the second bias unit 60 can be made smaller than the breakdown voltage of the transistors in the input unit 10 and the output unit 20, thereby achieving circuit protection.

[0062] Figure 4 A schematic diagram showing voltages at each node or current flowing through the level converter of the present application and the prior art is shown.

[0063] like Figure 4 As shown, through the level converter and the corresponding timing control provided by the present application, the level converter charges the output node in advance before each flip, so that when the input signal flips thereafter to make the output node and the first driving voltage terminal GND conductive, no large instantaneous current will be generated, thereby avoiding affecting the level flip of the output node. Figure 4It can be seen that under high resolution, the level converter in the prior art has too large instantaneous current when flipping at the same time, which causes the level converter to fail to flip smoothly, resulting in abnormal display. However, the level converter provided by the present application can flip smoothly by cutting off the connection between the output node and the second driving voltage terminal GND in advance and precharging the output node.

[0064] Figure 5 A schematic diagram of a display device according to an embodiment of the utility model is shown.

[0065] like Figure 5 As shown, a display device of an embodiment of the utility model includes a level converter in any embodiment of the present disclosure. The display device may be a display device including a source driver, and the source driver includes a level converter in any embodiment of the present disclosure. For example, the display device may be a liquid crystal display device, an organic light emitting display device, an electronic paper display device, etc.

[0066] The display device includes a display panel, and the display panel is, for example, any one of an OLED display panel, an LCD display panel, and an LED display panel.

[0067] The display panel includes a timing controller and a source driver. The timing controller is used to provide a timing signal, and the first pre-charge control signal LSH_EN and the second pre-charge control signal LSH_PCH to the source driver.

[0068] The source driver is used to provide corresponding driving voltages to multiple pixel units according to the above timing signals and the first precharge control signal LSH_EN and the second precharge control signal LSH_PCH. The source driver includes a shift register, a first latch unit, a second latch unit, a level converter, a digital-to-analog converter and an output buffer unit.

[0069] In one embodiment, the shift register may receive and generate a shift signal in response to a horizontal clock signal. The first latch unit may include a plurality of first latches, and the first latches synchronize the input image signal with the horizontal clock signal in response to the shift signal generated by the shift register, and sample the input image signal. The second latch unit may include a plurality of second latches and store the image data output from the first latch unit. The level converter converts the output data voltage of the second latch unit into a voltage level required by the circuit. For example, the digital-to-analog converter converts the digital voltage signal output by the level converter into an analog signal according to a reference voltage. The output buffer unit receives and amplifies the analog signal output by the digital-to-analog converter.

[0070] It should be additionally explained that the positions of the first biasing unit 50 and the second biasing unit 60 can be interchangeable, and the present application does not impose any limitation on this.

[0071] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that technicians in the relevant technical field can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A level converter, wherein: include: at least one output node, and an input unit connected between the at least one output node and the first driving voltage terminal, and used to control the first output node, the corresponding output node in the second output node and the first driving voltage terminal to be turned on according to an input signal, an output unit connected between the at least one output node and the second driving voltage terminal, and configured to control the corresponding output node to be conductive with the second driving voltage terminal according to the potential of the first output node and the second output node, and output a first output signal at the first output node and a second output signal at the second output node, A control unit is connected to the at least one output node, and is used to disconnect the input unit from the at least one output node in a pre-operation stage, and provide a current path between the at least one output node and the second driving voltage terminal during at least part of the pre-operation stage to facilitate pre-charging of the at least one output node, each of the pre-operation stages corresponding to a level flipping action of the input signal.

2. The level converter according to claim 1, wherein: Each of the pre-operation stages starts before the level inversion action of the input signal. It ends before the level flipping action of the input signal or between the level flipping action and the next level flipping action of the input signal. And the time interval between two adjacent pre-operation stages is greater than the duration of each of the pre-operation stages.

3. The level converter according to claim 2, wherein: The control unit comprises: A first pre-charge control unit, connected between the at least one output node and the input unit, and configured to control the input unit to be disconnected from the at least one output node according to a first pre-charge control signal; A second pre-charging control unit is connected in parallel with the output unit between the at least one output node and the second driving voltage terminal, and is used to control the conduction of the connection between the at least one output node and the second driving voltage terminal according to a second pre-charging control signal. The first pre-charge control signal is valid during the pre-operation phase, and the second pre-charge control signal is valid during at least part of the pre-operation phase.

4. The level converter according to claim 3, wherein: The input unit includes a first transistor and a second transistor, wherein the first transistor and the second transistor are connected between the first driving voltage terminal and the at least one output node. The control terminal of the first transistor receives a first input signal, and the first conduction terminal is connected to the first driving voltage terminal to receive a first driving voltage; The control terminal of the second transistor receives a second input signal, and the first conduction terminal is connected to the first driving voltage terminal to receive a first driving voltage. The first input signal is in antiphase with the second input signal.

5. The level converter according to claim 4, wherein: The output unit includes a third transistor and a fourth transistor, The third transistor is connected between the second driving voltage terminal and the second output node, and the control terminal of the third transistor is connected to the first output node; The fourth transistor is connected between the second driving voltage terminal and the first output node, and the control terminal of the fourth transistor is connected to the second output node.

6. The level converter according to claim 5, wherein: The first pre-charging control unit includes a fifth transistor and a sixth transistor, The fifth transistor is connected between the first transistor and the second output node, and a control terminal receives the first pre-charge control signal; The sixth transistor is connected between the second transistor and the first output node, and a control terminal receives the first pre-charge control signal.

7. The level converter according to claim 5, wherein: The second pre-charging control unit includes a seventh transistor and an eighth transistor, The seventh transistor is connected in parallel with the third transistor and the fourth transistor between the second driving voltage terminal and the second output node, The eighth transistor is connected in parallel with the third transistor and the fourth transistor between the second driving voltage terminal and the first output node, Wherein, the control terminals of the seventh transistor and the eighth transistor receive the second pre-charging control signal respectively.

8. The level converter according to claim 5, wherein: Also includes: a first bias unit connected between the second driving voltage terminal and the output unit and receiving a first bias voltage, and used for controlling a voltage drop between the second driving voltage terminal and the output unit according to the first bias voltage; The second bias unit is connected between the at least one output node and the input unit and receives a second bias voltage, and is used to control a voltage drop between the at least one output node and the input unit according to the second bias voltage.

9. The level converter according to claim 8, wherein: The first bias unit includes a ninth transistor and a tenth transistor, the ninth transistor is connected between the second driving voltage terminal and the third transistor, and the control terminal receives the first bias voltage; The tenth transistor is connected between the second driving voltage terminal and the fourth transistor, and the control terminal receives the first bias voltage; The second bias unit includes an eleventh transistor and a twelfth transistor, the eleventh transistor is connected between the first transistor and the second output node, and the control end receives the second bias voltage; the twelfth transistor is connected between the second transistor and the first output node, and the control end receives the second bias voltage.

10. The level converter according to claim 5, wherein: The first transistor and the second transistor are NPN transistors, and the third transistor and the fourth transistor are PNP transistors.

11. A source driver, wherein: A level converter comprising any one of claims 1 to 10.

12. A display panel, wherein: include: Pixel array; A timing controller, used for providing a timing signal and a first pre-charge control signal and a second pre-charge control signal; The source driver according to claim 11 is connected to the timing controller and the pixel array, and inputs a source driving signal to the pixel array according to the control of the timing controller.

13. The display panel according to claim 12, wherein: The display panel is any one of an OLED display panel, an LCD display panel, and a LED display panel.

14. A display device, characterized in that: Includes the display panel as claimed in claim 12.

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