Level conversion device, source driver and display device

Abstract

The utility model discloses a level conversion device, a source driver and a display device, comprising a plurality of level converters used for respectively receiving data voltage as input signals, an input unit used for controlling a corresponding output node to be conducted with a first driving voltage end according to the input signals, and an output unit used for controlling a corresponding output node to be conducted with a second driving voltage end according to the input signals, the input unit is used for controlling the corresponding output node to be connected with a second driving voltage end according to the potentials of the first output node and the second output node, and the control unit is connected with the output node and used for disconnecting the input unit from the output node according to an enable signal in a pre-operation stage. A current path between the output node and the second driving voltage end is provided in at least part of time of the pre-operation stage so as to pre-charge the output node, and the mode detection circuit compares the image data of the current driving line with the image data of the previous line so as to detect the image data of the current driving line. And a corresponding enable signal is provided for the control unit according to the comparison result. Therefore, the level shifter can smoothly turn over and is more power-saving at the same time.

Description

Technical Field

[0001] The utility model relates to the technical field of display driving, in particular to a level conversion device, a source driver and a display device. Background Art

[0002] With the rapid development of display technology, a large number of driving circuits are needed to improve the color depth, resolution and other performance of display devices. On the one hand, in order to make the display device thinner and lighter, it is necessary to reduce the size of the driving circuit in the display device. On the other hand, in order to reduce the power consumption of the display device, it is necessary to set the driving voltage to a lower level. However, the scanning signal line driving circuit and the data signal line driving circuit in the display device require a higher operating voltage. Due to the reduction of the driving voltage, the low voltage signal input by the peripheral circuit cannot make the scanning signal line driving circuit and the data signal line driving circuit in the display device work normally. Therefore, it is necessary to use a level shifter to raise the low voltage signal input by the peripheral circuit to the high operating voltage required by the driving circuit.

[0003] When the display driver drives the display panel with a single driver chip, at high resolution (such as 3552RGBx3840), the source driver needs to output 10656 (3552*3) grayscale voltages. At this time, the required level converters (LevelShift, LSH) will also reach 106560 (each grayscale voltage is 10 bits). In terms of design, when the 106560 level converters flip at the same time, the instantaneous current is too large, causing the level converters to fail to flip smoothly, resulting in display abnormalities.

[0004] like Figure 1 As shown, in the level converter in the prior art, the output voltage provided by the output nodes Q and QB is controlled by the switch tube M1, the switch tube M2, the switch tube M3 and the switch tube M4, and the control signals VIP and VIN received by the control ends of the switch tubes M1 and M2 are inversely proportional. When the control signal VIP is in a valid state, the switch tube M1 is turned on and the switch tube M2 is turned off. At this time, due to the simultaneous flipping of multiple level converters, the instantaneous current flowing through the switch tube M1 may be too large, so that the output node QB voltage cannot be pulled down by the ground terminal GND. When the control signal VIN is in a valid state, the switch tube M2 is turned on and the switch tube M1 is turned off. At this time, due to the simultaneous flipping of multiple level converters, the instantaneous current flowing through the switch tube M2 may be too large, so that the output node Q voltage cannot be pulled down by the ground terminal GND, so that the level converter cannot be flipped, thereby affecting the display effect. Utility Model Content

[0005] In view of the above problems, an object of the present invention is to provide a display driving technology field, and in particular to a level converter, a source driver and a display device, so that the level converter can be effectively flipped.

[0006] According to one aspect of the utility model, a level conversion device is provided, which includes: a plurality of level converters and a mode detection circuit, wherein the plurality of level converters are used to respectively receive data voltages corresponding to image data of a current driving row as input signals, each level converter includes: at least one output node, and an input unit connected between the at least one output node and a first driving voltage terminal, and used to control the first output node, the corresponding output node in the second output node and the first driving voltage terminal to be turned on according to the input signal, and the output unit is connected between the at least one output node and the second driving voltage terminal, and used to control the corresponding output node to be turned on according to the potential of the first output node and the second output node. An output node outputs a first output signal, and a second output node outputs a second output signal. A control unit is connected to the at least one output node and is used to disconnect the input unit from the at least one output node according to an enable signal in a pre-operation stage, and provide a current path between the at least one output node and the second driving voltage terminal during at least part of the pre-operation stage to facilitate pre-charging of the at least one output node. Each of the pre-operation stages corresponds to a level flipping action of the input signal. The mode detection circuit is used to receive image data line by line, compare the image data of the current driving line with the image data of the previous line, and provide the corresponding enable signal to the control unit according to the comparison result.

[0007] Optionally, each of the pre-operation stages starts before the level flipping action of the input signal and ends before the level flipping action of the input signal or between the level flipping action and the next level flipping action of the input signal, and the time interval between two adjacent pre-operation stages is greater than the duration of each of the pre-operation stages.

[0008] Optionally, the enable signal includes: a first pre-charge control signal and a second pre-charge control signal, and the control unit includes: a first pre-charge control unit, connected between the at least one output node and the input unit, and used to control the input unit to be disconnected from the at least one output node according to the first pre-charge control signal; a second pre-charge control unit, connected in parallel with the output unit between the at least one output node and the second drive voltage terminal, and used to control the conduction of the connection between the at least one output node and the second drive voltage terminal according to the second pre-charge control signal.

[0009] Optionally, the mode detection circuit includes a first latch unit, a first logic element, a second logic element, and a third logic element, wherein the first latch unit latches the image data of the previous row of the current driving row in response to a first latch enable signal; the first logic element has a first input end that receives the image data of the current driving row, a second input end that is connected to the first latch unit to receive the image data of the previous row of the current driving row, and an output end that outputs a comparison result between the image data of the current driving row and the image data of the previous row; the second logic element has a first input end that is connected to the output end of the first logic element, a second input end that receives the third pre-charge control signal, and an output end that outputs the first pre-charge control signal; the third logic element has a first input end that is connected to the output end of the first logic element, a second input end that receives the fourth pre-charge control signal, and an output end that outputs the second pre-charge control signal.

[0010] Optionally, the third pre-charge control signal is valid during the pre-operation phase, and the fourth pre-charge control signal is valid during at least part of the pre-operation phase.

[0011] Optionally, the first logic element is any one of an XOR gate and an XNOR gate; the second logic element and the third logic element are any one of an AND gate and an OR gate.

[0012] Optionally, inverters are respectively arranged between the second logic element, the third logic element and the first logic element, and / or the output ends of the second logic element and the third logic element are respectively arranged with a first level conversion unit and a second level conversion unit to perform level conversion on the output signals of the second logic element and the third logic element.

[0013] According to another aspect of the utility model, a source driver is provided, which is used to receive image data row by row according to a timing signal, and drive the corresponding row of pixel units to display a picture, including the level conversion device described in any one of the above items, and a second latch unit and a third latch unit, wherein the second latch unit synchronizes the input image signal with the horizontal clock signal in response to a shift signal, and samples the input image signal to obtain image data; the third latch unit latches the image data of the current driven row output from the second latch unit in response to a second latch enable signal, and provides it to the level conversion device.

[0014] Optionally, the first latch unit is connected to the second latch unit, and in response to a first latch enable signal, latches the previous row image data of the current driving row output from the second latch unit, the first input end of the first logic element is connected to the third latch unit, and the second input end is connected to the first latch unit, the first latch enable signal and the second latch enable signal change synchronously, so that the first logic element simultaneously receives the previous row image data of the current driving row and the image data of the current driving row for comparison.

[0015] According to another aspect of the present invention, a display device is provided, comprising: the above-mentioned source driver and a timing controller, which is used to provide a timing signal, the third pre-charge control signal and the fourth pre-charge control signal to the source driver.

[0016] The level converter provided in the present application switches off the connection between the output node and the second driving voltage terminal GND in advance and precharges the output node, so that the level converter can be flipped smoothly.

[0017] In a preferred embodiment, by setting a bias unit and reasonably setting the first bias voltage and the second bias voltage, the voltage output from the first bias unit and the second bias unit can be smaller than the breakdown voltage of the transistors in the input unit and the output unit, thereby achieving circuit protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 A circuit diagram of a level converter according to the prior art is shown.

[0020] Figure 2 A circuit diagram of a level converter according to an embodiment of the utility model is shown.

[0021] Figure 3 The figure shows a signal timing diagram of a level converter according to an embodiment of the present utility model.

[0022] Figure 4 A schematic diagram of a display device according to an embodiment of the utility model is shown.

[0023] Figure 5 A mode detection circuit diagram according to an embodiment of the utility model is shown.

[0024] Figure 6 The figure shows a signal timing diagram of a mode detection circuit according to an embodiment of the present utility model.

[0025] Figure 7 A schematic diagram showing power comparison of each power source before and after setting the mode detection circuit according to an embodiment of the utility model is shown. DETAILED DESCRIPTION

[0026] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0027] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0028] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0029] In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention may be implemented without following these specific details.

[0030] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0031] Figure 2 A circuit diagram of a level converter according to an embodiment of the utility model is shown.

[0032] like Figure 2 As shown, the level converter 1 of the embodiment of the present utility model includes an input unit 11, an output unit 12, and a control unit.

[0033] The input unit 11 is connected between the first output node Q, the second output node QB and the first driving voltage terminal, and is used to control the corresponding output node among the first output node Q and the second output node QB to be conductive with the first driving voltage terminal according to an input signal.

[0034] The input unit 11 includes a first transistor M1 and a second transistor M2. The control terminal of the first transistor M1 receives a first input signal VIP, and the first conduction terminal is connected to the first driving voltage terminal GND to receive the first driving voltage; the control terminal of the second transistor M2 receives a second input signal VIN, and the first conduction terminal is connected to the first driving voltage terminal GND to receive the first driving voltage. The second input signal VIN may be inverted with the first input signal VIP.

[0035] In one embodiment, the first driving voltage may be a ground voltage, for example, the first driving voltage is 0V.

[0036] The output unit 12 is connected between the first output node Q, the second output node QB and the second driving voltage terminal AVDD, and is used to control the corresponding output node to be connected to the second driving voltage terminal AVDD according to the potential of the first output node Q and the second output node QB, thereby outputting the first output signal through the first output node QB and the second output signal through the second output node Q. The second driving voltage is higher than the first driving voltage.

[0037] The output unit 12 includes a third transistor M3 and a fourth transistor M4. The third transistor M3 is connected between the second driving voltage terminal AVDD and the second output node QB, the first conduction terminal of the third transistor M3 is connected to the second output node QB to output the second output signal at the second output node QB, and the control terminal is connected to the first output node Q. The fourth transistor M4 is connected between the second driving voltage terminal AVDD and the first output node Q, the first conduction terminal of the fourth transistor M4 is connected to the first output node Q to output the first output signal at the first output node Q, and the control terminal is connected to the second output node QB.

[0038] In one embodiment, the first transistor M1 and the second transistor M2 are NPN transistors, and the third transistor M3 and the fourth transistor M4 are PNP transistors.

[0039] The conventional working principle of the circuit is that when the first input signal VIP is at a high level (e.g., 1.8V), the first transistor M1 is turned on. Since the second input signal VIN is inverted with the first input signal VIP, the second input signal VIN is at a low level, the second transistor M2 is turned off, and the potential of the second output node QB is the first driving voltage (low potential). The potential of the control terminal of the fourth transistor M4 is pulled down, thereby making the second driving voltage terminal AVDD conductive with the first output node Q, and the first output node Q outputs the first output signal affected by the second driving voltage terminal AVDD, which is a high voltage first output signal converted by the level converter, and the second output node QB outputs a low voltage second output signal inverted with the first output node Q.

[0040] When the first input signal VIP is at a low level, the first transistor M1 is turned off. Since the second input signal VIN is in phase opposition to the first input signal VIP, the second input signal VIN is at a low level, the second transistor M2 is turned on, and the potential of the first output node Q is the first driving voltage (low potential). The potential of the control terminal of the third transistor M3 is pulled down, thereby making the second driving voltage terminal AVDD conductive with the second output node QB, and the second output node QB outputs the second output signal affected by the second driving voltage terminal AVDD, the second output signal is a high voltage second output signal converted by the level converter, and the first output node Q outputs a low voltage first output signal in phase opposition to the second output node QB.

[0041] In this process, when the first input signal VIP is flipped to a high level, the first transistor M1 is turned on and the second transistor M2 is turned off. At this time, due to the fact that multiple level converters are flipped at the same time, the instantaneous current flowing through the switch tube M1 is too large, so that the voltage of the second output node QB cannot be pulled down by the ground terminal GND. When the second input signal VIN is flipped to a high level, the second transistor M2 is turned on and the first transistor M1 is turned off. At this time, due to the fact that multiple level converters are flipped at the same time, the instantaneous current flowing through the second transistor M2 is too large, so that the voltage of the output node Q cannot be pulled down by the ground terminal GND, so that the level converter cannot be flipped, thereby affecting the display effect.

[0042] Based on this, the level converter 1 provided in the present application also includes a control unit, which is connected to at least one output node, and is used to disconnect the input unit 11 from at least one output node according to an enable signal in the pre-operation stage, and provide a current path between at least one output node and the second driving voltage terminal GND during at least part of the pre-operation stage to facilitate pre-charging of at least one output node, and each pre-operation stage corresponds to a level flipping action of the input signal.

[0043] The enable signal includes a first precharge control signal LSH_EN_1 and a second precharge control signal LSH_PCH_1.

[0044] The control unit includes: a first pre-charging control unit 13, connected between at least one output node and the input unit 11, and used to control the input unit 11 to be disconnected from at least one output node according to a first pre-charging control signal LSH_EN; a second pre-charging control unit 14, connected in parallel with the output unit 12 between at least one output node and the second driving voltage terminal AVDD, and used to control the conduction of the connection between at least one output node and the second driving voltage terminal AVDD according to a second pre-charging control signal LSH_PCH.

[0045] The first pre-charging control unit 13 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 is connected between the first transistor M1 and the second output node QB, and the control end receives the first pre-charging control signal LSH_EN_1. The sixth transistor M6 is connected between the second transistor M2 and the first output node Q, and the control end receives the first pre-charging control signal LSH_EN_1.

[0046] The first pre-charging control unit 13 controls the connection and disconnection between the first transistor M1 and the second output node QB and the connection and disconnection between the second transistor M2 and the first output node Q through the fifth transistor M5 and the sixth transistor M6 .

[0047] The second pre-charge control unit 14 includes a seventh transistor M7 and an eighth transistor M8, wherein the seventh transistor M7 is connected between the second driving voltage terminal AVDD and the second output node QB, and the control terminal receives the second pre-charge control signal LSH_PCH_1, and the eighth transistor M8 is connected between the second driving voltage terminal AVDD and the first output node Q, and the control terminal receives the second pre-charge control signal LSH_PCH_1. The second pre-charge control unit 14 provides a pre-charge path to the first output node Q and the second output node QB through the seventh transistor M7 and the eighth transistor M8.

[0048] The fifth transistor M5 and the sixth transistor M6 are, for example, NPN transistors, and the seventh transistor M7 and the eighth transistor M8 are, for example, PNP transistors.

[0049] Figure 3 The figure shows a signal timing diagram of a level converter according to an embodiment of the present utility model.

[0050] like Figure 3 As shown, time t1 is the falling edge of the first control signal LSH_EN, time t2 is the falling edge of the second control signal LSH_PCH, time t3 is the rising edge of the second control signal LSH_PCH, and time t4 is the rising edge of the first control signal LSH_EN, wherein the time period t1-t4 corresponds to the above-mentioned pre-operation stage, and times t2 and t3 are within the time period t1-t4.

[0051] Each pre-operation stage starts before the level flip action of the input signal VIP and ends before the level flip action of the input signal VIP or between the level flip action and the next level flip action of the input signal VIP, and the time interval between two adjacent pre-operation stages is greater than the duration of each pre-operation stage.

[0052] Here, it is taken as an example that each pre-operation stage starts before the level flipping action of the input signal VIP and ends between the level flipping action and the next level flipping action of the input signal VIP.

[0053] At time t1 before the first input signal VIP flips, the first control signal LSH_EN_1 flips to a low level, controlling the current path between the first transistor M1 and the second output node QB and the second transistor M2 and the first output node Q to be disconnected. At time t2 before the first input signal VIP flips, the second pre-charge control signal LSH_PCH_1 flips to a low level, providing a pre-charge path to the first output node Q and the second output node QB, at which time the first output signal flips from a low level to a high level. At time t3 when the first input signal VIP flips, the first input signal VIP flips from a low level to a high level, and the switch tube M1 is turned on. At time t4, the first control signal LSH_EN_1 flips from a low level to a high level, and the current path between the first transistor M1 and the second output node QB and the second transistor M2 and the first output node Q is turned on, at which time the second output signal flips from a high level to a low level.

[0054] It can be understood that if the start and end of each pre-operation phase are both before the level flipping action of the input signal VIP, the falling edge of the output signal of the first output node Q is controlled by the falling edge of the first input signal VIP.

[0055] By precharging the output node before the input signal is flipped, and cutting off the current path between the first output node Q and the second output node QB and the first drive voltage terminal GND, it is avoided that a large current at the moment of flipping charges the load of the first drive voltage terminal GND, thereby causing the flipping failure.

[0056] In addition, the present application also includes a first bias unit 15 and a second bias unit 16. The first bias unit 15 is connected between the second driving voltage terminal AVDD and the output unit 12, and receives a first bias voltage VBP, and is used to control the voltage drop between the second driving voltage terminal AVDD and the output unit 12 according to the first bias voltage VBP; the second bias unit 16 is connected between the output node and the input unit 11, and receives a second bias voltage VBN, and is used to control the voltage drop between the output node and the input unit 11 according to the second bias voltage VBN.

[0057] In one embodiment, the first bias unit 15 includes a ninth transistor M9 and a tenth transistor M11, the ninth transistor M9 is connected between the second driving voltage terminal AVDD and the third transistor M3, and the control terminal receives the first bias voltage VBP, the tenth transistor M11 is connected between the second driving voltage terminal AVDD and the fourth transistor M4, and the control terminal receives the first bias voltage VBP.

[0058] In one embodiment, the second bias unit 16 includes an eleventh transistor M11 and a twelfth transistor M12, the eleventh transistor M11 is connected between the first transistor M1 and the second output node QB, and the control end receives the second bias voltage VBN, the twelfth transistor M12 is connected between the second transistor M2 and the first output node Q, and the control end receives the second bias voltage VBN.

[0059] By properly setting the first bias voltage VBP and the second bias voltage VBN, the voltage output from the first bias unit 15 and the second bias unit 16 can be made smaller than the breakdown voltage of the transistors in the input unit 11 and the output unit 12, thereby achieving circuit protection.

[0060] Through the level converter provided by the present application and the corresponding timing control, the level converter charges the output node in advance before each flipping, so that when the input signal flips thereafter and the output node is connected to the first drive voltage terminal GND, no large instantaneous current will be generated, thereby avoiding affecting the level flipping of the output node. The level converter in the prior art has too large instantaneous current when flipping at the same time, causing the level converter to fail to flip smoothly, resulting in abnormal display. The level converter provided by the present application disconnects the connection between the output node and the second drive voltage terminal GND in advance, and pre-charges the output node, so that the level converter can flip smoothly.

[0061] It should be additionally explained that the positions of the first biasing unit 30 and the second biasing unit can be interchangeable, and the present application does not impose any limitation on this.

[0062] Figure 4 A schematic diagram of a display device according to an embodiment of the utility model is shown.

[0063] like Figure 4 As shown, a display device of an embodiment of the utility model includes a level converter in any embodiment of the present disclosure. The display device may be a display device including a source driver, and the source driver includes a level converter in any embodiment of the present disclosure. For example, the display device may be a liquid crystal display device, an organic light emitting display device, an electronic paper display device, etc.

[0064] The display device includes a timing controller 3 and a source driver.

[0065] The timing controller 3 is used to provide a timing signal to the source driver, and to provide a third pre-charge control signal LSH_EN_2 and a fourth pre-charge control signal LSH_PCH_2 to the mode detection circuit 2; the source driver is used to receive image data line by line according to the timing signal, and drive the corresponding row of pixel units to display the picture.

[0066] The source driver includes a shift register 4 , a first latch unit 5 , a second latch unit 6 , a level conversion device, a digital-to-analog converter 7 and an output buffer unit 8 .

[0067] In one embodiment, the shift register 4 can receive and generate a shift signal in response to a horizontal clock signal. The second latch unit 5 can include a plurality of second latches, and the second latches synchronize the input image signal with the horizontal clock signal in response to the shift signal generated by the shift register 4, and sample the input image signal. The third latch unit 6 can include a plurality of third latches and store the image data output from the second latch unit 5. The level conversion device converts the output data voltage of the third latch unit 6 into a voltage level required by the circuit. For example, the digital-to-analog converter 7 converts the digital voltage signal output by the level converter 1 into an analog signal according to a reference voltage. The output buffer unit 8 receives and amplifies the analog signal output by the digital-to-analog converter.

[0068] In one embodiment, the level conversion device includes a plurality of the above-mentioned level converters 1 and a mode detection circuit 2, wherein the mode detection circuit 2 is used to receive image data line by line, compare the image data of the current driven line with the image data of the previous line, and provide a corresponding enable signal to the control unit according to the comparison result.

[0069] Figure 5 A mode detection circuit diagram according to an embodiment of the utility model is shown. Figure 6 The figure shows a signal timing diagram of a mode detection circuit according to an embodiment of the present utility model.

[0070] Specifically, Figure 5 and Figure 6 In combination, the second latch unit 5 samples the input image signal according to the shift signal SAM generated by the shift register 4. After a row of image data is full, the third latch unit 6 latches the image data Dout2 (N) of the current driving row output from the second latch unit 5 according to the second latch enable signal LD, and provides it to the level converter 1.

[0071] The mode detection circuit 2 includes a first latch unit 21 , a first logic element 22 , a second logic element 23 , and a third logic element 24 .

[0072] The first latch unit 21 includes a plurality of first latches for latching the previous line image data Dout2 (N-1) of the current driving line outputted from the first latch unit 5 according to the first latch enable signal LD1.

[0073] The first logic element 22 has a first input end connected to the second latch unit 6 to receive the image data Dout2(N) of the current driving row, a second input end connected to the third latch unit 21 to receive the image data Dout2(N-1) of the previous row of the current driving row, and an output end outputs the comparison result of the image data Dout2(N) of the current driving row and the image data Dout2(N-1) of the previous row. In one embodiment, the first logic element 22 is, for example, any one of an XOR gate and an XOR gate, which is used to determine whether the inputs of the two input ends are the same. The first latch enable signal LD1 and the second latch enable signal LD ​​change synchronously (there may be a slight time difference here), so that the first logic element 22 simultaneously receives the image data of the previous row of the current driving row and the image data of the current driving row for comparison.

[0074] The second logic element 23 has a first input terminal connected to the output terminal of the first logic element 22, a second input terminal receiving the third pre-charge control signal LSH_EN_2, and an output terminal outputting the first pre-charge control signal LSH_EN_1. In one embodiment, the second logic element 23 is, for example, an AND gate or an OR gate. When the third pre-charge control signal LSH_EN_2 and the comparison result are both at a high level or a low level, a valid first pre-charge control signal LSH_EN_1 is output.

[0075] The third logic element 24 has a first input terminal connected to the output terminal of the first logic element 22, a second input terminal receiving the fourth pre-charge control signal LSH_PCH_2, and an output terminal outputting the second pre-charge control signal LSH_PCH_1. In one embodiment, the third logic element 24 is, for example, an AND gate or an OR gate. When the fourth pre-charge control signal LSH_PCH_2 and the comparison result are both at a high level or a low level, a valid second pre-charge control signal LSH_PCH_1 is output.

[0076] In one embodiment, inverters are respectively provided between the second logic element 23 , the third logic element 24 and the first logic element 22 to adjust the high and low level relationship between the two input terminals of the second logic element 23 and the third logic element 24 .

[0077] In one embodiment, the output ends of the second logic element 23 and the third logic element 24 are also connected to inverters to adjust the high and low levels of the output end signals of the second logic element 23 and the third logic element 24. The output ends of the second logic element 23 and the third logic element 24 are also provided with a first level conversion unit 25 and a second level conversion unit 26, respectively, for performing level conversion on the output ends of the second logic element 23 and the third logic element 24 to obtain a suitable driving potential.

[0078] In one embodiment, the third pre-charge control signal LSH_EN_2 is configured to be valid in the pre-operation phase to control the current paths between the first transistor M1 and the second output node QB and between the second transistor M2 and the first output node Q to be disconnected.

[0079] The fourth pre-charge control signal LSH_PCH_2 is configured to be valid at least part of the time during the pre-operation phase to provide a pre-charge path for the first output node Q and the second output node QB.

[0080] At the same time, the third pre-charge control signal LSH_EN_2 and the fourth pre-charge control signal LSH_PCH_2 are logically operated with the comparison result of the image data Dout2(N) of the current driving row and the image data Dout2(N-1) of the previous row, and finally the first pre-charge control signal LSH_EN_1 and the second pre-charge control signal LSH_PCH_1 of the corresponding state are output. When the image data does not change, the level converter does not perform the pre-charge operation, so as to realize low power consumption operation.

[0081] Figure 7 A schematic diagram showing power comparison of each power source before and after setting the mode detection circuit according to an embodiment of the utility model is shown.

[0082] like Figure 7 As shown in the circuit simulation results at 4K resolution, it can be seen that when the input remains unchanged, the difference between adding the above-mentioned mode detection circuit 2 and not adding it. When the mode detection circuit 2 is added, the instantaneous current of the first driving voltage terminal AVSS and the second driving voltage terminal AVDD is significantly smaller, and the overall average current is also reduced from tens of mA to hundreds of uA, and the power is significantly better than when the mode detection circuit 2 is not added.

[0083] It should be noted that it will be understood by those skilled in the art that the words "during", "when" and "when..." used in this document in connection with the operation of the circuit are not strict terms indicating an action that occurs immediately when the start-up action begins, but rather that there may be some small but reasonable delay or delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this document mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0084] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that technicians in the relevant technical field can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A level conversion device, wherein: include: Multiple level shifters and mode detection circuits, The plurality of level converters are used to respectively receive data voltages corresponding to the image data of the current driving row as input signals, Each level converter includes: at least one output node, and an input unit connected between the at least one output node and the first driving voltage terminal, and used to control the first output node, the corresponding output node in the second output node and the first driving voltage terminal to be turned on according to the input signal, an output unit connected between the at least one output node and the second driving voltage terminal, and configured to control the corresponding output node to be conductive with the second driving voltage terminal according to the potential of the first output node and the second output node, and output a first output signal at the first output node and a second output signal at the second output node, a control unit connected to the at least one output node, configured to disconnect the input unit from the at least one output node according to an enable signal in a pre-operation phase, and provide a current path between the at least one output node and the second driving voltage terminal during at least part of the pre-operation phase, so as to pre-charge the at least one output node, wherein each of the pre-operation phases corresponds to a level flipping action of the input signal, The mode detection circuit is used to receive image data line by line, compare the image data of the current driving line with the image data of the previous line, and provide the corresponding enable signal to the control unit according to the comparison result.

2. The level conversion device according to claim 1, wherein: Each of the pre-operation stages starts before the level inversion action of the input signal. It ends before the level flipping action of the input signal or between the level flipping action and the next level flipping action of the input signal. And the time interval between two adjacent pre-operation stages is greater than the duration of each of the pre-operation stages.

3. The level conversion device according to claim 2, wherein: The enable signal includes: a first precharge control signal and a second precharge control signal, The control unit comprises: a first pre-charging control unit, connected between the at least one output node and the input unit, and configured to control the input unit to be disconnected from the at least one output node according to the first pre-charging control signal; A second pre-charging control unit is connected in parallel with the output unit between the at least one output node and the second driving voltage terminal, and is used to control the conduction of the connection between the at least one output node and the second driving voltage terminal according to the second pre-charging control signal.

4. The level conversion device according to claim 3, wherein: The mode detection circuit includes a first latch unit, a first logic element, a second logic element, and a third logic element. The first latch unit latches the image data of a previous row of the current driving row in response to a first latch enable signal; The first logic element has a first input end receiving the image data of the current driving row, a second input end connected to the first latch unit to receive the image data of a previous row of the current driving row, and an output end outputting a comparison result between the image data of the current driving row and the image data of the previous row; a second logic element, wherein a first input terminal is connected to an output terminal of the first logic element, a second input terminal receives a third precharge control signal, and an output terminal outputs a first precharge control signal; The third logic element has a first input terminal connected to the output terminal of the first logic element, a second input terminal receiving a fourth precharge control signal, and an output terminal outputting a second precharge control signal.

5. The level conversion device according to claim 4, wherein: The third pre-charge control signal is effective during the pre-operation phase, and the fourth pre-charge control signal is effective during at least a portion of the pre-operation phase.

6. The level conversion device according to claim 5, wherein: The first logic element is any one of an XOR gate and an XNOR gate; The second logic element and the third logic element are any one of an AND gate and an OR gate.

7. The level conversion device according to claim 6, wherein: Inverters are also provided between the second logic element, the third logic element and the first logic element respectively. And / or the output ends of the second logic element and the third logic element are further provided with a first level conversion unit and a second level conversion unit respectively, so as to perform level conversion on the output signals of the second logic element and the third logic element.

8. A source driver for receiving image data line by line according to a timing signal and driving corresponding rows of pixel units to display a picture, comprising the level conversion device according to any one of claims 4 to 7, and The second latch unit and the third latch unit, The second latch unit synchronizes the input image signal with the horizontal clock signal in response to the shift signal, and samples the input image signal to obtain image data; The third latch unit latches the image data of the current driving row output from the second latch unit in response to the second latch enable signal, and provides the image data to the level conversion device.

9. The source driver according to claim 8, wherein: The first latch unit is connected to the second latch unit, and latches the image data of the previous row of the current driving row output from the second latch unit in response to the first latch enable signal. The first input end of the first logic element is connected to the third latch unit, and the second input end is connected to the first latch unit. The first latch enable signal and the second latch enable signal change synchronously, so that the first logic element simultaneously receives the previous row image data of the current drive row and the image data of the current drive row for comparison.

10. A display device, comprising: The source driver according to claim 8 or 9 and The timing controller is used to provide a timing signal, the third pre-charge control signal and the fourth pre-charge control signal to the source driver.

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