Level shifter, drive circuit, and display device
By designing a level converter including input circuit, output circuit and boost circuit, the problem that level converters in the prior art cannot effectively convert low voltage signals, and the leakage problem of the inverter is solved and the power consumption reduction of the inverter is achieved.
Patent Information
- Application Number
- CN202421246378.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-31
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-05-31
AI Technical Summary
Existing level converters cannot effectively convert low voltage signals into high voltage signals in high resolution display devices, resulting in leakage problems of inverter and increasing power consumption.
A level converter is designed, including an input circuit, an output circuit and a boost circuit, and the output voltage is inverted through an inverter, and a combined boost mechanism of the first pull-up unit and the second pull-up unit is used to ensure that the voltage is pulled up to the desired level and avoid leakage.
It effectively solves the leakage problem of the inverter, reduces the power consumption of the level converter, and meets the rotation time requirements of the level converter by high-resolution display devices.
Smart Images
Figure CN222619398U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of display driving, in particular to a level converter, a driving circuit and a display device. Background Art
[0002] With the rapid development of display technology, a large number of driving circuits are needed to improve the color depth, resolution and other performance of display devices. On the one hand, in order to make the display device thinner and lighter, the size of the driving circuit in the display device needs to be reduced. On the other hand, in order to reduce the power consumption of the display device, the driving voltage needs to be set lower. However, the scanning signal line driving circuit and the data signal line driving circuit in the display device require a higher operating voltage. Due to the reduction of the driving voltage, the peripheral
[0003] The low voltage signal input by the circuit cannot make the scanning signal line driving circuit and the data signal line driving circuit in the display device work normally. Therefore, a level converter is needed to increase the low voltage signal input by the peripheral circuit to the high working voltage required by the driving circuit.
[0004] In the case of a high resolution (such as 4K×4K) and a demultiplexer (DEMUX) technology, the transition time plus the IR drop must be ensured to be within 40ns. Therefore, it is impossible to shorten the flip time by using the pre-charging technology. The display device of the prior art uses an RCC pull-up network (Regulated Cross Coupled Pull Up Network) to achieve level conversion. However, when converting a low voltage signal to a high voltage signal, this type of level converter cannot completely pull the high voltage signal high. As a result, after the high voltage signal is provided to the input end of the inverter, the inverter will have a leakage problem, which increases the power consumption of the level converter.
[0005] Therefore, a new level converter is needed to solve the above problems. Utility Model Content
[0006] In view of the above problems, the purpose of the present invention is to provide a level converter, a driving circuit and a display device, so as to solve the leakage problem of the level converter and reduce power consumption.
[0007] According to one aspect of the utility model, a level converter is provided, comprising an input circuit for controlling one of a first output node and a second output node to be electrically connected to a first power supply voltage according to an inverted first input signal and a second input signal; an output circuit for controlling the voltage of another output node to be equal to a second power supply voltage according to the voltage of the output node electrically connected to the first power supply voltage;
[0008] A boost circuit is connected to the output circuit at a first pull-up node and a second pull-up node, and is used to pull up the voltage of a pull-up node corresponding to an output node electrically connected to the first power supply voltage to the second power supply voltage, wherein the first output node corresponds to the first pull-up node, and the second output node corresponds to the second pull-up node; at least one inverter is used to invert the voltage of at least one output node to obtain an output voltage, wherein the boost circuit includes: a first pull-up unit and a second pull-up unit, and in the process of pulling up the corresponding pull-up node to the second power supply voltage, when the voltage of the corresponding pull-up node reaches the first voltage, the first pull-up unit no longer works on pulling up the node, and the second pull-up unit pulls up the voltage of the node to the second power supply voltage.
[0009] Optionally, the level converter is configured such that when the first input signal jumps to a high level, the first output node is electrically connected to the first power supply voltage, and when the first input signal jumps to a low level, the second output node is electrically connected to the first power supply voltage, wherein the second power supply voltage is greater than the first power supply voltage.
[0010] Optionally, the first pull-up unit includes a first transistor, a first end of which is connected to the second power supply voltage, a second end of which is connected to the first pull-up node, and a control end of which is connected to the first output node; a second transistor, a first end of which is connected to the second power supply voltage, a second end of which is connected to the second pull-up node, and a control end of which is connected to the second output node.
[0011] Optionally, the second pull-up unit comprises a third transistor, a first end of which is connected to the second power supply voltage, a second end of which is connected to the first pull-up node, and a control end of which is connected to the first bias voltage;
[0012] A fourth transistor has a first end connected to the second power supply voltage, a second end connected to the second pull-up node, and a control end connected to the first bias voltage.
[0013] Optionally, the input circuit includes a fifth transistor, whose control end is connected to the first input signal, whose first end is connected to the first output node, and whose second end is connected to the first power supply voltage; a sixth transistor, whose control end is connected to the second input signal, whose first end is connected to the second output node, and whose second end is connected to the first power supply voltage; and the output circuit includes a seventh transistor, whose first end is connected to the first pull-up node, whose second end is connected to the first output node, and whose control end is connected to the second output node; and an eighth transistor, whose first end is connected to the second pull-up node, whose second end is connected to the second output node, and whose control end is connected to the first output node.
[0014] Optionally, the level converter further includes a protection circuit connected between the output circuit and the input circuit, for limiting the current flowing through the inverter, and controlling the voltage drop between the output circuit and the input circuit by setting a second bias voltage.
[0015] Optionally, the protection circuit includes a ninth transistor and a tenth transistor connected sequentially between the first output node and the first end of the fifth transistor, and an eleventh transistor and a twelfth transistor connected sequentially between the second output node and the second end of the sixth transistor, wherein the control end of the ninth transistor is connected to its second end, the control end of the eleventh transistor is connected to its second end, and the control ends of the tenth transistor and the twelfth transistor are connected to the second bias voltage.
[0016] Optionally, the on-state voltage drops of the third transistor and the fourth transistor are preset multiples of the on-state voltage drops of the fifth transistor and the sixth transistor.
[0017] According to a second aspect of the present invention, a driving circuit is provided, comprising a shift register, the above-mentioned level converter, a digital-to-analog converter and an operational amplifier.
[0018] According to a third aspect of the utility model, a display device is provided, including a display panel, including a pixel array composed of a plurality of pixel units; a driving circuit as described above, wherein the driving circuit provides corresponding driving voltages to the plurality of pixel units according to a digital clock signal.
[0019] The utility model provides a level converter, a driving circuit and a display device, wherein the level converter comprises: an input circuit for controlling one of a first output node and a second output node to be electrically connected to a first power supply voltage according to an inverted first input signal and a second input signal; an output circuit for controlling the voltage of another output node to be equal to the second power supply voltage according to the voltage of the output node electrically connected to the first power supply voltage; a boost circuit connected to the first pull-up node and the second pull-up node with the output circuit, and used to pull up the voltage of the pull-up node corresponding to the output node electrically connected to the first power supply voltage to the second power supply voltage; at least one inverter for inverting the voltage of at least one output node to obtain an output voltage, wherein the boost circuit comprises a first pull-up unit and a second pull-up unit, and in the process of pulling up the corresponding pull-up node to the second power supply voltage, when the voltage of the corresponding pull-up node reaches the first voltage, the first pull-up unit no longer acts on the pull-up of the node, and the second pull-up unit pulls up the voltage of the node to the second power supply voltage, thereby improving the leakage problem of the inverter and reducing the power consumption of the level converter. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0021] Figure 1 A circuit diagram of a level converter is shown;
[0022] Figure 2 A circuit diagram of a level converter according to an embodiment of the utility model is shown;
[0023] Figure 3 Shows Figure 1 The level shifter shown with Figure 2 Simulation comparison diagram of the level converter shown;
[0024] Figure 4 A circuit diagram of a driving circuit according to an embodiment of the utility model is shown. DETAILED DESCRIPTION
[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0026] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0027] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0028] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0029] Figure 1 A circuit diagram of a level converter is shown.
[0030] See also Figure 1The level converter 100 includes transistors M1, M3, M5, M7 and M9 connected in sequence between the power supply voltage AVDD_1 and the power supply voltage VSSD, and transistors M2, M4, M6, M8 and M10 connected in sequence between the power supply voltage AVDD_1 and the power supply voltage VSSD. Among them, the control ends of the transistors M10 and M9 are respectively connected to the inverted first input signal IN and the second input signal INB, the control ends of the transistors M7 and M8 are connected to the bias voltage VBN1, the control ends of the transistors M5 and M6 are connected to their second ends, the second end of the transistor M3 and the first end of the transistor M5 are connected to the second output node OT1, the second end of the transistor M4 and the first end of the transistor M6 are connected to the first output node OB1, the control ends of the transistors M2 and M3 are connected to the first output node OB1, and the control ends of the transistors M1 and M4 are connected to the second output node OT1.
[0031] In addition, the level converter 100 also includes an inverter composed of transistors M11 and M12, the transistors M11 and M12 are connected between the power supply voltage AVDD_2 and the power supply voltage VSSA in sequence, the control end of the transistor M11 is connected to the first output node OB1, the control end of the transistor M12 is connected to the first end of the transistor M8, and the common node of the transistors M11 and M12 serves as the output end OUT1 of the inverter to provide an output voltage.
[0032] When the level converter 100 operates in a steady state, if the first input signal IN jumps to a low level, the second input signal INB jumps to a high level. At this time, the transistor M9 is turned on, the transistor M10 is turned off, and the second output node OT1 is pulled down to a low level by the power supply voltage VSSD, so that the transistor M4 and the transistor M1 are turned on, and the transistor M1 pulls up the voltage of the first end of the transistor M3 to AVDD_1-Vth1 (Vth1 represents the threshold voltage of the transistor M1), and the transistor M4 pulls up the voltage of the first output node OB1 to AVDD_1-Vth2 (Vth2 represents the threshold voltage of the transistor M2).
[0033] If the first input signal IN jumps to a high level, the second input signal INB jumps to a low level. At this time, the transistor M10 is turned on, the transistor M9 is turned off, and the first output node OB1 is pulled down to a low level by the power supply voltage VSSD, so that the transistor M3 and the transistor M2 are turned on, and the transistor M2 pulls up the voltage of the first end of the transistor M4 to AVDD_1-Vth2, and the transistor M3 pulls up the voltage of the second output node OT1 to AVDD_1-Vth1.
[0034] When the first output node OB1 is at a high level, the voltage of the first output node OB1 is at most AVDD_1-Vth2. When this voltage is provided to the transistor M11, the transistor M11 cannot be completely turned off, resulting in leakage of the inverter and increasing the power consumption of the level converter 100.
[0035] Based on this, the utility model proposes a new level converter, which can improve the leakage problem of the inverter.
[0036] Figure 2 A circuit diagram of a level converter according to an embodiment of the utility model is shown.
[0037] In one embodiment of the present invention, the level converter 200 includes an input circuit 210 , an output circuit 220 , a boost circuit 230 , and an inverter 240 .
[0038] The input circuit 210 is connected between the first output node OB2, the second output node OT2 and the power supply voltage VSSD, and is used to control one of the first output node OB2 and the second output node OT2 to be electrically connected to the power supply voltage VSSD according to the first input signal IN and the second input signal INB.
[0039] The input circuit 210 includes transistors M9 and M10, the second terminals of the transistors M9 and M10 are connected to the power supply voltage VSSD, the control terminal of the transistor M10 receives the first input signal IN, the first terminal of the transistor M10 is connected to the first output node OB2, the control terminal of the transistor M9 receives the second input signal INB, and the first terminal of the transistor M9 is connected to the second output node OT2, wherein the first input signal IN and the second input signal INB are inverted.
[0040] Optionally, the power supply voltage VSSD is, for example, a ground voltage or 0V.
[0041] The output circuit 220 is connected between the boost circuit 230 and the first and second output nodes OB2 and OT2, and is used to control the voltage of another output node to be equal to the power supply voltage AVDD_1 according to the voltage of the output node electrically connected to the power supply voltage VSSD.
[0042] The output circuit 220 includes transistors M3 and M4, wherein a first end of the transistor M3 is connected to the second pull-up node N2, a second end of the transistor M3 is connected to the second output node OT2, a control end of the transistor M3 is connected to the first output node OB2, a first end of the transistor M4 is connected to the first pull-up node N1, a second end of the transistor M4 is connected to the first output node OB2, and a control end of the transistor M4 is connected to the second output node OT2. The voltage value of the power supply voltage AVDD_1 is greater than the voltage value of the power supply voltage VSSD.
[0043] Optionally, the power supply voltage AVDD_1 is, for example, 8.5V.
[0044] The boost circuit 230 and the output circuit 220 are connected to the first pull-up node N1 and the second pull-up node N2, and are used to pull up the voltage of the pull-up node corresponding to the output node electrically connected to the power supply voltage VSSD to the power supply voltage AVDD_1 according to the voltage of the output node electrically connected to the power supply voltage VSSD. The first pull-up node N1 corresponds to the first output node OB2, and the second pull-up node N2 corresponds to the second output node OT2.
[0045] The boost circuit 230 includes a first pull-up unit composed of transistors M1 and M2 , and a second pull-up unit composed of transistors M13 and M14 .
[0046] Specifically, when the boost circuit 230 pulls up the corresponding pull-up node, the first pull-up unit no longer works on pulling up the node after the voltage of the pull-up node is pulled up to the first voltage AVDD_1-Vth (Vth represents the threshold voltage of the transistor M1 or the transistor M2), and then the second pull-up unit needs to continue to pull up the node to the power supply voltage AVDD_1.
[0047] Among them, the first ends of transistors M1-M2 and the first ends of transistors M13-M14 are connected to the power supply voltage AVDD_1, the second ends of transistors M1 and M13 are connected to the second pull-up node N2, the second ends of transistors M2 and M14 are connected to the first pull-up node N1, the control end of transistor M1 is connected to the second output node OT2, the control end of transistor M2 is connected to the first output node OB2, and the control ends of transistors M13 and transistor M14 are connected to the bias voltage VBP1.
[0048] Optionally, by properly setting the bias voltage VBP1 , the on-state voltage drop of the transistors M13 and M14 is about one hundred times the on-state voltage drop of the transistors M9 and M10 .
[0049] The inverter 240 is used to provide an output voltage at its output terminal OUT according to the voltage of the first output node OB2, wherein the output voltage is inversely proportional to the voltage of the first output node OB2.
[0050] The inverter 240 includes transistors M11 and M12 connected in sequence between the power supply voltage AVDD_2 and the power supply voltage VSSA, the control end of the transistor M11 is connected to the first output node OB2, the control end of the transistor M12 is connected to the first end of the transistor M8, and the common node of the transistors M11 and M12 serves as the output end OUT2 of the inverter 240 to provide an output voltage.
[0051] Optionally, the control terminal of the transistor M12 may also be connected to the first output node OB2.
[0052] Optionally, the power supply voltage AVDD_2 is, for example, 8.5V, and the power supply voltage VSSA is, for example, 0V or a ground voltage.
[0053] When the level converter 200 operates in a steady state, if the first input signal IN jumps to a high level, the second input signal INB jumps to a low level. At this time, the transistor M9 is turned off and the transistor M10 is turned on, so that the voltage of the first output node OB2 is pulled down, the transistors M2 and M3 are turned on, and the transistor M3 pulls up the voltage of the second output node OT2 to the power supply voltage AVDD_1. After the transistor M2 and the transistor M14 pull up the voltage of the first pull-up node N1, that is, the first end of the transistor M4, to the first voltage AVDD_1-Vth2 (Vth2 represents the threshold voltage of the transistor M2), the transistor M14 pulls up the voltage of the first pull-up node N1 again until the voltage of the first pull-up node N1 is equal to the power supply voltage AVDD_1.
[0054] If the first input signal IN jumps to a low level, the second input signal INB jumps to a high level. At this time, transistor M9 is turned on and transistor M10 is turned off, so that the voltage of the second output node OT2 is pulled down, transistors M1 and M4 are turned on, and transistor M4 pulls up the voltage of the first output node OB2 to the power supply voltage AVDD_1. After transistor M1 and transistor M13 pull up the voltage of the second pull-up node N2, that is, the first end of transistor M3, to the first voltage AVDD_1-Vth1 (Vth1 represents the threshold voltage of transistor M1), transistor M13 pulls up the voltage of the second pull-up node N2 again until the voltage of the second pull-up node N2 is equal to the power supply voltage AVDD_1.
[0055] Compared with the level converter 100, the level converter 200 provided in the embodiment of the utility model has a higher voltage value when the first output node OB is at a high level. In theory, the gate voltage of the transistor M11 can be equal to its source voltage, thereby completely turning off the transistor M11 to solve the problem of leakage of the inverter 240 when the first output node OB is at a high level.
[0056] It is understandable that, although the present invention only provides an embodiment in which the inverter 240 is connected to the first output node OB2, in actual applications, an inverter may also be connected to the second output node OT2 as needed, or only one inverter may be connected to the second output node OT2.
[0057] In another embodiment of the present invention, the level converter 200 may further include a protection circuit 250 .
[0058] The protection circuit 250 is connected between the input circuit 210 and the output circuit 220, and protects the level converter 200 by limiting the current flowing through the inverter 240 and controlling the voltage drop between the output circuit 220 and the input circuit 210, so as to prevent the input circuit 210 from being over-voltage or the inverter 240 from being over-current, thereby damaging the level converter 200.
[0059] Furthermore, the protection circuit 250 includes a voltage limiting unit composed of transistors M7 and M8 for limiting the voltage of the first terminals of the transistors M9 and M10, and a current limiting unit composed of transistors M5 and M6 for limiting the current of the transistors M11 and M12.
[0060] Among them, the transistor M5 and the transistor M7 are connected between the second output node OT2 and the first end of the transistor M9 in sequence, the transistor M6 and the transistor M8 are connected between the first output node OB2 and the first end of the transistor M10 in sequence, the control end of the transistor M5 is connected to its second end, the control end of the transistor M6 is connected to its second end, and the control ends of the transistors M7 and M8 are connected to the bias voltage VBN1.
[0061] The voltage drop between the first output node OB2 , the second output node OT2 and the input circuit 220 can be controlled by properly setting the bias voltage VBN1 .
[0062] Figure 3 Shows Figure 1 The level shifter shown with Figure 2 A simulation comparison of the level converter is shown.
[0063] See also Figure 3 When the first input signal IN jumps to a high level, the voltage of the first output node OB1 of the level converter 100 decreases to 2.09V, and the voltage of the output terminal OUT1 increases to 8.5V. At this time, the current of the leakage current I1 of the inverter 240 is 66.7uA. The voltage of the first output node OB2 of the level converter 200 decreases to 2.01V, and the voltage of the output terminal OUT2 increases to 8.5V. The current of the leakage current I2 of the inverter 240 is 2.68uA.
[0064] When the first input signal IN jumps to a low level, the voltage of the first output node OB1 of the voltage converter 100 increases to 7.95V, the voltage of the output terminal OUT1 decreases to 183uV, and the current of the leakage current I1 of the inverter 240 is 69.2uA. The voltage of the first output node OB2 of the level converter 200 increases to 8.5V, the voltage of the output terminal OUT2 decreases to 1.46uV, and the current of the leakage current I2 of the inverter 240 is 2.77uA.
[0065] In summary, compared with the level converter 100 , the leakage problem of the inverter 240 of the voltage converter 200 is significantly improved.
[0066] In addition, through Figure 3 It can be seen that the overall delay of the voltage converter 200 during level flipping is maintained within 40 ns, which meets the requirements of the driving circuit for the level converter.
[0067] Optionally, transistors M7-M10 and transistor M12 are NPN transistors, and transistors M1-M6 and transistor M11 are PNP transistors. The first end, the second end, and the control end of the NPN transistor are respectively the drain end, the source end, and the gate end, and the first end, the second end, and the control end of the PNP transistor are respectively the source end, the drain end, and the gate end.
[0068] Based on the level converter 200 provided in the embodiment of the utility model, the utility model also provides a display device, which includes a driving circuit and a display panel. The display panel includes a pixel array composed of a plurality of pixel units. The driving circuit is used to provide corresponding driving voltages to the plurality of pixel units according to a digital clock signal DIN[0:9].
[0069] Figure 4 A circuit diagram of a driving circuit according to an embodiment of the utility model is shown.
[0070] See also Figure 4 The driving circuit includes a shift register, a level converter, a digital-to-analog converter, and an operational amplifier used as a buffer. The digital clock signal DIN[0:9] is converted into an analog signal after passing through the shift register unit, the level converter, the digital-to-analog converter, and the operational amplifier to drive the display panel.
[0071] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that technicians in the relevant technical field can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.
Claims
1. A level converter, characterized in that: include: An input circuit for controlling one of the first output node and the second output node to be electrically connected to a first power supply voltage according to an inverted first input signal and a second input signal; an output circuit, configured to control a voltage of another output node to be equal to a second power supply voltage according to a voltage of an output node electrically connected to the first power supply voltage; a boost circuit connected to the output circuit at a first pull-up node and a second pull-up node, for pulling up a voltage of a pull-up node corresponding to an output node electrically connected to the first power supply voltage to the second power supply voltage, the first output node corresponding to the first pull-up node, and the second output node corresponding to the second pull-up node; at least one inverter, configured to invert the voltage of at least one output node to obtain an output voltage, Wherein, the boost circuit comprises: The first pull-up unit and the second pull-up unit, in the process of pulling up the corresponding pull-up node to the second power supply voltage, when the voltage of the corresponding pull-up node reaches the first voltage, the first pull-up unit no longer works on pulling up the node, and the second pull-up unit then pulls up the voltage of the node to the second power supply voltage.
2. The level converter according to claim 1, wherein: The level converter is configured such that when the first input signal jumps to a high level, the first output node is electrically connected to the first power supply voltage, and when the first input signal jumps to a low level, the second output node is electrically connected to the first power supply voltage, wherein the second power supply voltage is greater than the first power supply voltage.
3. The level converter according to claim 1, wherein: The first pulling unit comprises: a first transistor, having a first end connected to the second power supply voltage, a second end connected to the first pull-up node, and a control end connected to the first output node; A second transistor has a first end connected to the second power supply voltage, a second end connected to the second pull-up node, and a control end connected to the second output node.
4. The level converter according to claim 3, characterized in that: The second pulling unit comprises: a third transistor, a first end connected to the second power supply voltage, a second end connected to the first pull-up node, and a control end connected to a first bias voltage; A fourth transistor has a first end connected to the second power supply voltage, a second end connected to the second pull-up node, and a control end connected to the first bias voltage.
5. The level converter according to claim 4, characterized in that: The input circuit comprises: a fifth transistor, a control end connected to the first input signal, a first end connected to the first output node, and a second end connected to the first power supply voltage; a sixth transistor, a control end connected to the second input signal, a first end connected to the second output node, and a second end connected to the first power supply voltage, The output circuit comprises: a seventh transistor, a first end connected to the first pull-up node, a second end connected to the first output node, and a control end connected to the second output node; An eighth transistor, having a first end connected to the second pull-up node, a second end connected to the second output node, and a control end connected to the first output node.
6. The level converter according to claim 5, characterized in that: Also includes: The protection circuit is connected between the output circuit and the input circuit, and is used for limiting the current flowing through the inverter and controlling the voltage drop between the output circuit and the input circuit by setting a second bias voltage.
7. The level converter according to claim 6, characterized in that: The protection circuit comprises: a ninth transistor and a tenth transistor connected in sequence between the first output node and the first end of the fifth transistor, an eleventh transistor and a twelfth transistor connected in sequence between the second output node and the second end of the sixth transistor, The control end of the ninth transistor is connected to the second end thereof, the control end of the eleventh transistor is connected to the second end thereof, and the control ends of the tenth transistor and the twelfth transistor are connected to the second bias voltage.
8. The level converter according to claim 7, characterized in that: The on-state voltage drops of the third transistor and the fourth transistor are preset multiples of the on-state voltage drops of the fifth transistor and the sixth transistor.
9. A driving circuit, characterized in that: The invention comprises a shift register, a level converter according to any one of claims 1 to 8, a digital-to-analog converter and an operational amplifier.
10. A display device, characterized in that: include: A display panel including a pixel array composed of a plurality of pixel units; The driving circuit as claimed in claim 9, wherein the driving circuit provides corresponding driving voltages to the plurality of pixel units according to a digital clock signal.