Signal amplification circuit and chip

Abstract

The embodiment of the utility model provides a signal amplification circuit and a chip. The signal amplifying circuit comprises an amplifying unit and a gain adjusting unit, the signal input end of the signal amplification circuit is connected with the amplification unit, and the amplification unit is connected with the signal output end of the gain adjustment unit and the signal output end of the signal amplification circuit; the gain adjusting unit is connected with at least two paths of driving voltage; wherein the voltage values of the driving voltages are different; the gain adjusting unit is used for transmitting one of the driving voltages to the control end of the amplifying unit and adjusting the amplification factor of the amplifying unit by switching the driving voltages transmitted to the control end of the amplifying unit. According to the embodiment of the invention, the circuit area of the signal amplification circuit is not obviously increased while the amplification factor is adjustable, so that the design flexibility of the signal amplification circuit is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of signal amplification, and in particular to a signal amplification circuit and a chip. Background Art

[0002] Low Noise Amplifier (LNA) is a common signal amplifier. In the design of signal amplification circuit, a current mirror is usually used to copy the reference current and provide bias to the LNA. The LNA static current is regulated by controlling the number of switch tubes in the current mirror to control the amplification factor of the LNA. However, the current mirror occupies a large area in the circuit or chip. In order to achieve the adjustable LNA amplification factor, the number of switch tubes in the current mirror needs to be increased, so that the current mirror occupies a larger area and reduces the flexibility of the signal amplification circuit design. Utility Model Content

[0003] In view of this, an embodiment of the present application provides a signal amplification circuit to at least partially solve the above-mentioned problem.

[0004] According to a first aspect of an embodiment of the present application, a signal amplifying circuit is provided, comprising: an amplifying unit and a gain adjusting unit; the signal input end of the signal amplifying circuit is connected to the amplifying unit, and the amplifying unit is respectively connected to the gain adjusting unit and the signal output end of the signal amplifying circuit; and the gain adjusting unit is connected to at least two driving voltages; wherein the voltage values ​​of the driving voltages are different; the gain adjusting unit is used to transmit one of the driving voltages to the control end of the amplifying unit, and adjust the amplification factor of the amplifying unit by switching the driving voltage transmitted to the control end of the amplifying unit.

[0005] Optionally, the amplification unit includes a common-source and common-gate amplification unit; the gate of the common-source tube of the common-source and common-gate amplification unit is connected to the signal input terminal, the source of the common-source tube is grounded, and the drain of the common-source tube is connected to the source of the common-gate tube of the common-source and common-gate amplification unit; the gate of the common-gate tube is connected to the gain adjustment unit as the control terminal of the amplification unit, and the drain of the common-gate tube is connected to the signal output terminal; the gain adjustment unit includes at least two voltage input terminals and an adjustment switch; each of the voltage input terminals is connected to one of the driving voltages, and each of the voltage input terminals is connected to the gate of the common-gate tube through the adjustment switch, and the adjustment switch is used to connect the gate of the common-gate tube to one of the at least two voltage input terminals; wherein the voltage values ​​of the driving voltages connected to different voltage input terminals are different.

[0006] Optionally, in any embodiment of the present application, the drain of the common-gate tube is also connected to a power supply voltage, and a first voltage input terminal of at least two of the voltage input terminals is connected to the power supply voltage.

[0007] Optionally, in any embodiment of the present application, the signal amplifying circuit includes an input matching circuit, which is connected to the signal input end and is used for impedance matching of the signal input end; and / or the signal amplifying circuit includes an output matching circuit, which is connected to the signal output end and is used for impedance matching of the signal output end.

[0008] Optionally, in any embodiment of the present application, the input matching circuit includes a second inductor and a second capacitor; the first end of the second inductor is connected to the signal input end, and the second end of the second inductor is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the common source tube.

[0009] Optionally, in any embodiment of the present application, the output matching circuit includes a first inductor and a first capacitor; the first end of the first inductor is connected to the power supply voltage, and the second end of the first inductor is respectively connected to the drain of the common-gate tube and the first end of the first capacitor; the second end of the first capacitor is connected to the signal output end.

[0010] Optionally, in any embodiment of the present application, the signal amplification circuit also includes a bias module, the bias module includes a bias switch tube and a current source; the drain of the bias switch tube is respectively connected to the current source and the gate of the bias switch tube, the source of the bias switch tube is grounded, and the gate of the bias switch tube is connected to the gate of the common source tube.

[0011] Optionally, in any embodiment of the present application, the signal amplification circuit also includes a first noise reduction module connected to the common source tube; the first noise reduction module includes a first resistor; the first end of the first resistor is respectively connected to the second end of the second capacitor and the gate of the common source tube, and the second end of the first resistor is connected to the gate of the bias switch tube; and / or, the first noise reduction module includes a third inductor, the first end of the third inductor is connected to the source of the common source tube, and the second end of the third inductor is grounded.

[0012] Optionally, in any embodiment of the present application, the signal amplification circuit also includes a second noise reduction module connected to the common-gate tube, the second noise reduction module includes a second resistor and a third capacitor; the first end of the second resistor is connected to the adjustment switch, the second end of the second resistor is respectively connected to the first end of the third capacitor and the gate of the common-gate tube, and the second end of the third capacitor is grounded.

[0013] According to a second aspect of the embodiments of the present application, a chip is provided, comprising the signal amplification circuit described in the above embodiments.

[0014] In the embodiment of the present application, the signal inputted from the signal input terminal can be amplified by the amplifier unit. By setting the gain adjustment unit to be connected to the amplifier unit, and the gain adjustment unit to be connected to at least two driving voltages, the gain adjustment unit can be used to transmit one of the driving voltages connected thereto to the control terminal of the amplifier unit, and the amplification factor of the amplifier unit can be adjusted by switching the driving voltage transmitted to the control terminal of the amplifier unit. Since the gain adjustment unit has a relatively small requirement for the occupied circuit area, a small-sized switching element can be used, so that the area cost increased by using the gain adjustment unit can be ignored. Therefore, the embodiment of the present application can realize the adjustable amplification factor without significantly increasing the circuit area of ​​the signal amplifier circuit, thereby improving the flexibility of the signal amplifier circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0016] Figure 1 A schematic diagram of the structure of a signal amplification circuit provided in an optional embodiment of the present application;

[0017] Figure 2 A schematic diagram of the structure of another signal amplification circuit provided in an optional embodiment of the present application.

[0018] Figure 3 A schematic diagram of the structure of another signal amplification circuit provided for an optional embodiment of the present application.

[0019] Reference numerals:

[0020] 100, signal amplification circuit; 101, amplification unit; 110, common source and common gate amplification unit; 120, gain adjustment unit; 121, voltage input terminal; 1211, first voltage input terminal; 1212, second voltage input terminal; 1213, third voltage input terminal; 1214, fourth voltage input terminal; 122, adjustment switch; 130, current source;

[0021] SIN, signal input terminal; SOUT, signal output terminal; VDD, power supply voltage;

[0022] M1, common source tube; M2, common gate tube; M3, bias switch tube;

[0023] L1, first inductor; L2, second inductor; L3, third inductor;

[0024] C1, first capacitor; C2, second capacitor; C3, third capacitor;

[0025] R1, first resistor; R2, second resistor. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0027] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "an" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0028] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0029] According to a first aspect of an embodiment of the present application, a signal amplification circuit is provided to solve the above-mentioned problem.

[0030] Figure 1 FIG. 1 is a schematic diagram showing a structure of a signal amplifying circuit 100 applicable to an embodiment of the present application. Figure 1 As shown, the signal amplifying circuit 100 includes: an amplifying unit 101 and a gain adjusting unit 120 .

[0031] The signal input terminal SIN of the signal amplifying circuit is connected to the amplifying unit 101, and the amplifying unit 101 is respectively connected to the gain adjusting unit 120 and the signal output terminal SOUT of the signal amplifying circuit; and the gain adjusting unit 120 is connected to at least two driving voltages vg; wherein the voltage values ​​of each driving voltage vg are different.

[0032] The amplifier unit 101 may be an amplifier circuit composed of one or more switch tubes, such as a common-source common-gate amplifier circuit.

[0033] The gain adjustment unit 120 is used to transmit one of the driving voltages vg connected thereto to the control end of the amplifying unit 101, and adjust the amplification factor of the amplifying unit 101 by switching the driving voltage vg transmitted to the control end of the amplifying unit 101. The gain adjustment unit 120 can be made of a simple switch element, such as a single-pole double-throw switch or a single-pole multi-throw switch, which has a small requirement for occupying a circuit area.

[0034] In the embodiment of the present application, the signal inputted by the signal input terminal SIN can be amplified and outputted by the amplifier unit 101. By setting the gain adjustment unit 120 to be connected to the amplifier unit 101, and the gain adjustment unit 120 to be connected to at least two driving voltages vg, the gain adjustment unit 120 can be used to transmit one of the driving voltages vg connected thereto to the control terminal of the amplifier unit 101, and by switching the driving voltage vg transmitted to the control terminal of the amplifier unit 101, the amplification factor of the amplifier unit 101 can be adjusted. Since the gain adjustment unit 120 has a small requirement for the occupied circuit area, a small-sized switching element can be used, so that the area cost increased by using the gain adjustment unit can be ignored, so the embodiment of the present application can realize the adjustable amplification factor while not significantly increasing the circuit area of ​​the signal amplifier circuit 100, thereby improving the flexibility of the design of the signal amplifier circuit 100.

[0035] like Figure 2 As shown, in some optional embodiments, the amplification unit includes a common-source and common-gate amplification unit 110 .

[0036] The common-source and common-gate amplifier unit 110 includes a common-gate transistor M2 and a common-source transistor M1. The gate of the common-source transistor M1 is connected to the signal input terminal SIN, the source of the common-source transistor M1 is grounded, and the drain of the common-source transistor M1 is connected to the source of the common-gate transistor M2 of the common-source and common-gate amplifier unit 110. The gate of the common-gate transistor M2 is connected to the gain adjustment unit 120 as the control terminal of the amplifier unit, and the drain of the common-gate transistor M2 is connected to the signal output terminal SOUT. The signal input terminal SIN is used to receive the signal to be amplified, and the signal output terminal SOUT is used to output the amplified signal.

[0037] The gain adjustment unit 120 includes at least two voltage input terminals 121 and an adjustment switch 122; each voltage input terminal 121 is connected to a driving voltage vg, and each voltage input terminal 121 is connected to the gate of the common gate tube M2 through the adjustment switch 122, and the adjustment switch 122 is used to connect the gate of the common gate tube M2 to one of the at least two voltage input terminals 121; wherein different voltage input terminals 121 are connected to different voltage values ​​of the driving voltage vg. Figure 2 As shown, at least two voltage input terminals 121 may include a first voltage input terminal 1211 and a second voltage input terminal 1212, and the first voltage input terminal 1211 may be connected to the power supply voltage VDD, and the power supply voltage VDD is used as a driving voltage vg. The second voltage input terminal 1212 may be connected to the driving voltage vg2, and the driving voltage vg2 is used as another driving voltage vg. The voltage values ​​of the driving voltage vg2 and the power supply voltage VDD can be set to any voltage value that makes the gate tube M2 in the saturation region, and the voltage value of the driving voltage vg2 should be different from the power supply voltage VDD. The embodiment of the present application does not specifically limit the value of the driving voltage vg connected to different voltage input terminals 121, as long as the common source and common gate amplifier unit 110 can work normally. The regulating switch 122 may also be other suitable switches, all within the protection scope of the embodiment of the present application. The regulating switch 122 may adopt a small-sized switch with an area smaller than the switch tube, and the area cost increased by setting the regulating switch 122 can be ignored.

[0038] In the embodiment of the present application, the amplification unit may include a common-source common-gate amplification unit 110. The gate of the common-source transistor M1 of the common-source common-gate amplification unit 110 is connected to the signal input terminal SIN, the source is grounded, and the drain is connected to the source of the common-gate transistor M2 of the common-source common-gate amplification unit 110. The gate of the common-gate transistor M2 is connected to the gain adjustment unit 120 as the control terminal of the amplification unit, and the drain is connected to the signal output terminal SOUT. The gain adjustment unit 120 includes at least two voltage input terminals 121 and an adjustment switch 122, each voltage input terminal 121 is connected to a driving voltage vg, and each voltage input terminal 121 is connected to the gate of the common-gate transistor M2 through the adjustment switch 122, and the adjustment switch 122 is used to connect the gate of the common-gate transistor M2 to one of the at least two voltage input terminals 121, and the voltage values ​​of the driving voltage vg connected to different voltage input terminals 121 are different. The gate of the common-gate tube M2 can be connected to a driving voltage vg by adjusting the switch 122 to switch the gain of the common-source common-gate amplifier unit 110. Since the adjustment switch 122 can adopt a small-sized switch whose area is smaller than that of the switch tube, the increased area cost can be ignored. The embodiment of the present application can achieve adjustable gain without significantly increasing the area occupied by the signal amplifier circuit 100, thereby improving the flexibility of the design of the signal amplifier circuit 100.

[0039] In some optional embodiments, the drain of the common gate transistor M2 is also connected to the power supply voltage VDD, and the first voltage input terminal 1211 of the at least two voltage input terminals 121 is connected to the power supply voltage VDD. It should be understood that the number of the first voltage input terminal 1211 of the at least two voltage input terminals 121 is one.

[0040] For example, Figure 2 As shown, the gain adjustment unit 120 may be connected to a first voltage input terminal 1211 and a second voltage input terminal 1212, wherein the first voltage input terminal 1211 is connected to the power supply voltage VDD, and the second voltage input terminal 1212 is connected to the driving voltage vg2. The voltage value of the driving voltage vg2 is different from the power supply voltage VDD, that is, the driving voltage vg can be the power supply voltage VDD and the driving voltage vg2. Alternatively, Figure 3 As shown, the gain adjustment unit 120 may be connected to a first voltage input terminal 1211, a second voltage input terminal 1212, a third voltage input terminal 1213 and a fourth voltage input terminal 1214, wherein the first voltage input terminal 1211 is connected to the power supply voltage VDD, the second voltage input terminal 1212 is connected to the driving voltage vg3, the third voltage input terminal 1213 is connected to the driving voltage vg4, and the fourth voltage input terminal 1214 is connected to the driving voltage vg5. The voltage values ​​of the driving voltages vg3, vg4, vg5 and the power supply voltage VDD are different from each other, that is, the driving voltage vg can be the driving voltages vg3, vg4, vg5 and the power supply voltage VDD. It should be understood that in order to normally drive the common gate tube M2 to turn on, the driving voltages vg2, vg3, vg4, vg5 and the power supply voltage VDD can be set to voltage values ​​that make the gate tube M2 in the saturation region.

[0041] In the embodiment of the present application, by connecting the first voltage input terminal 1211 of the at least two voltage input terminals 121 to the power supply voltage VDD, the power supply voltage VDD can be used to provide a voltage for the gate of the common gate tube M2, thereby reducing the number of voltage sources by reusing the power supply voltage VDD and reducing the cost of the signal amplification circuit 100.

[0042] In some optional embodiments, the signal amplifying circuit 100 may include an input matching circuit connected to the signal input terminal SIN for impedance matching of the signal input terminal SIN. And / or, the signal amplifying circuit 100 may include an output matching circuit connected to the signal output terminal SOUT for impedance matching of the signal output terminal SOUT.

[0043] In the embodiment of the present application, the signal amplifying circuit 100 may include an input matching circuit connected to the signal input terminal SIN, and the impedance matching of the signal input terminal SIN can be achieved through the input matching circuit, thereby improving the signal transmission power of the signal amplifying circuit 100 and reducing the reflection of the signal by the signal amplifying circuit 100. In addition, the signal amplifying circuit 100 may also include an output matching circuit connected to the signal output terminal SOUT, and the impedance matching of the signal output terminal SOUT can be achieved through the output matching circuit, thereby improving the signal transmission power of the signal amplifying circuit 100 and reducing the reflection of the signal by the signal amplifying circuit 100.

[0044] As a feasible implementation method, Figure 2 and Figure 3 As shown, the input matching circuit includes a second inductor L2 and a second capacitor C2. The first end of the second inductor L2 is connected to the signal input terminal SIN, the second end of the second inductor L2 is connected to the first end of the second capacitor C2; and the second end of the second capacitor C2 is connected to the gate of the common source transistor M1.

[0045] In the embodiment of the present application, the input matching circuit includes a second inductor L2 and a second capacitor C2. By connecting the first end of the second inductor L2 to the signal input end SIN, and the second end of the second inductor L2 to the first end of the second capacitor C2; the second end of the second capacitor C2 is connected to the gate of the common source transistor M1. The simple combination of the second inductor L2 and the second capacitor C2 can be used to achieve impedance matching of the signal output end SOUT, which is beneficial to improving the applicability of the signal amplification circuit 100.

[0046] As a feasible implementation method, Figure 2 and Figure 3 As shown, the output matching circuit includes a first inductor L1 and a first capacitor C1. The first end of the first inductor L1 is connected to the power supply voltage VDD, the second end of the first inductor L1 is connected to the drain of the common gate tube M2 and the first end of the first capacitor C1 respectively, and the second end of the first capacitor C1 is connected to the signal output terminal SOUT.

[0047] In the embodiment of the present application, the output matching circuit includes a first inductor L1 and a first capacitor C1. By connecting the first end of the first inductor L1 to the power supply voltage VDD, the second end of the first inductor L1 is respectively connected to the drain of the common gate tube M2 and the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the signal output terminal SOUT, the impedance matching of the signal output terminal SOUT can be achieved by using a simple combination of the first inductor L1 and the first capacitor C1, which is beneficial to improving the applicability of the signal amplification circuit 100.

[0048] In some optional embodiments, the signal amplifying circuit 100 further includes a bias module, and the bias module includes a bias switch tube M3 and a current source 130. Figure 2 and Figure 3 As shown, the drain of the bias switch tube M3 is connected to the current source 130 and the gate of the bias switch tube M3 respectively, the source of the bias switch tube M3 is grounded, and the gate of the bias switch tube M3 is connected to the gate of the common source tube M1. The current source 130 can be connected to the power supply voltage VDD to continuously provide a stable current using the power supply voltage VDD.

[0049] As a feasible implementation, the bias module may include a plurality of bias subunits including bias switch tubes M3 and current sources 130. In each bias subunit, the drain of the bias switch tube M3 is used to be connected to the current source 130 and the gate of the bias switch tube M3, the source of the bias switch tube M3 is grounded, and the gate of the bias switch tube M3 is used to be connected to the gate of the common source tube M1. By controlling the number of bias subunits connected to the gate of the common source tube M1, the magnitude of the current passing through the common source and common gate amplifier unit 110 can be controlled to control the amplification factor of the signal amplifier circuit 100, thereby improving the flexibility of controlling the amplification factor of the signal amplifier circuit 100.

[0050] In the embodiment of the present application, the signal amplifying circuit 100 also includes a bias module, which includes a bias switch tube M3 and a current source 130. The drain of the bias switch tube M3 is respectively connected to the current source 130 and the gate of the bias switch tube M3, the source of the bias switch tube M3 is grounded, and the gate of the bias switch tube M3 is connected to the gate of the common source tube M1, so that the bias module can be used to provide a bias for the gate of the common source tube M1 to drive the common source tube M1, thereby ensuring that the signal amplifying circuit 100 can work normally.

[0051] In some optional embodiments, the signal amplifying circuit 100 further includes a first noise reduction module connected to the common source transistor M1 .

[0052] like Figure 2 and Figure 3 As shown, the first noise reduction module includes a first resistor R1; the first end of the first resistor R1 is respectively connected to the second end of the second capacitor C2 and the gate of the common source tube M1, and the second end of the first resistor R1 is connected to the gate of the bias switch tube M3. And / or, the first noise reduction module includes a third inductor L3, the first end of the third inductor L3 is connected to the source of the common source tube M1, and the second end of the third inductor L3 is grounded.

[0053] In the embodiment of the present application, the signal amplification circuit 100 further includes a first noise reduction module connected to the common source tube M1, and the first noise reduction module may include a first resistor R1 and / or a third inductor L3. By connecting the first end of the first resistor R1 to the second end of the second capacitor C2 and the gate of the common source tube M1 respectively, and connecting the second end of the first resistor R1 to the gate of the bias switch tube M3, the first resistor R1 can be used to denoise the signal output by the second capacitor C2. By including the third inductor L3 in the first noise reduction module, the first end of the third inductor L3 is connected to the source of the common source tube M1, and the second end of the third inductor L3 is grounded, the third inductor L3 can be used to denoise the signal passing through the common source tube M1, thereby improving the signal-to-noise ratio of the signal amplification circuit 100.

[0054] In some optional embodiments, the signal amplifying circuit 100 further includes a second noise reduction module connected to the common gate transistor M2. Figure 2 and Figure 3 As shown, the second noise reduction module includes a second resistor R2 and a third capacitor C3, the first end of the second resistor R2 is connected to the adjustment switch 122, the second end of the second resistor R2 is respectively connected to the first end of the third capacitor C3 and the gate of the common gate tube M2, and the second end of the third capacitor C3 is grounded.

[0055] In the embodiment of the present application, the signal amplification circuit 100 may further include a second noise reduction module, which may include a second resistor R2 and a third capacitor C3. By connecting the first end of the second resistor R2 and the adjustment switch 122, the second end of the second resistor R2 is respectively connected to the first end of the third capacitor C3 and the gate of the common gate tube M2, and the second end of the third capacitor C3 is grounded, the second resistor R2 and the third capacitor C3 can be used to denoise the voltage output by the adjustment switch 122, thereby reducing the influence of the noise in the voltage on the signal amplification circuit 100.

[0056] According to a second aspect of the embodiments of the present application, a chip is provided. The switch chip may include the signal amplifying circuit 100 provided in any embodiment of the first aspect above.

[0057] The chip provided in the embodiment of the present application and the embodiment of the aforementioned signal amplifying circuit 100 are based on the same inventive concept and can achieve the same effect. The specific implementation process can refer to the description in the embodiment of the aforementioned signal amplifying circuit 100 and will not be repeated here.

[0058] According to an embodiment of the present application, an electronic device is also provided, which may include a chip provided in the embodiment of the second aspect above.

[0059] The electronic device provided in the embodiment of the present application is based on the same inventive concept as the embodiment of the aforementioned chip and signal amplification circuit 100 and can achieve the same effect. The specific implementation process can be found in the description in the aforementioned embodiment and will not be repeated here.

[0060] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0061] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA)). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., a random access memory (RAM), a read-only memory (ROM), a flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a dedicated computer for executing the method shown here.

[0062] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0063] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.

Claims

1. A signal amplification circuit, characterized in that: include: an amplifying unit and a gain adjusting unit; The signal input end of the signal amplifying circuit is connected to the amplifying unit, and the amplifying unit is respectively connected to the gain adjusting unit and the signal output end of the signal amplifying circuit; and the gain adjusting unit is connected to at least two driving voltages; wherein the voltage values ​​of the driving voltages are different; The gain adjustment unit is used to transmit one of the driving voltages to the control end of the amplifying unit, and adjust the amplification factor of the amplifying unit by switching the driving voltage transmitted to the control end of the amplifying unit.

2. The signal amplifying circuit according to claim 1, characterized in that: The amplification unit comprises a common-source and common-gate amplification unit; The gate of the common source tube of the common source and common gate amplification unit is connected to the signal input terminal, the source of the common source tube is grounded, and the drain of the common source tube is connected to the source of the common gate tube of the common source and common gate amplification unit; The gate of the common-gate tube is connected to the gain adjustment unit as the control end of the amplifying unit, and the drain of the common-gate tube is connected to the signal output end; The gain adjustment unit includes at least two voltage input terminals and an adjustment switch; each of the voltage input terminals is connected to one of the driving voltages, and each of the voltage input terminals is connected to the gate of the common-gate tube through the adjustment switch, and the adjustment switch is used to connect the gate of the common-gate tube to one of at least two of the voltage input terminals; wherein the voltage values ​​of the driving voltages connected to different voltage input terminals are different.

3. The signal amplifying circuit according to claim 2, characterized in that: The drain of the common-gate tube is also connected to a power supply voltage, and a first voltage input terminal of at least two voltage input terminals is connected to the power supply voltage.

4. The signal amplifying circuit according to claim 2, characterized in that: The signal amplifying circuit comprises an input matching circuit, which is connected to the signal input terminal and is used for impedance matching of the signal input terminal; and / or, The signal amplifying circuit comprises an output matching circuit, and the output matching circuit is connected to the signal output end and is used for impedance matching of the signal output end.

5. The signal amplifying circuit according to claim 4, characterized in that: The input matching circuit includes a second inductor and a second capacitor; The first end of the second inductor is connected to the signal input end, the second end of the second inductor is connected to the first end of the second capacitor; and the second end of the second capacitor is connected to the gate of the common source transistor.

6. The signal amplifying circuit according to claim 4, characterized in that: The output matching circuit includes a first inductor and a first capacitor; The first end of the first inductor is connected to the power supply voltage, the second end of the first inductor is respectively connected to the drain of the common gate tube and the first end of the first capacitor; the second end of the first capacitor is connected to the signal output end.

7. The signal amplifying circuit according to any one of claims 2 to 6, characterized in that: The signal amplification circuit further includes a bias module, and the bias module includes a bias switch tube and a current source; The drain of the bias switch tube is connected to the current source and the gate of the bias switch tube respectively, the source of the bias switch tube is grounded, and the gate of the bias switch tube is connected to the gate of the common source tube.

8. The signal amplifying circuit according to claim 5, characterized in that: The signal amplification circuit further includes a bias module, and the bias module includes a bias switch tube and a current source; The drain of the bias switch tube is connected to the current source and the gate of the bias switch tube respectively, the source of the bias switch tube is grounded, and the gate of the bias switch tube is connected to the gate of the common source tube; The signal amplification circuit further includes a first noise reduction module connected to the common source transistor; The first noise reduction module includes a first resistor; the first end of the first resistor is respectively connected to the second end of the second capacitor and the gate of the common source tube, and the second end of the first resistor is connected to the gate of the bias switch tube; and / or, the first noise reduction module includes a third inductor, the first end of the third inductor is connected to the source of the common source tube, and the second end of the third inductor is grounded.

9. The signal amplifying circuit according to claim 7, characterized in that: The signal amplification circuit further includes a second noise reduction module connected to the common-gate tube, and the second noise reduction module includes a second resistor and a third capacitor; The first end of the second resistor is connected to the regulating switch, the second end of the second resistor is respectively connected to the first end of the third capacitor and the gate of the common-gate tube, and the second end of the third capacitor is grounded.

10. A chip, characterized in that: The method comprises at least one signal amplifying circuit according to any one of claims 1 to 9.

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