Silicon wafer caching mechanism

Abstract

The utility model discloses a silicon wafer temporary storage mechanism, which comprises a lifting module sliding table, a connecting plate and mounting frames, the connecting plate is horizontally hung on the lifting module sliding table, the two sides of the connecting plate are respectively and vertically hung with one mounting frame, a plurality of pin holes which are horizontally aligned layer by layer are respectively arranged on one opposite side surfaces of the mounting frames from top to bottom, and the pin holes are arranged on the lifting module sliding table. And a positioning pin is inserted into the pin hole. Through the mode, according to the silicon wafer caching mechanism provided by the utility model, the integrally-formed positioning bases are arranged on the positioning pins to accurately control the extension size, the layer-by-layer arrangement of the positioning bases is adopted to accurately control the layer-by-layer spacing, and the lower connecting pieces are adopted as references to realize frame correction through the waist-shaped holes; therefore, the cache space is multiplied, and excellent stability and reliability can be kept.

Description

Technical Field

[0001] The utility model relates to the field of photovoltaic silicon wafer production equipment, in particular to a silicon wafer buffer mechanism. Background Art

[0002] In the process of photovoltaic silicon wafer automated production, if the mechanism or equipment at the front end of the transmission fails or is suspended for some reason, the equipment and mechanism at the back end of the transmission cannot stop running immediately. Therefore, it is necessary to place a silicon wafer buffer mechanism during the silicon wafer transmission process.

[0003] With the development of photovoltaic technology, the production rhythm is getting faster and faster, and the requirements for cost reduction and efficiency improvement are getting higher and higher. The original 30-layer or 50-layer cache mechanism cannot meet the needs. Due to the different storage quantities of cache and carrier, it cannot adapt to the throughput requirements of the 100-layer basket carrier, which will still cause equipment downtime. In addition, the original ceramic positioning pins are expensive, and the original toothed positioning plate silicon wafers are easily damaged and left residues. Utility Model Content

[0004] The main technical problem solved by the utility model is to provide a silicon wafer cache mechanism, in which an integrally formed positioning base is arranged on the positioning pin to accurately control the elongation size, and the layer height spacing is accurately controlled by arranging the positioning base layer by layer. The frame correction is achieved through the waist-shaped holes based on the lower connecting parts, thereby doubling the cache space and maintaining excellent stability and reliability.

[0005] In order to solve the above technical problems, a technical solution adopted by the utility model is: to provide a silicon wafer cache mechanism, including a lifting module slide, a connecting plate, and a mounting frame, wherein a connecting plate is horizontally mounted on the lifting module slide, and a mounting frame is vertically suspended on each side of the connecting plate, and a plurality of pin holes horizontally aligned layer by layer are opened on opposite sides of the mounting frames from top to bottom, and positioning pins are inserted in the pin holes.

[0006] In a preferred embodiment of the present invention, at least two rows of pin holes are provided on each of the mounting frames.

[0007] In a preferred embodiment of the present utility model, the positioning pin is composed of an embedded section inserted in the pin hole and a supporting section extending out of the pin hole.

[0008] In a preferred embodiment of the present invention, the positioning pin is provided with an integrally formed positioning base at the junction of the embedded section and the supporting section, and the positioning base is abutted against the surface of the mounting frame.

[0009] In a preferred embodiment of the present invention, a set screw is further provided on the installation frame, and the set screw is vertically locked to the embedded section of the positioning pin.

[0010] In a preferred embodiment of the utility model, the connecting plate is provided with two groups of waist-shaped holes parallel to the positioning pins, a mounting frame is matched and connected to one group of waist-shaped holes by a plurality of bolts, and lower connecting pieces are provided at the lower ends of the two mounting frames.

[0011] The beneficial effects of the utility model are as follows: a silicon wafer cache mechanism provided by the utility model has an integrally formed positioning base on the positioning pin to accurately control the elongation size, and the layer height spacing is accurately controlled by arranging the positioning base layer by layer, and the frame correction is achieved through the waist-shaped holes based on the lower connecting parts, thereby doubling the cache space and maintaining excellent stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0013] Figure 1 This is an overall structural diagram of a silicon chip cache mechanism of the utility model;

[0014] Figure 2 This is a waist-shaped hole structure diagram of a silicon wafer buffer mechanism of the utility model;

[0015] Figure 3 The utility model discloses a positioning pin structure diagram of a silicon chip buffer mechanism. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] like Figure 1-3 As shown, the embodiment of the utility model includes:

[0018] A silicon wafer cache mechanism comprises a lifting module slide 1, a connecting plate 2, and a mounting frame 3. The lifting module slide 1 is horizontally mounted with a connecting plate 2, and a mounting frame 3 is vertically suspended on each side of the connecting plate 2. The opposite side of the mounting frames 3 is provided with a plurality of pin holes 4 horizontally aligned layer by layer from top to bottom, and positioning pins 5 are inserted into the pin holes 4.

[0019] Each of the mounting frames 3 is provided with at least two rows of pin holes 4. The mounting frames 3 need to be finely processed to ensure that the spacing between any positioning pins 5 is within the tolerance range. The positioning pins 5 of the utility model can be replaced by injection molded parts instead of ceramics to reduce material costs. In this solution, four positioning pins 5 on the same horizontal plane jointly support a silicon wafer 100, which is a layer.

[0020] Furthermore, the positioning pin 5 is composed of an embedded section 51 inserted into the pin hole 4 and a supporting section 52 extending out of the pin hole 4 .

[0021] Furthermore, the positioning pin 5 is provided with an integrally formed positioning base 53 at the connection point between the embedded section 51 and the supporting section 52, and the positioning base 53 is abutted against the surface of the mounting frame 3. The utility model adds a positioning base 53 to the positioning pin 5, and the integral forming reduces the processing cost.

[0022] Furthermore, the mounting frame 3 is also provided with a set screw 6, which is vertically locked to the embedded section 51 of the positioning pin 5. The positioning pin 5 and the mounting frame 3 have a tolerance match, and the positioning pin 5 is placed in the pin hole 4 and fixed by the set screw 6 on the side.

[0023] Furthermore, the connecting plate 2 is provided with two groups of waist-shaped holes 7 parallel to the positioning pins 5, and a piece of mounting frame 3 is matched and connected with a group of waist-shaped holes 7 by a plurality of bolts, and a lower connecting piece 8 is provided at the lower ends of the two mounting frames 3. The waist-shaped holes can be adjusted in front and back positions according to the size of the silicon wafer 100.

[0024] The original 30-layer or 50-layer cache mechanism cannot meet the needs. Due to the different storage quantities of cache and carriers, it cannot adapt to the throughput requirements of the 100-layer flower basket carrier, which will still cause equipment downtime.

[0025] When the silicon wafer 100 needs to be introduced into the basket, if the upstream mechanism stops due to a fault, the silicon wafer 100 buffer mechanism of this product will take over the transmission of the upstream silicon wafer 100 and continue to introduce the silicon wafer 100 into the basket. As shown in the figure, the four positioning pins 5 of each layer form a buffer space for the silicon wafer 100. If the capacity of the buffer space in the silicon wafer 100 buffer mechanism of this product is less than the capacity of the basket, it will still cause the downstream equipment of the basket to stop.

[0026] In order to solve this problem, the cache space capacity constructed by the positioning pins 5 designed in this product should be larger than the flower basket capacity, at least reaching 100 layers, and can cache 100 silicon wafers 100, which can better meet actual production needs.

[0027] In order to solve the structural problem of the mounting frame 3 caused by the expansion of the size of the positioning pins 5, the mounting frame 3 adopts a mesh-shaped structure, and the lower connecting member 8 is used to establish a reference spacing at the bottom of the mounting frame 3, and a waist-shaped hole 7 is provided at the position of the connecting plate 2, so that the storage space of each layer of silicon wafers 100 on the mounting frame 3 can be stable and controllable.

[0028] When the silicon wafers 100 need to be continuously exported from the basket, or when the downstream equipment is suspended due to a fault, the silicon wafer 100 cache mechanism of this product begins to receive the silicon wafers 100 output from the basket, and the lifting module slide 1 starts to rise from the original position, holding up a silicon wafer 100 each time it rises, until all the silicon wafers 100 in the basket carrier are cached. When the downstream equipment resumes operation or the basket is replaced, the cache begins to descend, and each time it descends, a silicon wafer 100 is placed on the silicon wafer 100 transmission device and transmitted to the next section.

[0029] In summary, the utility model provides a silicon wafer 100 cache mechanism, an integrally formed positioning base 53 is arranged on the positioning pin 5 to accurately control the elongation size, and the layer height spacing is accurately controlled by arranging the positioning base 53 layer by layer. The frame correction is achieved through the waist-shaped hole 7 based on the lower connecting piece 8, thereby doubling the cache space and maintaining excellent stability and reliability.

[0030] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A silicon chip cache mechanism, characterized in that: It includes a lifting module slide, a connecting plate, and a mounting frame. The lifting module slide is horizontally mounted with a connecting plate, and a mounting frame is vertically suspended on both sides of the connecting plate. The opposite side of the mounting frames is provided with a plurality of pin holes horizontally aligned layer by layer from top to bottom, and positioning pins are inserted in the pin holes.

2. The silicon chip cache mechanism according to claim 1, characterized in that: Each of the mounting frames is provided with at least two rows of pin holes.

3. The silicon chip cache mechanism according to claim 1, characterized in that: The positioning pin is composed of an embedded section inserted in the pin hole and a supporting section extending out of the pin hole.

4. The silicon chip cache mechanism according to claim 3, characterized in that: The positioning pin is provided with an integrally formed positioning base at the connection point between the embedded section and the supporting section, and the positioning base is abutted against the surface of the installation frame.

5. The silicon chip cache mechanism according to claim 3, characterized in that: The mounting frame is also provided with a set screw, which is vertically locked to the embedded section of the positioning pin.

6. The silicon chip buffer mechanism according to claim 1, characterized in that: The connecting plate is provided with two groups of waist-shaped holes parallel to the positioning pins, a mounting frame is matched and connected with one group of waist-shaped holes through a plurality of bolts, and lower connecting pieces are provided at the lower ends of the two mounting frames.

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