Data reading circuit and memory

Abstract

The utility model discloses a data reading circuit and a memory, and the data reading circuit comprises a first voltage sampling module which is used for accessing a first current and outputting a first voltage; the second voltage sampling module is used for accessing a second current and outputting a second voltage; the first input end of the comparison module is connected with the output end of the first voltage sampling module to receive the first voltage, the second input end of the comparison module is connected with the output end of the second voltage sampling module to receive the second voltage, and the output end of the comparison module is used for outputting a comparison result obtained according to the first voltage and the second voltage; wherein the first current is one of the reference current and the read current flowing through the bit line, and the second current is the other one of the reference current and the read current. According to the invention, the accuracy and reliability of data reading are improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data reading circuit and a memory. Background Art

[0002] Non-volatile memory devices, with their advantages of low cost, low power consumption, high reliability and fast access speed, have occupied an increasingly important position in the memory field and are widely used in the consumer electronics field.

[0003] For data reading of non-volatile memory, the read current is compared with the reference current through a sense amplifier (SA) to read the data of the selected storage cell. However, if the accuracy of SA is not high, there is a risk of data reading errors. Therefore, how to improve the reading accuracy and improve the accuracy of data reading from non-volatile memory is a technical problem that those skilled in the art need to solve urgently. Utility Model Content

[0004] The present application provides a data reading circuit and a memory, which can improve the reliability and accuracy of data reading of a non-volatile memory.

[0005] In a first aspect, the present application provides a data reading circuit, which is applied to a memory, wherein the memory includes a plurality of storage cells, each of which is connected to a bit line, and the data reading circuit includes:

[0006] A first voltage sampling module, used for receiving a first current and outputting a first voltage;

[0007] A second voltage sampling module, used for receiving a second current and outputting a second voltage;

[0008] a comparison module, wherein a first input terminal of the comparison module is connected to an output terminal of the first voltage sampling module to receive the first voltage, a second input terminal of the comparison module is connected to an output terminal of the second voltage sampling module to receive the second voltage, and an output terminal of the comparison module is used to output a comparison result obtained according to the first voltage and the second voltage;

[0009] The first current is one of a reference current and a read current flowing through the bit line, and the second current is the other of the reference current and the read current.

[0010] In some implementations, the comparison module includes: a first latch, and two ends of the first latch are respectively connected to the first voltage sampling module and the second voltage sampling module.

[0011] In some implementations, the data reading circuit further includes: a switch module and a compensation load;

[0012] The first end of the switch module is connected to the first input end of the comparison module, and the second end of the switch module is connected to the second input end of the comparison module;

[0013] The input end of the switch module is used to access the reference current, and the input end of the switch module is also connected to the compensation load.

[0014] In some implementations, the first voltage sampling module includes: a first sampling resistor and a first sampling switch, and the second voltage sampling module includes a second sampling resistor and a second sampling switch;

[0015] One end of the first sampling resistor is connected to the power supply voltage, the other end of the first sampling resistor is connected to the first end of the first sampling switch, and the other end of the first sampling resistor is also connected to the first current;

[0016] The second end of the first sampling switch is connected to the first input end of the comparison module, and the control end of the first sampling switch is used to receive a sampling control signal;

[0017] One end of the second sampling resistor is connected to the power supply voltage, the other end of the second sampling resistor is connected to the first end of the second sampling switch, and the other end of the second sampling resistor is also connected to the second current;

[0018] The second end of the second sampling switch is connected to the second input end of the comparison module, and the control end of the second sampling switch is used to receive the sampling control signal;

[0019] The sampling control signal is used to control the switching states of the first sampling switch and the second sampling switch.

[0020] In some implementations, the first voltage sampling module further includes a first current source, and the first voltage sampling module further includes a second current source;

[0021] One end of the first current source is connected to the power supply voltage, and the other end of the first current source is connected to the first end of the first sampling switch;

[0022] One end of the second current source is connected to the power supply voltage, and the other end of the second current source is connected to the first end of the second sampling switch.

[0023] In some embodiments, the first latch is composed of two mutually coupled inverters, a first end of the first latch is connected to a second end of the first sampling switch, and a second end of the first latch is connected to a second end of the second sampling switch.

[0024] In some implementations, the comparison module further includes: a second latch, a first inverter, a second inverter, and a gating switch;

[0025] The input end of the first inverter is connected to the first end of the first latch and the second end of the first sampling switch, and the output end of the first inverter is connected to the first end of the gating switch;

[0026] The input end of the second inverter is connected to the second end of the first latch and the second end of the second sampling switch, and the output end of the second inverter is connected to the second end of the gating switch;

[0027] The output terminal of the gate switch is connected to the input terminal of the second latch.

[0028] In some embodiments, the data reading circuit further includes a pre-charge module, and the pre-charge module includes a first pre-charge sub-module and a second pre-charge sub-module;

[0029] One end of the first pre-charging submodule and one end of the second pre-charging submodule are respectively connected to the power supply voltage;

[0030] The other end of the first pre-charging submodule is connected to the input end of the first voltage sampling module;

[0031] The other end of the second pre-charging submodule is connected to the input end of the second voltage sampling module.

[0032] In some embodiments, the data reading circuit further includes a first switch tube and a second switch tube; the switch module includes a first switch and a second switch;

[0033] The first end of the first switch tube is connected to the input end of the first voltage sampling module, and the second end of the first switch tube is used to access the first current;

[0034] The first end of the second switch tube is connected to the input end of the second voltage sampling module, and the second end of the second switch tube is used to access the second current;

[0035] One end of the first switch is connected to the second end of the first switch tube, and the other end of the first switch is connected to the compensation load and a reference current generator included in the peripheral circuit of the memory respectively;

[0036] One end of the second switch is connected to the second end of the second switch tube, and the other end of the second switch is connected to the compensation load and a reference current generator included in the peripheral circuit of the memory respectively.

[0037] In some embodiments, the switch module further includes a third switch, and two ends of the third switch are respectively connected to one end of the first switch and one end of the second switch.

[0038] In some embodiments, the compensation load includes any one or more of a compensation capacitor and an adjustable resistor.

[0039] In some embodiments, the memory is a NOR memory, and the NOR memory includes a plurality of storage units.

[0040] In some embodiments, the memory is a non-volatile memory device with a split floating gate, and the non-volatile memory device with a split floating gate includes a plurality of memory cell pairs, and the memory cell pairs include two memory cells, one of the two memory cells is connected to the first voltage sampling module, and the other of the two memory cells is connected to the second voltage sampling module.

[0041] In a second aspect, the present application further provides a memory, comprising a plurality of memory cells and a peripheral circuit, each of the memory cells being connected to a bit line, and the peripheral circuit comprising the data reading circuit described in the first aspect, wherein the data reading circuit is connected to the bit line.

[0042] In some embodiments of the present application, the data reading circuit and memory are applied to the memory, the memory includes a plurality of memory cells, each memory cell is connected to a bit line, and the data reading circuit includes: a first voltage sampling module, which is used to access a first current and output a first voltage; a second voltage sampling module, which is used to access a second current and output a second voltage; a comparison module, wherein a first input terminal of the comparison module is connected to an output terminal of the first voltage sampling module to receive a first voltage, a second input terminal of the comparison module is connected to an output terminal of the second voltage sampling module to receive a second voltage, and an output terminal of the comparison module is used to output a comparison result obtained according to the first voltage and the second voltage; wherein the first current is one of a reference current and a read current flowing through the bit line, and the second current is the other of the reference current and the read current. The present application improves the accuracy and reliability of data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 A circuit diagram of a storage array of a memory provided for some embodiments of the present application;

[0045] Figure 2 Some embodiments of the present application provide corresponding Figure 1 A circuit diagram of a memory cell pair in the memory array shown;

[0046] Figure 3 Some embodiments of the present application provide corresponding Figure 1 A schematic cross-sectional structure diagram of a memory cell pair in the memory array shown;

[0047] Figure 4 A structural block diagram of a memory provided for some embodiments of the present application;

[0048] Figure 5 It is a schematic diagram of the distribution of the read current of a non-volatile memory device with a split floating gate under different background data (Background Pattern) modes;

[0049] Figure 6 A circuit structure diagram of a data reading circuit;

[0050] Figure 7 for Figure 6 Schematic diagram of the circuit structure of the inverter;

[0051] Figure 8 For Figure 6 A schematic diagram of the structure of the flip point adjustment circuit of the inverter;

[0052] Fig. 9 is a schematic diagram of the transfer characteristic curve of the inverter;

[0053] Fig.10 A structural block diagram of a data reading circuit provided in some embodiments of the present application;

[0054] Fig.11 Another structural block diagram of a data reading circuit provided in some embodiments of the present application;

[0055] Fig.12 Another structural block diagram of a data reading circuit provided in some embodiments of the present application;

[0056] Fig.13 Another structural block diagram of a data reading circuit provided in some embodiments of the present application;

[0057] Fig.14 Another structural block diagram of a data reading circuit provided for some embodiments of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0061] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0062] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0063] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0064] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0065] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] With the development of informatization and digitalization, data storage and management are becoming more and more important. Therefore, the development of storage technology is becoming more and more critical. Among them, Flash memory, as a non-volatile memory, has the advantages of high density, low power consumption, and fast reading speed. It is widely used in digital devices, embedded systems, and computer hardware. For non-volatile memory, the reliability and anti-interference characteristics of the data reading circuit in its peripheral circuit will have a huge impact on the reading speed and power consumption of the entire non-volatile memory.

[0068] The memory 100 of the present application includes: Figure 1 The storage array 10 is shown. Figure 1 A circuit diagram of a memory array 10 of a memory 100 provided in some embodiments of the present application. Figure 1 As shown, the memory array 10 includes a plurality of memory cell pairs 101 arranged in an array, that is, the plurality of memory cell pairs 101 arranged in an array are arranged in multiple rows and columns. Each row of memory cell pairs 101 includes at least two memory cell pairs 101 arranged along the row direction. Each column of memory cell pairs 101 includes at least two memory cell pairs 101 arranged along the column direction. For example, Figure 1 Only four rows and five columns of memory cell pairs 101 are shown. It should be noted that the row direction and column direction may be in any direction. For example, Figure 1 The X direction and Y direction shown can be a row or a column of storage cell pairs respectively. For example, the diagonal direction can also be a row or a column of storage cell pairs. For example, a row of storage cell pairs 101 is not necessarily arranged in a straight line, but can be arranged in a zigzag pattern alternately up and down. The specific situation of the rows and columns depends on the actual process layout. In fact, the number of rows and columns of the memory cell pairs 101 included in the memory depends on its storage capacity. Please refer to Figure 2 and Figure 3 As shown, Figure 2Some embodiments of the present application provide corresponding Figure 1 The circuit diagram of a memory cell pair 101 in the memory array 10 is shown. Figure 3 Some embodiments of the present application provide corresponding Figure 1 The cross-sectional structure diagram of a memory cell pair 101 in the memory array 10 is shown.

[0069] like Figure 3 As shown, the memory 100 includes a semiconductor layer 107, and the semiconductor layer 107 can be of a first doping type. Each memory cell pair 101 includes a first source and drain region 1081, a second source and drain region 1082, and a channel region 109 located in the semiconductor layer 107. The channel region 109 is located between the first source and drain region 1081 and the second source and drain region 1082. The first source and drain region 1081 and the second source and drain region 1082 can be of a second doping type, which is different from the first doping type. For example, the first doping type can be a P-type, and the second doping type can be an N-type. It can be understood that the first doping type can be an N-type, and the second doping type can be a P-type.

[0070] like Figure 2 and Figure 3 As shown, each memory cell pair 101 is a split floating gate structure. Each memory cell pair 101 includes two memory cells 102 connected in series and a word line gate 103 located between the two memory cells 102. The two memory cells 102 connected in series share one word line gate 103. The word line gate 103 is located on one side of the channel region 109 and an insulating layer (not shown in the figure) is provided between the word line gate 103 and the semiconductor layer 107.

[0071] Each memory cell 102 further includes a split gate structure 104 located on one side of the channel region 109. The word line gate 103 is located between the two split gate structures 104. An insulating layer (not shown in the figure) is provided between the word line gate 103 and the split gate structure 104. The orthographic projections of the split gate structure 104 and the word line gate 103 on the semiconductor layer 107 overlap with the orthographic projection of the channel region 109 on the semiconductor layer 107.

[0072] Each split gate structure 104 includes a floating gate 105 (abbreviated as FG) and a control gate 106 (abbreviated as CG). The control gate 106 is located on the side of the floating gate 105 away from the semiconductor layer 107 along the first direction X. Data is stored through the floating gate 105, that is, a floating gate 105 can be used as a storage bit. An insulating layer (not shown in the figure) is arranged between the floating gate 105 and the semiconductor layer 107. An insulating layer (not shown in the figure) is also arranged between the control gate 106 and the floating gate 105. For example, Figure 3As shown, two spaced-apart split gate structures 104 include a first split gate structure 1041 and a second split gate structure 1042. The first split gate structure 1041 includes a first floating gate 1051 and a first control gate 1061. The second split gate structure 1042 includes a second floating gate 1052 and a second control gate 1062. The first floating gate 1051 and the second floating gate 1052 constitute two storage bits that are mirror images of each other. The first storage bit is the first floating gate 1051, and the second storage bit is the second floating gate 1052. Figure 3 The first pair of memory cells shown can store 2 bits of data.

[0073] The material of the control gate 106 and the word line gate 103 includes metal. The material of the floating gate 105 includes polysilicon. The material of the insulating layer between the word line gate 103 and the semiconductor layer 107, the insulating layer between the control gate 106 and the floating gate 105, the insulating layer between the floating gate 105 and the semiconductor layer 107, and the insulating layer between the word line gate 103 and the split gate structure 104 may include silicon oxide.

[0074] For example, due to the above structural design of the memory cell pair 101, each memory cell pair 101 can store two bits of data. When the data stored in each memory cell 102 is "0", the floating gate 105 of the memory cell 102 has more electrons, so that the memory cell 102 is in a programmed state. At this time, the memory cell 102 has a first threshold voltage. When the data stored in each memory cell 102 is "1", there are not enough electrons in the floating gate 105 of the memory cell 102, so that the memory cell 102 is in an unprogrammed state. At this time, the memory cell 102 has a second threshold voltage. The first threshold voltage is greater than the second threshold voltage. For example, the first threshold voltage can be greater than or equal to 2V and less than or equal to 3V. The second threshold voltage can be less than 0V.

[0075] like Figure 1 As shown, the memory 100 further includes a plurality of word lines WL arranged along the column direction. , i is an integer greater than or equal to 0. For example, a plurality of word lines WL Including word lines WL arranged in sequence <0> , WL <1> , WL <2> and WL <3> .like Figure 1 and Figure 2 As shown, the word line gate 103 of each memory cell pair 101 in each row of memory cell pairs 101 is connected to a word line WL connect.

[0076] like Figure 1 As shown, the memory 100 further includes two control gate lines connected to each row of memory cell pairs 101. The two control gate lines include a first control gate line CG0 and the second control gate line CG1 For example, a plurality of first control gate lines CG0 The first control gate lines CG0 are arranged in sequence along the column direction. <0> , first control gate line CG0 <1> , first control gate line CG0 <2> and the first control gate line CG0 <3> ; Multiple second control gate lines CG1 The second control gate lines CG1 are arranged in sequence along the column direction. <0> , the second control gate line CG1 <1> , the second control gate line CG1 <2> and the second control gate line CG1 <3> A first control gate line CG0 and a second control gate line CG1 Adjacently arranged, and a word line WL Set on a first control gate line CG0 and a second control gate line CG1 Between. Figure 1 and Figure 2 As shown, the first control gate line CG0 and the second control gate line CG1 are respectively connected to the control gates 106 of the two memory cells 102 of each memory cell pair 101 in each row of memory cell pairs 101. Figure 1 and Figure 2 As shown, the first storage bit (first floating gate 1051) is connected to the first control gate 1061, and the first control gate 1061 is connected to the first control gate line CG0. The second storage bit (second floating gate 1052) is connected to the second control gate 1062, and the second control gate 1062 is connected to the second control gate line CG1. connect.

[0077] The memory 100 further includes a plurality of bit lines. The first source-drain region 1081 and the second source-drain region 1082 of each memory cell pair 101 can be connected to two bit lines respectively through bit line contacts (not shown).

[0078] In some embodiments, two adjacent memory cell pairs 101 in a row of memory cell pairs 101 share a bit line. In this way, the number of bit lines can be reduced, and there is more space for arranging memory cell pairs 101, so as to increase the storage capacity of the memory 100. For example, Figure 1 and Figure 2 As shown, the plurality of bit lines include a plurality of first bit lines BL<2n> and a plurality of second bit lines BL<2n+1> alternately arranged along the row direction, where n is a natural number. For example, the plurality of first bit lines BL<2n> include a first bit line BL <0> , first bit line BL <2> , a first bit line BL<2n>, etc., a plurality of second bit lines BL<2n+1> includes a second bit line BL <1> , the second bit line BL <3> , the second bit line BL<2n+1>, etc. Two adjacent memory cell pairs 101 in a row of memory cell pairs 101 are located in two adjacent columns. Among two adjacent memory cell pairs 101 in a row of memory cell pairs 101, the first source and drain regions 1081 and the second source and drain regions 1082 of one memory cell pair 101 are connected to the first bit line BL<2n> and the second bit line BL<2n+1> respectively through bit line contacts, and the first source and drain regions 1081 and the second source and drain regions 1082 of the other memory cell pair 101 are connected to the second bit line BL<2n+1> and the first bit line BL<2n+2> respectively through bit line contacts.

[0079] In two adjacent memory cell pairs 101 in a row of memory cell pairs 101, the first source and drain regions 1081 and the second source and drain regions 1082 of one memory cell pair 101 are connected to the first bit line BL<2n> and the second bit line BL<2n+1> respectively through bit line contacts, and the first source and drain regions 1081 and the second source and drain regions 1082 of the other memory cell pair 101 are connected to the second bit line BL<2n+1> and the first bit line BL<2n+2> respectively through bit line contacts. For example, Figure 2 and Figure 3 As shown, the first source-drain region 1081 of a memory cell pair 101 is connected to the second bit line BL<2n+1>, and the second source-drain region 1082 of a memory cell pair 101 is connected to the first bit line BL<2n>. Figure 3 The first source and drain region 1081 in the circuit is close to the first control gate line CG0. , Figure 3 The first source and drain region 1081 in the Figure 1 The first bit line BL<2n> in Figure 3 The second source and drain region 1082 is close to the second control gate line CG1 , Figure 3 The second source and drain region 1082 in the corresponding connection Figure 1 The second bit line BL<2n+1> in .

[0080] In other embodiments, two adjacent memory cell pairs 101 in a row of memory cell pairs 101 may not share a bit line. For example, in two adjacent memory cell pairs 101 in a row of memory cell pairs 101, any one of the two bit lines connected to one memory cell pair 101 is different from any one of the two bit lines connected to another memory cell pair 101. In this way, when any one of the two adjacent memory cell pairs 101 in a row of memory cell pairs 101 is operated through a non-shared bit line, the operation is simpler.

[0081] In other embodiments, two adjacent memory cell pairs 101 in a row of memory cell pairs 101 may not share a bit line. For example, in two adjacent memory cell pairs 101 in a row of memory cell pairs 101, the first source and drain region 1081 or the second source and drain region 1082 of one memory cell pair 101 is connected to the bit line BL<2n-1> or the bit line BL<2n> through a bit line contact, respectively, and the first source and drain region 1081 or the second source and drain region 1082 of the other memory cell pair 101 is connected to the bit line BL<2n+1> or the bit line BL<2n+2> through a bit line contact, respectively. In this way, two adjacent memory cell pairs 101 in a row of memory cell pairs 101 may not share a bit line.

[0082] Please refer to Figure 4 As shown, Figure 4 The structure block diagram of the memory 100 provided in some embodiments of the present application. Figure 4 As shown, the memory 100 includes a memory array 10 and a peripheral circuit 20. Figure 4 As shown, the peripheral circuit 20 is connected to the memory array 10, and the memory array 10 includes a plurality of memory cell pairs 101. The peripheral circuit 20 includes a controller (not shown in the figure). These memory cell pairs 101 are addressed by word lines and bit lines. The controller is further connected to a host (not shown in the figure). The host is, for example, a computer, a digital camera, etc. The controller is configured to receive data from the host and then store the data in the memory array 10, and is also configured to read data from the memory array 10 and then send it to the host.

[0083] like Figure 4 As shown, the peripheral circuit 20 may include a controller (not shown in the figure), a control gate driver 201, a word line driver 202, a bit line driver 203, a charge pump (not shown in the figure), a row decoder (not shown in the figure), and a column decoder (not shown in the figure). The controller is connected to the control gate driver 201, the word line driver 202, and the bit line driver 203, respectively. The row decoder receives the row address signal output by the controller, and decodes the row address signal to obtain a row address selection signal. The column decoder receives the column address signal output by the controller, and decodes the column address signal to obtain a column address selection signal. The controller controls the charge pump to output the word line voltage Vwl, the control gate drive voltage (including the control gate conduction voltage Vcg_pass and the control gate read voltage Vcg_rd), and the bit line drive voltage (including the bit line bypass voltage Vbl_pass and the bit line read voltage Vbl_rd). It should be noted that this is just an example, and the bit line bypass voltage Vbl_pass and the bit line read voltage Vbl_rd have no special meanings, and are only used to distinguish the read voltages of the two bit lines connected to the selected memory cell pair.

[0084] like Figures 1 to 4 As shown, the word line driver 202 is connected to a plurality of word lines WL The word line driver 202 receives the row address selection signal and the word line voltage Vwl, and outputs the word line voltage Vwl to a plurality of word lines WL according to the row address selection signal. , to select at least one word line WL At least one row of memory cell pairs 101 is connected.

[0085] like Figures 1 to 4 As shown, the control gate driver 201 and a plurality of first control gate lines CG0 and a plurality of second control gate lines CG1 The control gate driver 201 receives the row address selection signal and the control gate conduction voltage Vcg_pass and the control gate read voltage Vcg_rd, and outputs the control gate conduction voltage Vcg_pass and the control gate read voltage Vcg_rd to a plurality of first control gate lines CG0 according to the row address selection signal. and a plurality of second control gate lines CG1 , to select at least one first control gate line CG0 A row of memory cells 102 connected thereto, and / or at least one second control gate line CG1 A row of memory cells 102 is connected.

[0086] like Figures 1 to 4 As shown, the bit line driver 203 is connected to a plurality of bit lines, a charge pump, and a column decoder. The bit line driver 203 receives a bit line drive voltage and a column address selection signal, and outputs the bit line drive voltage to the selected bit line according to the column address selection signal to select at least one column of memory cell pairs 101 connected to at least one bit line. Figure 4 As shown, the peripheral circuit 20 also includes a reference current generator (not shown) and a sense amplifier 204. The sense amplifier 204 is connected to the reference current generator and a plurality of bit lines. Based on the structural design of the peripheral circuit 20 of the memory 100, the operation of the memory 100 may include an erase operation, a read operation, and a program operation.

[0087] like Figure 1 As shown, when a read operation is performed on the memory array 10, that is, after addressing the selected memory cell pair to be read in the memory array 10, a word line read voltage Vwl_rd is applied to the word line connected to the selected memory cell of the selected memory cell pair, so as to select the selected memory cell to be read. A control gate read voltage Vcg_rd is applied to the control gate line connected to the selected memory cell of the selected memory cell pair, and a control gate pass voltage Vcg_pass is applied to the control gate line connected to the unselected memory cell of the selected memory cell pair, wherein the control gate line connected to the selected memory cell is one of the first control gate line and the second control gate line in the selected memory cell pair, and the control gate line connected to the unselected memory cell is the other of the first control gate line and the second control gate line in the selected memory cell pair, and the control gate read voltage Vcg_rd is less than the control gate pass voltage Vcg_pass. In addition, a bit line read voltage Vbl_rd (for example, GND or 0V, or a voltage less than 1V) is applied to a target bit line connected to a selected memory cell of the selected memory cell pair, and a bit line bypass voltage Vbl_pass is applied to a target bit line connected to an unselected memory cell of the selected memory cell pair, wherein the target bit line connected to the selected memory cell is one of the first bit line and the second bit line in the selected memory cell pair, and the target bit line connected to the unselected memory cell is the other of the first bit line and the second bit line in the selected memory cell pair, and the bit line read voltage Vbl_rd is less than the bit line bypass voltage Vbl_pass. In this way, a read current I_rd is generated between the two bit lines connected to the selected memory cell pair, and when the read current I_rd is greater than the reference current I_ref, the data read from the selected memory cell is "1", and when the read current I_rd is less than the reference current I_ref, the data read from the selected memory cell is "0".

[0088] The memory 100 of the present application also includes a NOR memory, which includes a plurality of array-arranged storage cells, that is, the plurality of array-arranged storage cells are arranged in multiple rows and columns. Each storage cell is connected to a word line and two bit lines, and two adjacent storage cells can share a bit line. Two adjacent storage cells can store 2 bits of data.

[0089] Two adjacent memory cells of the memory of the present application can store two bits of data. When reading the data of one of the two adjacent memory cells, the magnitude of the read current I_rd will be affected by the data stored in the other of the two adjacent memory cells. That is, the background data (Background Pattern) stored in the adjacent first memory cell 1011 and the second memory cell 1012 are different, resulting in different impedances in the bit line path, so that the magnitude of the current that ultimately passes through the bit line path is different, thereby making the read current I_rd obtained by the sense amplifier different. For example, the selected memory cell pair of a non-volatile memory device with a split floating gate stores two bits of data, and the background data stored by the selected memory cell pair has a great influence on the data reading accuracy. Similarly, two adjacent memory cells of a NOR-type memory can also store two bits of data, and the background data of the two adjacent memory cells also has a great influence on the data reading accuracy. A non-volatile memory device with a split floating gate includes a non-volatile memory device with a split floating gate, please refer to Figure 5 As shown, Figure 5 Schematic diagram of the distribution of the read current I_rd of the non-volatile memory device with split floating gate in different background data modes, such as Figure 5 As shown in the figure, when the background data is "00" and "10", the normal distribution curves L1 and L2 of the corresponding read current I_rd are on the left side of the reference current I_ref, and the data read from the first storage unit 1011 is "0". When the background data is "01" and "11", the normal distribution curves L3 and L4 of the corresponding read current I_rd are on the right side of the reference current I_ref, and the data read from the first storage unit 1011 is "1".

[0090] like Figure 5 As shown, the problem with the current reading method is that, for the case where the background data is "01" and "11", although the normal distribution curves L3 and L4 of the read current I_rd are both on the right side of the reference current I_ref, the normal distribution curve L3 is obviously close to the reference current I_ref. At this time, the reading margin from the lowest value of the read current I_rd (i.e., about 7uA) to the reference current I_ref (about 5.4uA) is less than 2uA. When the background data is "00" and "01", a control gate read voltage is applied to the control gate line connected to the selected storage cell, and a word line read voltage is applied to the word line connected to the selected storage cell. Due to the coupling effect of the voltage on the word line connected to the selected storage cell, the voltage of the floating gate of the selected storage cell is raised, which will cause the read current I_rd flowing through the bit line path of the selected storage cell pair to which the selected storage cell belongs to increase, further reducing the reading margin. At this time, if the precision of the sensitive amplifier used is not high and the noise interference resistance is not strong, this will lead to a decrease in data reading accuracy, thereby increasing the risk of data reading errors.

[0091] Please refer to Figure 6 As shown, Figure 6 A circuit structure diagram of a data reading circuit, such as Figure 6 As shown, the data reading circuit includes a precharge branch, a reference circuit replica branch, a clamp circuit, a switch tube Q1, an inverter, and a data latch. The inverter is used to detect the voltage change of the first node SAIN and output a level signal opposite to the level at the node SAIN. The inverter's flip point voltage (the threshold voltage at which the inverter switches from one level to another) directly determines the accuracy of the read data, so it is critical to accurately adjust it to the desired flip point. Please refer to Figure 7 and Figure 8 As shown, Figure 7 for Figure 6 The circuit diagram of the inverter in the figure is as follows: Figure 8 For Figure 6 The schematic diagram of the flip point adjustment circuit of the inverter in FIG. Figure 6 and Figure 7 As shown, the inverter can be composed of two enhancement mode MOS field effect transistors, one of which is a first transistor Q2 and the other is a second transistor Q3, and the source of the second transistor Q3 is grounded. Figure 6 and Figure 7 The second transistor Q3 is shown directly connected to ground. Figure 6 and Figure 8 As shown, the second transistor Q3 of the inverter is added with another third transistor Q4 connected to the second transistor Q3 and connected to the control end of the third transistor Q4 through a newly added NBIAS voltage generating circuit. The source of the third transistor Q4 is grounded, thereby raising the flip point voltage of the inverter.

[0092] like Figure 6 As shown, when performing a read operation, the target bit line connected to the selected storage cell is charged through the precharge module, and the voltage of the target bit line connected to the selected storage cell is clamped to the bit line reading voltage through the clamp circuit, so as to obtain the reading current I_rd corresponding to the selected storage cell. In this way, the reference current I_ref and the reading current I_rd compete on the same branch, the reference current I_ref can charge the first node SAIN, and the reading current I_rd can discharge the first node SAIN. The flip point voltage of the inverter is compared with the target voltage at the first node SAIN and the comparison result is output, and then the data in the selected storage cell is read out and latched under the control of the control signal RDSA. If the data stored in the selected storage cell is "0", it indicates that the reference current I_ref is greater than the reading current I_rd, that is, the charging is greater than the discharging, and the target voltage at the first node SAIN is high level, and the output data is "0" after being flipped by the inverter. On the contrary, if the data stored in the selected memory cell is "1", it indicates that the reference current I_ref is smaller than the read current I_rd, that is, the charging is smaller than the discharging, the target voltage at the first node SAIN is low, and the output data is "1" after being flipped by the inverter.

[0093] like Figure 6 and Figure 8 The circuit for reading data in the structure shown is simple, but the accuracy is poor. In addition, since the inverter is used to detect the target voltage at the first node SAIN to determine the read data of the selected storage cell, the inverter's flip point voltage needs to be adjusted, and it is easily disturbed by power supply noise. The inverter's flip point voltage is compared with the target voltage of the first node SAIN to determine the read data of the selected storage cell. In addition to being disturbed by power supply noise and reducing the reading accuracy, it also has higher requirements for the target voltage of the first node SAIN. Please refer to Fig. 9 As shown, Fig. 9 is a schematic diagram of the transfer characteristic curve of the inverter, as shown in Fig. 9 As shown, when the voltage value input to the input terminal of the inverter is near the flip point, the output voltage of the inverter will be a value between 0 and the power supply voltage VDD. This requires that when performing a data read operation, the voltage value input to the input terminal of the inverter (i.e., the target voltage of the first node SAIN) should be far away from the flip point voltage so that the output voltage of the inverter can be closer to 0 or VDD. However, for non-volatile storage, there may be a situation where the difference between the read current I_rd and the reference current I_ref is small. At this time, no matter whether the read data is 0 or 1, the output voltage of the inverter will be between 0 and VDD, causing misreading.

[0094] In order to improve the above problem, a data reading circuit 200 is described below. The data reading circuit 200 can be applied to the memory 100 described in the above embodiment, but is not limited to the above memory 100.

[0095] Please refer to Fig.10 , Fig.10 A structural block diagram of a data reading circuit 200 provided in some embodiments of the present application, the data reading circuit 200 is applied to a memory 100, the memory 100 includes a plurality of storage cells, each of the storage cells is connected to a bit line, such as Fig.10 As shown, the data reading circuit 200 includes:

[0096] A first voltage sampling module 210, configured to receive a first current I1 and output a first voltage V1;

[0097] A second voltage sampling module 220, used for receiving a second current I2 and outputting a second voltage V2;

[0098] a comparison module 230, wherein a first input terminal IN1 of the comparison module 230 is connected to an output terminal out1 of the first voltage sampling module 210 to receive the first voltage V1, a second input terminal IN2 of the comparison module 230 is connected to an output terminal out2 of the second voltage sampling module 220 to receive the second voltage V2, and an output terminal of the comparison module 230 is used to output a comparison result obtained according to the first voltage V1 and the second voltage V2;

[0099] The first current I1 is one of a reference current I_ref and a read current I_rd flowing through the bit line, and the second current I2 is the other of the reference current I_ref and the read current I_rd.

[0100] In the embodiments of the present application, Fig.10 As shown, the data reading circuit 200 includes a first voltage sampling module 210, a second voltage sampling module 220 and a comparison module 230. The data reading circuit 200 has two symmetrical branches, one branch is the first voltage sampling module 210, and the other branch is the second voltage sampling module 220. Among them, the input end of the first voltage sampling module 210 or the input end of the second voltage sampling module 220 is connected to the target bit line, and the target bit line is the target bit line connected to the selected memory cell of two different and adjacent memory cells. When performing a read operation on the selected memory cell, there is only one branch, the input end of the selected voltage sampling module (one of the first voltage sampling module 210 and the second voltage sampling module 220) is connected to the target bit line connected to the selected memory cell to access the read current I_rd flowing through the bit line connected to the selected memory cell and generate a corresponding voltage, and the input end of the other non-selected voltage sampling module (the other of the first voltage sampling module 210 and the second voltage sampling module 220) is connected to the reference current I_ref and generates a corresponding voltage. For example, assuming that the first voltage sampling module 210 is a selected voltage sampling module and the second voltage sampling module 220 is a non-selected voltage sampling module, the input end of the first voltage sampling module 210 is connected to the first current I1 and generates a first voltage V1, and the input end of the other branch, that is, the second voltage sampling module 220, is connected to the reference current I_ref and generates a second voltage V2, at which time the first current I1 is the read current I_rd and the second current I2 is the reference current I_ref. Of course, assuming that the first voltage sampling module 210 is a non-selected voltage sampling module and the second voltage sampling module 220 is a selected voltage sampling module, the input end of the first voltage sampling module 210 is connected to the first current I1 and generates a first voltage V1, and the input end of the other branch, that is, the second voltage sampling module 220, is connected to the reference current I_ref and generates a second voltage V2, at which time the second current I2 is the read current I_rd and the first current I1 is the reference current I_ref.

[0101] like Fig.10 As shown, the first input terminal IN1 and the second input terminal IN2 of the comparison module 230 are respectively connected to the output terminal out1 of the first voltage sampling module 210 and the output terminal out2 of the second voltage sampling module 220 to receive the first voltage V1 and the second voltage V2. The comparison module 230 compares the received first voltage V1 and the second voltage V2 to obtain a comparison result, and can determine the data read from the selected storage cell to complete the data reading operation of the selected storage cell.

[0102] The data reading circuit 200 of the present application is symmetrical in structure as a whole, and a first voltage V1 generated by connecting one branch to the first current I1 is compared with a second voltage V2 generated by connecting another branch to the second current I2. If there is noise in the two branches or the conductivity of the transistor changes, these effects can be offset by the common-mode power supply noise of the data reading circuit 200 of the present application with a differential symmetrical structure, thereby improving the ability to resist noise interference and improving the reading accuracy of the memory 100 when performing a reading operation.

[0103] In some embodiments, please refer to Fig.11 , Fig.11 Another structural block diagram of the data reading circuit 200 provided in some embodiments of the present application is shown in FIG. Fig.11 As shown, the comparison module 230 includes: a first latch 231 , and two ends of the first latch 231 are respectively connected to the first voltage sampling module 210 and the second voltage sampling module 220 .

[0104] In the embodiments of the present application, Fig.10 and Fig.11 As shown, the comparison module 230 includes a first latch 231 for comparing the first voltage V1 and the second voltage V2. One end of the first latch 231 can be used as both an input end and an output end, and the other end of the first latch 231 can be used as both an input end and an output end. In this way, the voltage difference between the first voltage V1 generated by the first current I1 and the second voltage V2 generated by the second current I2 can be increased. By setting the first latch 231, the present application can increase the voltage difference between the first voltage V1 generated by the first current I1 and the second voltage V2 generated by the second current I2, thereby improving the reading accuracy of the data reading circuit 200 and improving the reliability and accuracy of data reading.

[0105] In some embodiments, please refer to Fig.12 and Fig.13 As shown, Fig.12 Another structural block diagram of a data reading circuit 200 provided in some embodiments of the present application, Fig.13 Another structural block diagram of the data reading circuit 200 provided in some embodiments of the present application is shown in FIG. Fig.12 and Fig.13 As shown, the data reading circuit 200 further includes: a switch module 240 and a compensation load 250;

[0106] The first end a of the switch module 240 is connected to the input end in1 of the first voltage sampling module 210 , and the second end b of the switch module 240 is connected to the input end in2 of the second voltage sampling module 220 ;

[0107] The input terminal c of the switch module 240 is used to access the reference current I_ref. The input terminal c of the switch module 240 is also connected to the compensation load 250 .

[0108] In the embodiment of the present application, the peripheral circuit 20 of the memory 100 includes not only the data reading circuit 200 but also a reference current generator 26 for generating a reference current I_ref. Fig.12 and Fig.13 As shown, the data reading circuit 200 includes a switch module 240 and a compensation load 250. The first terminal a of the switch module 240 is connected to the input terminal in1 of the first voltage sampling module 210, the second terminal b of the switch module 240 is connected to the input terminal in2 of the second voltage sampling module 220, the output terminal of the reference current generator 26 is connected to the input terminal c of the switch module 240, and the reference current generator 26 outputs the generated reference current I_ref to the input terminal c of the switch module 240. After receiving the reference current I_ref, the switch module 240 can choose to transmit the reference current I_ref to the input terminal in1 of the first voltage sampling module 210, or to the input terminal in2 of the second voltage sampling module 220. In this way, one of the two branches can transmit the reference current I_ref to one of the input terminal in1 of the first voltage sampling module 210 and the input terminal in2 of the second voltage sampling module 220 under the control of the switch module 240, and the other of the two branches can transmit the read current I_rd read from the selected storage cell to the other of the input terminal in1 of the first voltage sampling module 210 and the input terminal in2 of the second voltage sampling module 220 under the control of the switch module 240, so that the two input terminals of the comparison module 230 receive the read current I_rd and the reference current I_ref from the two parallel branches, that is, from the output terminal out1 of the first voltage sampling module 210 and the output terminal out2 of the second voltage sampling module 220, respectively.

[0109] The compensation load 250 of the present application refers to a compensation device for balancing the loads of the two branches. The compensation load 250 of the present application includes but is not limited to any one or more of a compensation capacitor and an adjustable resistor. Since one branch is directly connected to the selected storage unit and is connected to the read current I_rd generated when the selected storage unit is read, and the other branch is connected to the reference current I_ref and is not directly connected to the non-selected storage unit, the loads of the two branches will be biased. Since the branch connected to the read current I_rd in the two branches is directly connected to the selected storage unit, the load of the branch connected to the read current I_rd is greater than the load of the other branch connected to the reference current I_ref. In order to improve the circuit accuracy, the branch connected to the reference current I_ref is connected to the compensation load 250 through the control of the switch module 240, so that the branch connected to the reference current I_ref in the two branches is added to the compensation load 250, which can compensate for the load of the other branch connected to the reference current I_ref in the two branches, so that the loads on the two branches after compensation are approximately the same, so that the establishment of the current and voltage on the two branches is kept synchronous, and the reading accuracy is improved. The embodiment of the present application preferably uses a compensation capacitor as the compensation load 250. Compared with using an adjustable resistor as the compensation load 250, which requires calculating the load difference between the two branches for targeted load compensation, the charge coupling function of the compensation capacitor can be used to arbitrarily and flexibly make the loads on the two branches after compensation approximately the same. The compensation scheme is simpler and more efficient, thereby accelerating the data reading speed of the memory 100.

[0110] In some embodiments, Fig.12 As shown, the data reading circuit 200 further includes a precharge module 280, one end of which is connected to the power supply voltage VDD, and the other end of which is respectively connected to the input end in1 of the first voltage sampling module 210 and the first end of the first switch tube T1 mentioned in the following embodiment, and the other end of the precharge module 280 is also respectively connected to the input end in2 of the second voltage sampling module 220 and the first end of the second switch tube T2 mentioned in the following embodiment. When performing a read operation on the memory 100, the target bit line connected to the selected memory cell can be precharged through the precharge module 280.

[0111] In some embodiments, Fig.13 As shown, the pre-charging module 280 may include a first pre-charging sub-module 281 and a second pre-charging sub-module 282, one end of the first pre-charging sub-module 281 and one end of the second pre-charging sub-module 282 are respectively connected to the power supply voltage VDD, the other end of the first pre-charging sub-module 281 is connected to the input end in1 of the first voltage sampling module 210, and the other end of the second pre-charging sub-module 282 is connected to the input end in2 of the second voltage sampling module 220.

[0112] In the present application embodiment, Fig.13 As shown, the other end of the first pre-charging submodule 281 is connected to the first end of the first switch tube T1 mentioned in the following embodiment, and the other end of the second pre-charging submodule 282 is respectively connected to the input end in2 of the second voltage sampling module 220 and the first end of the second switch tube T2. The first pre-charging submodule 281 is used to charge the input end in1 of the first voltage sampling module 210, and the second pre-charging submodule 282 is used to charge the input end in2 of the second voltage sampling module 220. In this way, when the memory 100 is read, a short circuit between the input end in1 of the first voltage sampling module 210 and the input end in2 of the second voltage sampling module 220 is avoided.

[0113] In some embodiments, Fig.12 and Fig.13 As shown, in some embodiments, the data reading circuit 200 further includes a first switch tube T1 and a second switch tube T2; the switch module 240 includes a first switch S1 and a second switch S2;

[0114] The first end of the first switch tube T1 is connected to the input end in1 of the first voltage sampling module 210, and the second end of the first switch tube T1 is used to access the first current I1;

[0115] The first end of the second switch tube T2 is connected to the input end in2 of the second voltage sampling module 220, and the second end of the second switch tube T2 is used to access the second current I2;

[0116] One end of the first switch S1 is connected to the second end of the first switch tube T1, and the other end of the first switch S1 is connected to the compensation load and the reference current generator 26 included in the peripheral circuit of the memory respectively;

[0117] One end of the second switch S2 is connected to the second end of the second switch tube T2, and the other end of the second switch S2 is connected to the compensation load 250 and the reference current generator 26 included in the peripheral circuit 20 of the memory, respectively.

[0118] In the embodiments of the present application, Fig.12 and Fig.13 As shown, the data reading circuit 200 further includes a first switch tube T1 and a second switch tube T2, wherein the first end of the first switch tube T1 is connected to the input end in1 of the first voltage sampling module 210, the second end of the first switch tube T1 is connected to the first end a of the switch module 240, and the second end of the first switch tube T1 is also used to access the first current I1. The first end of the second switch tube T2 is connected to the input end in2 of the second voltage sampling module 220, the second end of the second switch tube T2 is connected to the second end b of the switch module 240, and the second end of the second switch tube T2 is also used to access the second current I2.

[0119] When the data reading circuit 200 obtains the data reading instruction, an opening command is generated and transmitted to the control end of the first switch tube T1 and the control end of the second switch tube T2. After receiving the opening command, the control end of the first switch tube T1 can be switched to the conducting state to access the first current I1, and transmit the first current I1 to the input end in1 of the first voltage sampling module 210. After receiving the opening command, the control end of the second switch tube T2 can be switched to the conducting state to access the second current I2, and transmit the second current I2 to the input end in2 of the second voltage sampling module 220. If the first current I1 is the reading current I_rd and the second current I2 is the reference current I_ref, then the first switch S1 is closed (disconnected) and the second switch S2 is opened (closed or turned on), so that the reference current I_ref is copied to the second branch Z2 by the current mirror, and the compensation load 250 is connected to the second branch Z2, so that the loads of the first branch Z1 and the second branch Z2 are approximately the same. Of course, if the first current I1 is the reference current I_ref and the second current I2 is the read current I_rd, then the first switch S1 is opened and the second switch S2 is closed, so that the reference current I_ref is copied to the first branch Z1 by the current mirror, and the compensation load 250 is connected to the first branch Z1, so that the loads of the first branch Z1 and the second branch Z2 are approximately the same.

[0120] In some embodiments, the peripheral circuit 20 further includes a clamp circuit 25 and a gating circuit 27, wherein the output end of the clamp circuit 25 is respectively connected to the control end of the first switch tube T1 and the control end of the second switch tube T2, and the gating circuit 27 is respectively connected to multiple storage cells one by one through multiple bit lines.

[0121] In the embodiments of the present application, Fig.12 and Fig.13 As shown, when a read operation is performed on the memory 100, a row address selection signal and a column address selection signal can be obtained according to the read instruction, and a memory cell can be selected as the selected memory cell according to the row address selection signal and the column address selection signal, and the gating circuit 27 can turn on the control switch (either the first switch tube T1 or the second switch tube T2) located on the bit line connected to the selected memory cell, thereby obtaining the read current I_rd of the bit line connected to the selected memory cell. The clamping circuit 25 is used to provide a clamping voltage, so as to clamp the voltage of the target bit line connected to the read current I_rd to a reference voltage through the clamping voltage, and the reference voltage refers to the voltage value corresponding to the reference current Iref generated by the reference current generator 26. For example, the reference current generator 26 can be connected to a standard reference cell, and the reference current generator 26 can read the standard reference cell, and when the reference current Iref is obtained by reading, the voltage value applied to the corresponding standard reference cell is set as the reference voltage.

[0122] It should be noted that whether the target bit line connected to the read current I_rd is connected to the clamping voltage generated by the clamping circuit 25 is determined by the first switch S1 and the second switch S2 included in the switch module 240. Exemplarily, the first switch tube T1 and the second switch tube T2 are both closed, the first switch S1 is open and the second switch S2 is closed, then the reference current generator 26 generates a reference current Iref that flows into the second branch Z2 through the closed second switch S2, and the clamping circuit 25 provides a clamping voltage to the first branch Z1 through the closed first switch tube T1 to clamp the voltage of the bit line BL1, so that the voltage of the bit line BL1 is equal to the reference voltage (i.e., the voltage value corresponding to the reference current Iref generated by the reference current generator 26).

[0123] In some embodiments, Fig.13 As shown, the switch module 240 further includes a third switch S3 , and two ends of the third switch S3 are respectively connected to one end of the first switch S1 and one end of the second switch S2 .

[0124] In the present application embodiment, Fig.13 As shown, the switch module 240 includes a first switch S1, a second switch S2 and a third switch S3. One end of the first switch S1 is connected to the second end of the first switch tube T1, and the other end of the first switch S1 is connected to the reference current generator 26 and the compensation load 250. One end of the second switch S2 is connected to the second end of the second switch tube T2, and the other end of the second switch S2 is connected to the reference current generator 26 and the compensation load 250. Two ends of the third switch S3 are respectively connected to one end of the first switch S1 and one end of the second switch S2. When the pre-charge module 280 pre-charges the target bit line, the third switch S3 is opened (closed or turned on) to balance the potentials of the first branch Z1 and the second branch Z2. After the pre-charge module 280 finishes pre-charging the target bit line and before reading the selected storage cell, the third switch S3 is opened.

[0125] In some embodiments, Fig.11 As shown, the first voltage sampling module 210 includes: a first sampling resistor R1 and a first sampling switch K1, and the second voltage sampling module 220 includes a second sampling resistor R2 and a second sampling switch K2;

[0126] One end of the first sampling resistor R1 is connected to the power supply voltage VDD, the other end of the first sampling resistor R1 is connected to the first end of the first sampling switch K1, and the other end of the first sampling resistor R1 is also connected to the first current I1;

[0127] The second end of the first sampling switch K1 is connected to the first input end of the comparison module 230, and the control end of the first sampling switch K1 is used to receive the sampling control signal SignalA;

[0128] One end of the second sampling resistor R2 is connected to the power supply voltage VDD, the other end of the second sampling resistor R2 is connected to the first end of the second sampling switch K2, and the other end of the second sampling resistor R2 is also connected to the second current I2;

[0129] The second end of the second sampling switch K2 is connected to the second input end of the comparison module 230, and the control end of the second sampling switch K2 is used to receive the sampling control signal SignalA;

[0130] The sampling control signal SignalA is used to control the switching states of the first sampling switch K1 and the second sampling switch K2.

[0131] In the embodiment of the present application, the first sampling resistor R1 and the second sampling resistor R2 have the same resistance value, and the first sampling switch K1 and the second sampling switch K2 have the same model. Figures 10 to 12 Assuming that the first voltage sampling module 210 is a selected voltage sampling module and the second voltage sampling module 220 is a non-selected voltage sampling module, when the first current I1 is a read current I_rd and the second current I2 is a reference current I_ref, the target bit line connected to the selected storage cell is precharged by the precharge module 280, and the voltage on the target bit line is clamped to the same value as the voltage applied by the reference current I_ref generated by the reference current generator 26 by the clamp circuit 25, so that the read current I_rd can be read. The read current I_rd and the reference current I_ref are respectively in the first branch and the second branch, and the read current I_rd and the reference current I_ref are respectively transmitted to the first voltage sampling module 210 and the second voltage sampling module 220 at the same time to obtain the first voltage V1 and the second voltage V2. Then, the first voltage V1 and the second voltage V2 are respectively transmitted to the first input terminal and the second input terminal of the comparison module 230 at the same time, and the comparison module 230 compares the first voltage V1 and the second voltage V2 to read the data stored in the selected storage cell. Similarly, assuming that the first voltage sampling module 210 is a non-selected voltage sampling module, the second voltage sampling module 220 is a selected voltage sampling module, the first current I1 is a reference current I_ref and the second current I2 is a read current I_rd, the data stored in the selected storage unit can also be read with reference to the above description.

[0132] In this embodiment, since the first sampling resistor R1 included in the first voltage sampling module 210 and the second sampling resistor R2 included in the second voltage sampling module 220 have the same resistance value, the reference current I_ref and the read current I_rd respectively flow through the resistors of the same size in the first voltage sampling module 210 and the second voltage sampling module 220 to generate two different voltages. Since the currents on the series path are equal everywhere, the power supply voltage VDD connected to the first sampling resistor R1 of the first sampling module minus the voltage value obtained by voltage division through the first sampling resistor R1 is obtained to obtain the first voltage V1, and the power supply voltage VDD connected to the second sampling resistor R2 of the second sampling module minus the voltage value obtained by voltage division through the second sampling resistor R2 is obtained to obtain the second voltage V2, thereby realizing the conversion from current to voltage. When the control end of the first sampling switch K1 receives the sampling control signal SignalA, the first voltage V1 is transmitted to the first end c of the first latch 231. When the control end of the second sampling switch K2 receives the sampling control signal SignalA, the second voltage V2 is transmitted to the second end d of the first latch 231. The first latch 231 amplifies the first voltage V1 and the second voltage V2.

[0133] In the present application, a first sampling resistor R1 and a second sampling resistor R2 with the same resistance are used for voltage division. The power supply voltage VDD connected to the first sampling resistor R1 and the second sampling resistor R2, respectively, and the voltage values ​​respectively generated by the first sampling resistor R1 and the second sampling resistor R2 can be used to calculate the first voltage V1 and the second voltage V2. In this way, the data reading circuit 200 compares the magnitudes of the first voltage V1 and the second voltage V2, rather than the magnitudes of the read current I_rd and the reference current I_ref. In this way, the risk of misreading caused by the small margin between the read current I_rd and the reference current I_ref during the read operation of the memory 100 can be reduced, thereby improving the data reading precision and accuracy of the memory 100.

[0134] In some embodiments, Fig.11 As shown, the first latch 231 is composed of two mutually coupled inverters, a first end c of the first latch 231 is connected to the second end of the first sampling switch K1, and a second end d of the first latch 231 is connected to the second end of the second sampling switch K2.

[0135] In the embodiments of the present application, Fig.11 As shown, the first latch 231 includes two inverters, which are the third inverter PI1 and the fourth inverter PI2. The two inverters are connected end to end to form a mutual feedback coupling form, that is, the input end of the third inverter PI1 is connected to the output end of the fourth inverter PI2, the output end of the third inverter PI1 is connected to the input end of the fourth inverter PI2, the input end of the third inverter PI1 and the output end of the fourth inverter PI2 are equivalent to the first end c of the first latch 231, and the output end of the third inverter PI1 and the input end of the fourth inverter PI2 are equivalent to the second end d of the first latch 231. When the input of the third inverter PI1 in the first latch 231 is "1", its output is "0", and the input of the fourth inverter PI2 in the first latch 231 will also become "0", so that the first end c of the first latch 231 keeps outputting "0". Similarly, when the input of the third inverter PI1 in the first latch 231 is "0", its output is "1", and the input of the fourth inverter PI2 in the first latch 231 also becomes "1", so that the first terminal c of the first latch 231 keeps outputting "1".

[0136] After the first voltage sampling module 210 samples the first voltage V1 and the second sampling module samples the second voltage V2, the first sampling switch K1 and the second sampling switch K2 are turned off by controlling the sampling control signal SignalA, and the first latch 231 can perform a second flip of the sampled first voltage V1 and the second voltage V2 to amplify the voltage difference between the first voltage V1 and the second voltage V2. The two inverters connected end to end in the first latch 231 can flip the low level twice and output it as 0, and the two inverters connected end to end in the first latch 231 can flip the high level twice and output it as 1. The first latch 231 of the present application is composed of two inverters connected end to end, which constitute a mutual feedback coupling form, have a positive feedback effect, and can accurately and quickly amplify the small signal voltage difference.

[0137] In some embodiments, please refer to Fig.14 As shown, Fig.14 Another structural block diagram of the data reading circuit 200 provided in some embodiments of the present application is shown in FIG. Fig.14 As shown, the first voltage sampling module 210 further includes a first current source 211, and the first voltage sampling module 210 further includes a second current source 221;

[0138] One end of the first current source 211 is connected to the power supply voltage VDD, and the other end of the first current source 211 is connected to the first end of the first sampling switch K1;

[0139] One end of the second current source 221 is connected to the power supply voltage VDD, and the other end of the second current source 221 is connected to the first end of the second sampling switch K2.

[0140] In the embodiment of the present application, the first current source 211 and the second current source 221 are the same, the first current source 211 is connected in parallel with the first sampling resistor R1, and the second current source 221 is connected in parallel with the second sampling resistor R2. In addition, one end of the first current source 211 is connected to the power supply voltage VDD, and the other end of the first current source 211 is simultaneously connected to the second end of the first sampling resistor R1 and the first end of the first sampling switch K1, respectively; one end of the second current source 221 is connected to the power supply voltage VDD, and the other end of the second current source 221 is simultaneously connected to the second end of the second sampling resistor R2 and the first end of the second sampling switch K2, respectively.

[0141] like Fig.11 As shown, since the resistance values ​​of the first sampling resistor R1 and the second sampling resistor R2 are the same, the read current I_rd and the reference current I_ref generate a voltage drop by flowing through the first sampling resistor R1 and the second sampling resistor R2, and the voltage difference ΔI×R across the first latch 231 is positively correlated with the resistance values ​​of the first sampling resistor R1 and the second sampling resistor R2, and for the comparison module 230, the resistance values ​​of the first sampling resistor R1 and the second sampling resistor R2 are more important. Because, if the resistance values ​​of the first sampling resistor R1 and the second sampling resistor R2 are too small, the voltage difference ΔI×R across the first latch 231 is small, resulting in poor data reading accuracy and anti-noise capability. If the resistance values ​​of the first sampling resistor R1 and the second sampling resistor R2 are too large, the resistor voltage division will be too large. When the power supply voltage VDD is low, the read current I_rd on the target bit line cannot be clamped to the voltage value applied to obtain the reference current I_ref, resulting in inaccurate read data. Therefore, it is necessary to pay attention to the reasonable selection of the sizes of the first sampling resistor R1 and the second sampling resistor R2.

[0142] In the embodiment of the present application, when the reading current I_rd and the reference current I_ref generate a voltage drop by flowing through the first sampling resistor R1 and the second sampling resistor R2, the first current source 211 and the second current source 221 can be used to divide the same current respectively, so that the first current I1 flowing through the first sampling resistor R1 and the second current I2 flowing through the second sampling resistor R2 can be reduced, so that the resistance of the first sampling resistor R1 and the second sampling resistor R2 can be appropriately increased. Since the resistance of the first sampling resistor R1 and the second sampling resistor R2 are the same, the first current I1 and the second current I2 can be subtracted by the same current value, so the current difference ΔI between the current flowing through the first node A and the current flowing through the second node B remains unchanged, and since the resistance of the first sampling resistor R1 and the second sampling resistor R2 increases synchronously, the voltage difference ΔI×R across the first latch 231 increases. The present application can achieve a smaller current difference ΔI by setting the first current source 211 and the second current source 221, but the voltage difference across the first latch 231 is larger. Increasing the voltage difference across the first latch 231 can avoid misreading caused by a small reading margin, thereby improving the accuracy of the read data.

[0143] In some embodiments, Fig.11 and Fig.14 As shown, the comparison module 230 further includes: a second latch 235, a first inverter 232, a second inverter 233 and a gate switch 234;

[0144] The input end of the first inverter 232 is connected to the first end c of the first latch 231 and the second end of the first sampling switch K1, and the output end of the first inverter 232 is connected to the first end of the gating switch 234;

[0145] The input end of the second inverter 233 is connected to the second end d of the first latch 231 and the second end of the second sampling switch K2, and the output end of the second inverter 233 is connected to the second end of the gate switch 234;

[0146] The output terminal of the gate switch 234 is connected to the input terminal of the second latch 235 .

[0147] In the embodiments of the present application, Figures 10 to 14 As shown, the comparison module 230 also includes a first inverter 232, a second inverter 233, a second latch 235 and a gate switch 234. The first end c of the first latch 231 is connected to the first end of the gate switch 234 through the first inverter 232, and the second end d of the first latch 231 is connected to the second end of the gate switch 234 through the second inverter 233. Continuing with the above embodiment, after the first sampling switch K1 completes sampling, the first voltage V1 connected to the first end c of the first latch 231 is transmitted to the first inverter 232 for flipping and outputting the first flipped voltage. Similarly, after the second sampling switch K2 completes sampling, the second voltage V2 connected to the second end d of the first latch 231 is transmitted to the second inverter 233 for flipping and outputting the second flipped voltage. The first end and the second end of the gate switch 234 receive the first flipped voltage obtained by flowing through the first inverter 232 and the second flipped voltage obtained by flowing through the first inverter 232, respectively.

[0148] Exemplarily, take the first current I1 connected to the first voltage sampling module 210 as the read current I_rd, and the data read from the selected storage cell as "0" as an example: assuming that the data stored in the selected storage cell is "0", the impedance on the target bit line connected to the selected storage cell is large, then the read current I_rd connected to the first voltage sampling module 210 is smaller than the reference current I_ref connected to the second voltage sampling module 220, so the voltage drop generated by the read current I_rd on the first sampling resistor R1 is small, therefore, the voltage value of the first voltage V1 (i.e., the voltage at the first node A) transmitted to the first input terminal of the first latch 231 by the first sampling switch K1 is large, that is, the first voltage V1 is high level, after the first input terminal of the first latch 231 is connected to the high level first voltage V1, the high level first voltage V1 can be flipped to 1, and then, through the first inverter 232, 1 is flipped to 0 and output to the first end of the selection switch 234. Similarly, the voltage value of the second voltage V2 (i.e., the voltage at the second node B) transmitted to the second input terminal of the first latch 231 by the second sampling switch K2 is small, that is, the second voltage V2 is at a low level. After the second input terminal of the first latch 231 is connected to the low-level second voltage V2, the low-level second voltage V2 can be flipped to 0, and then, after passing through the second inverter 233, 0 is flipped to 1 and output to the second end of the selection switch 234.

[0149] The present application converts the read current I_rd and the reference current I_ref into two corresponding voltages, and uses the first latch 231 to compare the magnitudes of the two voltages to read out the data. The present application can directly compare the magnitudes of the two voltages without considering the flip voltage of the inverter. Moreover, since the first latch 231 is composed of two mutually coupled inverters, the bistable circuit formed by the mutual coupling of the inverters has a positive feedback effect, which can not only improve the accuracy of data reading, but also speed up the reading speed.

[0150] In some embodiments, the memory 100 is a NOR memory 100, and the NOR memory 100 includes multiple storage units, one of the multiple storage units is connected to the first voltage sampling module 210, and another storage unit of the multiple storage units is connected to the second voltage sampling module 220.

[0151] In some embodiments, the memory 100 is a non-volatile memory device 100 with a split floating gate, and the non-volatile memory device 100 with a split floating gate includes a plurality of memory cell pairs, wherein the memory cell pairs include two memory cells, one of the two memory cells is connected to the first voltage sampling module 210, and the other of the two memory cells is connected to the second voltage sampling module 220.

[0152] The data reading circuit 200 of the present application is a differential symmetrical structure, so the anti-noise interference capability can be improved, and the reading accuracy can be improved by compensating the load of the branch connected to the reference current I_ref. The present application converts the current into voltage, and can improve the reading accuracy and the accuracy of the reading operation by adding a new current source or appropriately increasing the resistance value of the sampling resistor. The data reading circuit 200 of the present application is not limited to a non-volatile memory device with a split floating gate, and can be applied to other memories 100 with a smaller current margin, such as NOR Flash.

[0153] The present application also provides a memory 100, which includes a plurality of memory cells and a peripheral circuit, each of the memory cells is connected to a bit line, and the peripheral circuit includes the data reading circuit 200 described in the above embodiment, and the data reading circuit 200 is connected to the bit line.

[0154] The above is a detailed introduction to a data reading circuit and a memory provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data reading circuit, characterized in that: Applied to a memory, the memory includes a plurality of storage units, each of the storage units is connected to a bit line, and the data reading circuit includes: A first voltage sampling module, used for receiving a first current and outputting a first voltage; A second voltage sampling module, used for receiving a second current and outputting a second voltage; a comparison module, wherein a first input terminal of the comparison module is connected to an output terminal of the first voltage sampling module to receive the first voltage, a second input terminal of the comparison module is connected to an output terminal of the second voltage sampling module to receive the second voltage, and an output terminal of the comparison module is used to output a comparison result obtained according to the first voltage and the second voltage; The first current is one of a reference current and a read current flowing through the bit line, and the second current is the other of the reference current and the read current.

2. The data reading circuit according to claim 1, characterized in that: The comparison module includes: a first latch, and two ends of the first latch are respectively connected to the first voltage sampling module and the second voltage sampling module.

3. The data reading circuit according to claim 2, characterized in that: The data reading circuit further includes: a switch module and a compensation load; The first end of the switch module is connected to the first input end of the comparison module, and the second end of the switch module is connected to the second input end of the comparison module; The input end of the switch module is used to access the reference current, and the input end of the switch module is also connected to the compensation load.

4. The data reading circuit according to claim 3, characterized in that: The first voltage sampling module includes: a first sampling resistor and a first sampling switch, and the second voltage sampling module includes a second sampling resistor and a second sampling switch; One end of the first sampling resistor is connected to the power supply voltage, the other end of the first sampling resistor is connected to the first end of the first sampling switch, and the other end of the first sampling resistor is also connected to the first current; The second end of the first sampling switch is connected to the first input end of the comparison module, and the control end of the first sampling switch is used to receive a sampling control signal; One end of the second sampling resistor is connected to the power supply voltage, the other end of the second sampling resistor is connected to the first end of the second sampling switch, and the other end of the second sampling resistor is also connected to the second current; The second end of the second sampling switch is connected to the second input end of the comparison module, and the control end of the second sampling switch is used to receive the sampling control signal; The sampling control signal is used to control the switching states of the first sampling switch and the second sampling switch.

5. The data reading circuit according to claim 4, characterized in that: The first voltage sampling module further includes a first current source, and the first voltage sampling module further includes a second current source; One end of the first current source is connected to the power supply voltage, and the other end of the first current source is connected to the first end of the first sampling switch; One end of the second current source is connected to the power supply voltage, and the other end of the second current source is connected to the first end of the second sampling switch.

6. The data reading circuit according to claim 5, characterized in that: The first latch is composed of two mutually coupled inverters, a first end of the first latch is connected to a second end of the first sampling switch, and a second end of the first latch is connected to a second end of the second sampling switch.

7. The data reading circuit according to claim 6, characterized in that: The comparison module further includes: a second latch, a first inverter, a second inverter and a gating switch; The input end of the first inverter is connected to the first end of the first latch and the second end of the first sampling switch, and the output end of the first inverter is connected to the first end of the gating switch; The input end of the second inverter is connected to the second end of the first latch and the second end of the second sampling switch, and the output end of the second inverter is connected to the second end of the gating switch; The output terminal of the gate switch is connected to the input terminal of the second latch.

8. The data reading circuit according to claim 4, characterized in that: The data reading circuit further includes a pre-charging module, and the pre-charging module includes a first pre-charging sub-module and a second pre-charging sub-module; One end of the first pre-charging submodule and one end of the second pre-charging submodule are respectively connected to the power supply voltage; The other end of the first pre-charging submodule is connected to the input end of the first voltage sampling module; The other end of the second pre-charging submodule is connected to the input end of the second voltage sampling module.

9. The data reading circuit according to claim 8, characterized in that: The data reading circuit further includes a first switch tube and a second switch tube; the switch module includes a first switch and a second switch; The first end of the first switch tube is connected to the input end of the first voltage sampling module, and the second end of the first switch tube is used to access the first current; The first end of the second switch tube is connected to the input end of the second voltage sampling module, and the second end of the second switch tube is used to access the second current; One end of the first switch is connected to the second end of the first switch tube, and the other end of the first switch is connected to the compensation load and a reference current generator included in the peripheral circuit of the memory respectively; One end of the second switch is connected to the second end of the second switch tube, and the other end of the second switch is connected to the compensation load and a reference current generator included in the peripheral circuit of the memory respectively.

10. The data reading circuit according to claim 9, characterized in that: The switch module further includes a third switch, and two ends of the third switch are respectively connected to one end of the first switch and one end of the second switch.

11. The data reading circuit according to claim 3, characterized in that: The compensation load includes any one or more of a compensation capacitor and an adjustable resistor.

12. The data reading circuit according to any one of claims 1 to 11, characterized in that: The memory is a NOR type memory, and the NOR type memory includes a plurality of storage units.

13. The data reading circuit according to any one of claims 1 to 11, characterized in that: The memory is a non-volatile memory device with a split floating gate, and the non-volatile memory device with a split floating gate includes a plurality of memory cell pairs, and the memory cell pairs include two memory cells, one of the two memory cells is connected to the first voltage sampling module, and the other of the two memory cells is connected to the second voltage sampling module.

14. A memory, characterized in that: The memory includes a plurality of memory cells and a peripheral circuit, each of the memory cells is connected to a bit line, and the peripheral circuit includes the data reading circuit according to any one of claims 1 to 3, and the data reading circuit is connected to the bit line.

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