Packaging structure of semiconductor device and semiconductor device

Abstract

The embodiment of the utility model provides a packaging structure of a semiconductor device and the semiconductor device. The packaging structure comprises a substrate; the electrode layer is located on one side of the substrate, the electrode layer comprises a plurality of annular electrode structures, the annular electrode structures are arranged in a concentric circle mode, and the annular electrode structures are mutually insulated; the heat dissipation layer is located between the electrode layer and the substrate, the heat dissipation layer comprises a plurality of annular conductive structures, and the orthographic projection, facing the substrate, of the annular conductive structures is at least partially overlapped with the orthographic projection, facing the substrate, of the annular electrode structure; and the annular conductive structure is electrically connected with the annular electrode structure. According to the invention, each part of the heat dissipation layer can be uniformly expanded in a high-temperature environment, and local high-strength wear of the substrate is avoided, so that the failure risk of the semiconductor device can be reduced, the safety, reliability and stability of the semiconductor device are improved, and the service life of the semiconductor device is prolonged.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a packaging structure of a semiconductor device and a semiconductor device. Background Art

[0002] With the development and progress of semiconductor device manufacturing technology, the requirements for the safety, reliability and stability of semiconductor devices are gradually increasing. For semiconductor devices that shut down quickly at high currents, they usually need to withstand high currents and high voltages, which will cause a lot of heat to be generated during the shutdown process, thus causing thermal deformation and thermal stress of semiconductor devices.

[0003] In traditional semiconductor devices, a metal buffer layer is usually set between the cathode layer and the chip to dissipate heat from the cathode metal layer and ensure the device's conductive performance. However, metal materials have a large thermal expansion coefficient and tend to expand laterally in a direction parallel to the chip in a high temperature environment and shrink when the temperature drops, causing the metal buffer layer and the chip surface to shift relative to each other during the device switching process, thereby causing wear on the chip and causing chip failure, affecting the safety, reliability and stability of semiconductor devices and reducing the service life of semiconductor devices. Utility Model Content

[0004] Based on this, the packaging structure of the semiconductor device and the semiconductor device provided in the embodiments of the present application can enable uniform thermal expansion of the heat dissipation layer in a high-temperature environment, thereby avoiding local high-intensity wear on the substrate, thereby reducing the failure risk of the semiconductor device, improving the safety, reliability and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0005] According to a first aspect of an embodiment of the present application, a semiconductor device packaging structure is provided, including:

[0006] substrate;

[0007] An electrode layer, the electrode layer is located on one side of the substrate, the electrode layer includes a plurality of annular electrode structures, the annular electrode structures are arranged in a concentric circle manner, and the annular electrode structures are insulated from each other;

[0008] A heat dissipation layer, wherein the heat dissipation layer is located between the electrode layer and the substrate, and the heat dissipation layer includes a plurality of annular conductive structures, wherein the orthographic projection of the annular conductive structure toward the substrate at least partially overlaps with the orthographic projection of the annular electrode structure toward the substrate, and the annular conductive structure is electrically connected to the annular electrode structure.

[0009] In one embodiment, the heat dissipation layer includes a plurality of insulating structures, and the insulating structures are located between adjacent annular conductive structures.

[0010] In one of the embodiments, in the thickness direction of the substrate, the size of the insulating structure is smaller than or equal to the size of the annular conductive structure.

[0011] In one embodiment, the insulating structure is ring-shaped.

[0012] In one of the embodiments, the material of the insulating structure includes organic material.

[0013] In one of the embodiments, a difference between a thermal expansion coefficient of the heat dissipation layer and a thermal expansion coefficient of the substrate is smaller than a preset difference.

[0014] In one of the embodiments, the thermal expansion coefficient of each of the annular conductive structures in the heat dissipation layer is negatively correlated with the radius of the annular conductive structure.

[0015] In one of the embodiments, in the radial direction of the concentric circles, the size of the annular conductive structure is larger than the size of the corresponding annular electrode structure.

[0016] According to a second aspect of an embodiment of the present application, a semiconductor device is provided, including:

[0017] A packaging structure of a semiconductor device as described in any one of the first aspects above.

[0018] In one embodiment, the semiconductor device comprises:

[0019] chip;

[0020] an anode layer, the anode layer being located on one side of the chip;

[0021] A heat dissipation layer, the heat dissipation layer is located at a side of the chip away from the anode layer, and the heat dissipation layer includes a plurality of annular conductive structures;

[0022] A cathode layer, wherein the cathode layer is located on a side of the heat dissipation layer away from the chip, the cathode layer comprises a plurality of annular electrode structures, the annular electrode structures are arranged in a concentric circle manner, the annular electrode structures are insulated from each other, the orthographic projection of the annular conductive structure toward the chip at least partially overlaps with the orthographic projection of the annular electrode structure toward the chip, and the annular conductive structure is electrically connected to the annular electrode structure.

[0023] The semiconductor device packaging structure and semiconductor device provided by the embodiment of the present application, by setting the annular conductive structure and the annular electrode structure correspondingly, the heat dissipation layer can dissipate heat for the electrode layer, and at the same time, the electrode layer and the substrate can be electrically connected through the heat dissipation layer, thereby ensuring the electrical performance of the semiconductor device. In addition, by setting the heat dissipation layer as a plurality of concentrically arranged annular conductive structures, the cumulative effect of the thermal expansion of the heat dissipation layer can be suppressed, and the thermal expansion of the central area of ​​the heat dissipation layer can be avoided from acting on the edge of the heat dissipation layer, so that the heat dissipation layer can be uniformly thermally expanded in a high temperature environment, avoiding local high-intensity wear on the substrate, thereby reducing the failure risk of the semiconductor device, improving the safety, reliability and stability of the semiconductor device, and extending the service life of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic structural diagram of a semiconductor device packaging structure provided in an embodiment of the present application;

[0026] Figure 2 A schematic structural diagram of a cathode layer of a packaging structure of a semiconductor device provided in an embodiment of the present application;

[0027] Figure 3 A schematic structural diagram of a heat dissipation layer of a semiconductor device packaging structure provided in an embodiment of the present application;

[0028] Figure 4 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0029] Figure 5 A schematic structural diagram of another semiconductor device provided in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] 100-substrate, 200-electrode layer, 201-annular electrode structure, 202-electrode comb, 300-heat dissipation layer, 301-annular conductive structure, 302-insulating structure, 303-first heat dissipation structure, 304-second heat dissipation structure, 400-anode tube shell upper cover, 401-copper electrode, 402-copper flange, 500-cathode tube shell base, 501-cathode upper flange, 502-ceramic ring, 503-gate disc spring assembly, 504-gate lead ring, 505-cathode lower flange, 506-cathode copper electrode body, H1-dimensions of the annular conductive structure in the thickness direction of the substrate, H2-dimensions of the insulating structure in the thickness direction of the substrate. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of the stated features, wholes, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] It should be noted that in traditional semiconductor devices, a metal layer is usually arranged between the semiconductor substrate and the electrode layer as a heat dissipation layer. During the large current rapid shutdown process of the semiconductor device, the electrode layer is dissipated by the heat dissipation layer to prevent the semiconductor device from burning. At the same time, the current transmission effect between the electrode layer and the semiconductor substrate can be guaranteed, thereby improving the electrical performance of the semiconductor device.

[0038] However, in traditional semiconductor devices, the heat dissipation layer is usually a complete metal film layer covering the surface of the semiconductor substrate, and the cathode layer in traditional semiconductor devices is usually composed of multiple concentrically arranged cathode rings, and one cathode ring includes multiple cathode comb structures. During the operation of the semiconductor device, the cathode layer generates heat, and the metal heat dissipation layer absorbs the heat released by the cathode layer to increase the temperature, and thermal expansion occurs in the heat absorption area, so that the metal heat dissipation layer thermally expands on the surface of the semiconductor chip along the radial direction of the cathode layer. As a whole, the thermal expansion of the metal heat dissipation layer of the inner circle will continue to accumulate with the increase of the radius, causing the thermal expansion of the metal heat dissipation layer of the outer circle to be greater than the thermal expansion of the metal heat dissipation layer of the inner circle. Therefore, the relative displacement between the edge of the metal heat dissipation layer and the edge of the semiconductor chip is large. When the temperature of the heat dissipation layer changes, it is easy to cause the edge of the metal heat dissipation layer to frequently rub against the edge area of ​​the semiconductor chip, resulting in an increased risk of wear of the semiconductor chip, resulting in an increased risk of failure of the semiconductor chip, which in turn affects the safety, reliability and stability of the semiconductor device and reduces the service life of the semiconductor device.

[0039] like Figure 1 As shown, an embodiment of the present application provides a packaging structure of a semiconductor device, including: a substrate 100, an electrode layer 200 and a heat dissipation layer 300. The electrode layer 200 is located on one side of the substrate 100, and the electrode layer 200 includes a plurality of annular electrode structures 201, each of which is arranged in a concentric circle manner, and each of the annular electrode structures 201 is insulated from each other; the heat dissipation layer 300, the heat dissipation layer 300 is located between the electrode layer 200 and the substrate 100, and the heat dissipation layer 300 includes a plurality of annular conductive structures 301, the orthographic projection of the annular conductive structure 301 toward the substrate 100 at least partially overlaps with the orthographic projection of the annular electrode structure 201 toward the substrate 100, and the annular conductive structure 301 is electrically connected to the annular electrode structure 201.

[0040] like Figure 2 As shown, the annular electrode structure 201 includes a plurality of electrode comb bars 202 , and the electrode comb bars 202 are insulated from each other.

[0041] For example, the material of the substrate 100 may include silicon. The thermal conductivity of the heat dissipation layer 300 is greater than or equal to 100 W / (m·°C), and the thermal expansion coefficient of the heat dissipation layer 300 is less than or equal to 6×10 -6 / ℃, the conductivity of the heat dissipation layer 300 is greater than or equal to 1×10 7S / m, to meet the requirements of the flow and heat dissipation of the electrode layer 200. The material of the heat dissipation layer 300 may include a single material, such as molybdenum, molybdenum-copper alloy, tungsten, tungsten-copper alloy, etc., and the material of the heat dissipation layer 300 may include a composite material, such as aluminum diamond, copper diamond, etc. In the case where the material of the heat dissipation layer 300 includes a composite material, the thermal expansion coefficient of the heat dissipation layer 300 may be changed by adjusting the material type and material content of the composite material.

[0042] For example, the thermal expansion coefficient of the heat dissipation layer 300 can be determined according to the frequency of use of different annular electrode structures 201 in the electrode layer 200 and the size of the conduction current, so that the thermal expansion coefficient of the annular conductive structure 301 corresponding to the annular electrode structure 201 with large current and frequent switching is smaller, thereby further improving the uniformity of the thermal expansion of different positions of the heat dissipation layer 300 and reducing the risk of damage to semiconductor devices.

[0043] The packaging structure of the semiconductor device provided in the embodiment of the present application, by setting the annular conductive structure 301 corresponding to the annular electrode structure 201, the heat dissipation layer 300 can dissipate heat for the electrode layer 200, and at the same time, the electrode layer 200 and the substrate 100 can be electrically connected through the heat dissipation layer 300, thereby ensuring the electrical performance of the semiconductor device. In addition, by setting the heat dissipation layer 300 as a plurality of concentrically arranged annular conductive structures 301, the cumulative effect of the thermal expansion of the heat dissipation layer 300 can be suppressed, and the thermal expansion of the central area of ​​the heat dissipation layer 300 can be prevented from acting on the edge of the heat dissipation layer 300, so that the heat dissipation layer 300 can be uniformly thermally expanded in a high temperature environment, avoiding local high-intensity wear on the substrate 100, thereby reducing the failure risk of the semiconductor device, improving the safety, reliability and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0044] like Figure 1 and Figure 3 As shown, in some feasible implementations, the heat dissipation layer 300 includes a plurality of insulating structures 302 , and the insulating structures 302 are located between adjacent annular conductive structures 301 .

[0045] Exemplarily, the shape of the insulating structure 302 and the setting position of the insulating structure 302 can be determined according to the thermal expansion of the annular conductive structure 301. When the thermal expansion of the annular conductive structure 301 is large, the insulating structure 302 can be correspondingly set so that, under the limiting effect of the insulating structure 302, the thermal expansion of different annular conductive structures 301 in the same heat dissipation layer 300 at different positions of the same annular conductive structure 301 is the same, thereby improving the uniformity of the thermal expansion of the heat dissipation layer 300 and avoiding local high-intensity wear of the heat dissipation layer 300 on the substrate 100.

[0046] The packaging structure of the semiconductor device provided in the embodiment of the present application can provide an insulating structure 302 between adjacent annular conductive structures 301, so that when the annular conductive structure 301 undergoes thermal expansion, the insulating structure 302 can block the expansion of the annular conductive structure 301, thereby playing a limiting role. At the same time, the insulating structure 302 can absorb heat from the annular conductive structure 301, further accelerate the heat dissipation efficiency of the heat dissipation layer 300, and reduce the temperature change of the annular conductive structure 301, thereby further reducing the thermal expansion of the annular conductive structure 301, reducing the relative displacement between the heat dissipation layer 300 and the substrate 100, reducing the wear effect of the heat dissipation layer 300 on the substrate 100, improving the uniformity of the relative displacement of the heat dissipation layer 300 to the substrate 100, avoiding local high-intensity wear on the substrate 100, thereby reducing the failure risk of the semiconductor device, improving the safety, reliability and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0047] like Figure 1 As shown, in some feasible implementations, in the thickness direction of the substrate 100 , the size H2 of the insulating structure 302 is smaller than or equal to the size H1 of the annular conductive structure 301 .

[0048] The packaging structure of the semiconductor device provided in the embodiment of the present application can avoid the insulating structure 302 being too high, which would cause poor contact between the annular conductive structure 301 and the annular electrode structure 201, by setting the size H2 of the insulating structure 302 to be less than or equal to the size H1 of the annular conductive structure 301. This can improve the flow effect between the electrode layer 200 and the substrate 100, and further improve the electrical performance of the semiconductor device, and improve the reliability, stability and safety of the semiconductor device.

[0049] like Figure 3 As shown, in some possible implementations, the insulating structure 302 is ring-shaped.

[0050] Exemplarily, the annular insulating structure 302 may fill the entire space between adjacent annular conductive structures 301 , so as to enhance the limiting effect of the insulating structure 302 on the annular conductive structure 301 .

[0051] The packaging structure of the semiconductor device provided in the embodiment of the present application, by providing an annular insulating structure 302 between adjacent annular conductive structures 301, can limit the thermal expansion of the annular conductive structure 301 through the annular insulating structure 302, can improve the uniformity of the limiting effect of the insulating structure 302 on the annular conductive structure 301, avoid different limiting effects and heat dissipation effects of different insulating structures 302 formed on one side of the same annular conductive structure 301, further cause different thermal expansion amounts at different positions on the same annular conductive structure 301, thereby aggravating the non-uniformity of the wear of the annular conductive structure 301 on the substrate 100. Therefore, the limiting effect of the insulating structure 302 can be improved, the uniformity of the thermal expansion amount of the same annular conductive structure 301 can be improved, the uniformity of the thermal expansion amount of the heat dissipation layer 300 can be further improved, and the heat dissipation layer 300 can be avoided from forming local high-intensity wear on the substrate 100, thereby improving the reliability, safety and stability of the semiconductor device, reducing the risk of damage to the semiconductor device, and extending the service life of the semiconductor device.

[0052] In some feasible implementations, the material of the insulating structure 302 includes an organic material.

[0053] Exemplarily, the high temperature resistance of the material of the insulating structure 302 is greater than or equal to 150° C., and the material of the insulating structure 302 has a smaller elastic modulus and a higher fracture toughness. The material of the insulating structure 302 may include silicone rubber, PI, PEEK, and the like.

[0054] The packaging structure of the semiconductor device provided in the embodiment of the present application adopts organic materials to form the insulating structure 302, which can enhance the high temperature resistance of the insulating structure 302, avoid the melting of the insulating structure 302 at high temperature, and further cause the deformation of the annular conductive structure 301. At the same time, the insulating structure 302 with strong toughness and not easy to deform can also play a supporting and blocking role for the annular conductive structure 301, thereby effectively reducing the thermal expansion of the annular conductive structure 301, reducing the relative displacement between the annular conductive structure 301 and the substrate 100, and further reducing the wear of the annular conductive structure 301 on the substrate 100 during the heat dissipation process, thereby enhancing the reliability, safety and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0055] In some feasible implementations, the difference between the thermal expansion coefficient of the heat dissipation layer 300 and the thermal expansion coefficient of the substrate 100 is less than a preset difference.

[0056] For example, the material of the substrate 100 may be silicon, and the thermal expansion coefficient of silicon is about 2.5×10 -6 / ℃, the thermal expansion coefficient of the annular conductive structure 301 should be less than or equal to 6×10 -6 / ℃.

[0057] It should be noted that at the same temperature, materials with larger thermal expansion coefficients have larger thermal expansion amounts. When the difference between the thermal expansion coefficients of the heat dissipation layer 300 and the substrate 100 is too large, the relative displacement between the annular conductive material 301 in the heat dissipation layer 300 and the substrate 100 will be too large, resulting in an increase in the wear area corresponding to a temperature change, thereby increasing the risk of damage to the semiconductor chip, affecting the reliability, safety and stability of the semiconductor device, and shortening the service life of the semiconductor device.

[0058] The packaging structure of the semiconductor device provided in the embodiment of the present application can make the annular conductive structure 301 and the substrate 100 thermally expand in the same direction and have similar thermal expansion amounts by reducing the difference between the thermal expansion coefficient of the heat dissipation layer 300 and the thermal expansion coefficient of the substrate 100, thereby reducing the relative displacement between the annular conductive structure 301 and the substrate 100, and further reducing the wear of the annular conductive structure 301 on the substrate 100, reducing the risk of damage to the semiconductor chip, improving the reliability, safety and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0059] In some feasible implementations, the thermal expansion coefficient of each annular conductive structure 301 in the heat dissipation layer 300 is negatively correlated with the radius of the annular conductive structure 301 .

[0060] It should be noted that, in the process of heat dissipation of the electrode layer 200 through the heat dissipation layer 300, the thermal expansion amount of the annular conductive structure 301 with a smaller radius will be superimposed on the annular conductive structure 301 with a larger radius, so that the thermal expansion amount of the annular conductive structure 301 with a larger radius is further increased on the basis of the thermal expansion amount formed by the material being heated. Therefore, under the same temperature and the same thermal expansion coefficient of the annular conductive structure 301, the thermal expansion amount of the annular conductive structure 301 increases with the increase of the radius of the annular conductive structure 301.

[0061] The packaging structure of the semiconductor device provided in the embodiment of the present application can reduce the thermal expansion coefficient of the annular conductive structure 301 with a larger radius, so that the thermal expansion of the annular conductive structure 301 with a larger radius is adapted to the accumulated thermal expansion of the annular conductive structure 301 with a smaller radius, so that the total deformation of the annular conductive structures 301 with different radii is similar, so that the relative displacement between each annular conductive structure 301 in the heat dissipation layer 300 and the substrate 100 can be the same, and the thermal deformation mismatch problem between the central area and the edge area of ​​the heat dissipation layer 300 can be solved, and the uniformity of the wear of the substrate 100 at various locations in the heat dissipation layer 300 can be further improved, thereby reducing the risk of damage to the semiconductor chip, improving the reliability, safety and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0062] In some feasible implementations, in the radial direction of the concentric circles, the size of the annular conductive structure 301 is larger than the size of the corresponding annular electrode structure 201 .

[0063] The method for preparing a semiconductor device provided in the embodiment of the present application can avoid the large difference between the thermal expansion of the annular electrode structure 201 and the thermal expansion of the annular conductive structure 301 during the operation of the semiconductor device by forming a large-sized annular electrode structure 201, which causes the annular electrode structure 201 and the annular conductive structure 301 to be misaligned, resulting in a disconnection between the electrode layer 200 and the substrate 100, and poor flow quality between the annular electrode structure 201 in the electrode layer 200 and the substrate 100, thereby suppressing the problem of poor contact of the semiconductor device. The flow effect of the annular conductive structure 301 on the annular electrode structure 201 and the substrate 100 can be guaranteed, the electrical performance of the semiconductor device can be improved, the risk of damage to the semiconductor chip can be reduced, the reliability, safety and stability of the semiconductor device can be improved, and the service life of the semiconductor device can be extended.

[0064] like Figure 4 As shown, a second aspect of an embodiment of the present application provides a semiconductor device, including: a packaging structure of a semiconductor device as described in any one of the first aspects above.

[0065] The semiconductor device provided in the embodiment of the present application, by setting the annular conductive structure 301 corresponding to the annular electrode structure 201, the heat dissipation layer 300 can dissipate heat for the electrode layer 200, and at the same time, the electrode layer 200 and the substrate 100 can be electrically connected through the heat dissipation layer 300, thereby ensuring the electrical performance of the semiconductor device. In addition, by setting the heat dissipation layer 300 as a plurality of concentrically arranged annular conductive structures 301, the cumulative effect of the thermal expansion of the heat dissipation layer 300 can be suppressed, and the thermal expansion of the central area of ​​the heat dissipation layer 300 can be prevented from acting on the edge of the heat dissipation layer 300, so that the heat dissipation layer 300 can be uniformly thermally expanded in a high temperature environment, avoiding local high-intensity wear on the substrate 100, thereby reducing the failure risk of the semiconductor device, improving the safety, reliability and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0066] like Figure 5As shown, in some feasible implementations, the semiconductor device includes: a chip 102, an anode layer and a cathode layer. The anode layer is located on one side of the chip 102; a heat dissipation layer 300, the heat dissipation layer 300 is located on the side of the chip 102 away from the anode layer, and the heat dissipation layer 300 includes a plurality of annular conductive structures 301; a cathode layer, the cathode layer is located on the side of the heat dissipation layer 300 away from the chip 102, and the cathode layer includes a plurality of annular electrode structures 201, each annular electrode structure 201 is arranged in a concentric circle manner, each annular electrode structure 201 is insulated from each other, the positive projection of the annular conductive structure 301 toward the chip 102 is at least partially overlapped with the positive projection of the annular electrode structure 201 toward the chip 102, and the annular conductive structure 301 is electrically connected to the annular electrode structure 201.

[0067] Exemplarily, the chip 102 may include a whole wafer silicon-based chip, and the size may be 2 inches, 3 inches, 4 inches, 6 inches, and 8 inches, etc., and the thickness may range from 0.2 mm to 2 mm. The chip 102 may be divided into an active area in the central area and a terminal area in the edge area, wherein the active area is the main flow and heat generation area, and the terminal area is the main insulation area.

[0068] Exemplarily, the heat dissipation layer 300 includes a first heat dissipation structure 303 corresponding to the cathode layer and a second heat dissipation structure 304 corresponding to the anode layer, wherein at least the first heat dissipation structure 303 is annular. The thickness of the first heat dissipation structure 303 and the second heat dissipation structure 304 ranges from 0.5 mm to 5 mm, and the flatness is less than 5 μm, so that the pressure acting on the surface of the chip 102 when under pressure is more uniform, and the chip 102 is prevented from being broken due to excessive pressure locally.

[0069] Exemplarily, the semiconductor device further includes an anode tube shell upper cover 400 and a cathode tube shell base 500, wherein the anode tube shell upper cover 400 is located on the side of the anode layer away from the chip 102, and the cathode tube shell base 500 is located on the side of the cathode layer away from the chip 102. The material of the anode tube shell upper cover 400 includes oxygen-free copper, and the anode tube shell upper cover 400 includes a copper electrode 401 in the central area and a copper flange 403 in the edge area, and the copper electrode 401 and the copper flange are interconnected by high-temperature welding. The material of the cathode tube shell base 500 includes oxygen-free copper and alumina ceramic, and the cathode tube shell base 500 includes a cathode upper flange 501, a ceramic ring 502, a gate disc spring assembly 503, a gate lead ring 504, a cathode lower flange 505 and a cathode copper electrode body 506, and all of the above parts are interconnected by high-temperature welding. Among them, the ceramic ring 502 is used for high-voltage insulation so that the creepage distance and electrical clearance meet the high-voltage requirements of 8.5kV and above, the cathode copper electrode body 506 is used for current flow and heat dissipation, and each flange structure is used for interconnection and sealing. The gate disc spring assembly 503 is formed by stacking disc springs and gaskets, has a certain elasticity, and can produce a certain displacement under pressure, which is used to lead out the gate of the chip 102. The anode tube shell cover 400 and the cathode tube shell base 500 are interconnected by a cold pressure welding process to achieve the tube shell sealing of the semiconductor device, providing a closed space with a protective function for the chip 102. The interior is evacuated and filled with nitrogen to isolate the external water and oxygen environment to prevent the external environment changes from affecting the performance of the chip 102.

[0070] The semiconductor device provided in the embodiment of the present application, by setting the annular conductive structure 301 corresponding to the annular cathode structure in the cathode layer, enables the heat dissipation layer 300 to dissipate heat for the electrode layer 200, and at the same time enables the electrode layer 200 and the substrate 100 to be electrically connected through the heat dissipation layer 300, thereby ensuring the electrical performance of the semiconductor device. In addition, by setting the heat dissipation layer 300 as a plurality of concentrically arranged annular conductive structures 301, the cumulative effect of the thermal expansion of the heat dissipation layer 300 can be suppressed, and the thermal expansion of the central area of ​​the heat dissipation layer 300 can be prevented from acting on the edge of the heat dissipation layer 300, so that the heat dissipation layer 300 can be uniformly thermally expanded in a high temperature environment, avoiding local high-intensity wear on the substrate 100, thereby reducing the failure risk of the semiconductor device, improving the safety, reliability and stability of the semiconductor device, and extending the service life of the semiconductor device.

[0071] In the description of this specification, the descriptions with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc., mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0072] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device packaging structure, characterized in that: include: substrate; An electrode layer, the electrode layer is located on one side of the substrate, the electrode layer includes a plurality of annular electrode structures, the annular electrode structures are arranged in a concentric circle manner, and the annular electrode structures are insulated from each other; A heat dissipation layer, wherein the heat dissipation layer is located between the electrode layer and the substrate, and the heat dissipation layer includes a plurality of annular conductive structures, wherein the orthographic projection of the annular conductive structure toward the substrate at least partially overlaps with the orthographic projection of the annular electrode structure toward the substrate, and the annular conductive structure is electrically connected to the annular electrode structure.

2. The semiconductor device packaging structure according to claim 1, characterized in that: The heat dissipation layer includes a plurality of insulating structures, and the insulating structures are located between adjacent annular conductive structures.

3. The semiconductor device packaging structure according to claim 2, characterized in that: In the thickness direction of the substrate, the size of the insulating structure is smaller than or equal to the size of the annular conductive structure.

4. The semiconductor device packaging structure according to claim 2, characterized in that: The insulating structure is ring-shaped.

5. The semiconductor device packaging structure according to claim 2, characterized in that: The material of the insulating structure includes organic material.

6. The semiconductor device packaging structure according to claim 1, characterized in that: A difference between a thermal expansion coefficient of the heat dissipation layer and a thermal expansion coefficient of the substrate is smaller than a preset difference.

7. The semiconductor device packaging structure according to claim 1, characterized in that: The thermal expansion coefficient of each of the annular conductive structures in the heat dissipation layer is negatively correlated with the radius of the annular conductive structure.

8. The semiconductor device packaging structure according to claim 1, characterized in that: In the radial direction of the concentric circles, the size of the annular conductive structure is larger than the size of the corresponding annular electrode structure.

9. A semiconductor device, characterized in that include: The semiconductor device packaging structure according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that include: chip; an anode layer, the anode layer being located on one side of the chip; A heat dissipation layer, the heat dissipation layer is located at a side of the chip away from the anode layer, and the heat dissipation layer includes a plurality of annular conductive structures; A cathode layer, wherein the cathode layer is located on a side of the heat dissipation layer away from the chip, the cathode layer comprises a plurality of annular electrode structures, the annular electrode structures are arranged in a concentric circle manner, the annular electrode structures are insulated from each other, the orthographic projection of the annular conductive structure of the semiconductor device toward the chip at least partially overlaps with the orthographic projection of the annular electrode structure toward the chip, and the annular conductive structure is electrically connected to the annular electrode structure.

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