Packaging structure of gallium nitride device
By designing a gallium nitride device package structure that is compatible with the existing 4-pin TO247 package structure of silicon devices, the problem of replacement difficulties and poor performance is solved, and direct replacement and performance improvement with silicon devices is achieved.
Patent Information
- Application Number
- CN202420604571.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-26
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2034-03-26
AI Technical Summary
In the prior art, the package structure of gallium nitride devices is difficult to compatible with the 4-pin TO247 package structure of existing silicon devices, resulting in difficult replacement and poor performance.
A package structure for gallium nitride devices is designed, using a TO247 package frame, including drain pin, source pin, Kelvin source pin and gate pin, and is implemented through a Cascode module and plastic packaging body, which is directly replaced with the 4-pin TO247 package structure of existing silicon devices.
Direct replacement with existing silicon devices is achieved, reducing manufacturing costs and improving performance, especially in high-frequency and high-voltage applications.
Smart Images
Figure CN222673034U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and in particular to a packaging structure of a gallium nitride device. Background Art
[0002] TO247 is a small-outline plug-in electronic device packaging structure. "TO" stands for "Transistor Outline" and "247" stands for the size of the package. It is commonly used in semiconductor devices in medium-high voltage and high current application scenarios, such as high-power silicon-based metal-oxide semiconductor field-effect transistors (MOSFET or MOS for short), silicon carbide MOSFET, silicon IGBT, etc. According to the number of pins, the TO247 package structure includes 3 pins and 4 pins. Taking silicon MOS as an example, its 3-pin TO247 package structure includes a lead frame and pins. The silicon MOS chip is mounted on the lead frame, and the pins are electrically connected to the gate G, drain D and source S of the silicon MOS chip respectively. When used, its drive circuit and power circuit share the source S pin. Figure 1 4 is a schematic diagram of a TO247 package structure with 4 pins in the prior art. Figure 1 As shown in the figure, the 4-pin TO247 package has an additional Kelvin source pin KS (Kelvin Source) compared to the 3-pin TO247 package, also known as the auxiliary source, which can decouple the drive circuit and the power circuit when applied. The pin sequence is drain D, source S, Kelvin source pin KS and gate G, where the drain D pin is connected to the lead frame, and the other three pins are electrically connected to the silicon MOSFET chip by wire bonding.
[0003] Gallium nitride (GaN) is a third-generation semiconductor material. Because its bandgap width is greater than 2.2eV, GaN is also called a wide bandgap semiconductor material. In addition to a wider bandgap, it also has advantages such as high breakdown electric field (more resistant to high voltage), high electron saturation drift rate (greater power output) and good temperature resistance. Therefore, gallium nitride materials are also widely used in power semiconductor devices. Figure 2 , Figure 2 It is a circuit schematic diagram of a GaN Cascode module (gallium nitride common source and common gate cascade structure) in the prior art, such as Figure 2As shown, the GaN Cascode module 200 includes a cascaded D-mode (depletion mode) GaN HEMT (High Electron Mobility Transistors) chip 210 and a low-voltage enhanced silicon MOS chip 220, the first drain of the D-mode GaN HEMT chip 210 serves as the first power supply terminal D of the GaN Cascode structure 200, the first source of the D-mode GaN HEMT chip 210 is electrically connected to the second drain of the silicon MOS chip 220, the first gate of the D-mode GaN HEMT chip 210 is electrically connected to the second source of the silicon MOS chip 220, and serves as the second power supply terminal S of the GaN Cascode structure 200, and the second gate of the silicon MOS chip 11 serves as the control terminal G of the GaN Cascode structure 200. The GaN Cascode module 200 has the characteristics of large output impedance and can be applied to high voltage and large current (such as 650V, 60A) scenarios.
[0004] In terms of production cost, the same specification of silicon MOS or silicon carbide MOS devices are much higher than CaN Cascode, and the high-frequency performance is slightly worse than CaN Cascode. The switching loss of the driver is also larger than CaN Cascode, and the operating frequency is also subject to certain restrictions. Referring to the advantages of the aforementioned 4-pin TO247 package structure, it is necessary to provide a gallium nitride device that can be compatible with the 4-pin TO247 package structure of existing silicon devices. Utility Model Content
[0005] In view of the technical problems existing in the prior art, the utility model proposes a packaging structure of a gallium nitride device, which can directly replace the silicon device of the existing 4-pin TO247 packaging structure.
[0006] In order to solve the above technical problems, the utility model provides a packaging structure of a gallium nitride device, comprising a TO247 packaging frame, a Cascode module and a plastic package, wherein the TO247 packaging frame comprises a frame body and a drain pin, a source pin, a Kelvin source pin and a gate pin arranged in sequence, wherein the source pin is integrally connected to the frame body, and the drain pin and the gate pin are separated from the frame body; the Cascode module is composed of a D-Mode HEMT chip and a silicon MOS chip cascaded and placed on the front of the frame body; the first drain region of the D-Mode HEMT chip is electrically connected to the drain pin by wire bonding; the first gate region of the D-Mode HEMT chip is electrically connected to the frame body by wire bonding; the first source region of the D-Mode HEMT chip is electrically connected to the second drain region of the silicon MOS chip; the second gate region of the silicon MOS chip is electrically connected to the gate pin by wire bonding, and the second source region of the silicon MOS chip is electrically connected to the frame body by wire bonding; the back of the frame body and the pins are exposed outside the plastic package.
[0007] Optionally, the Kelvin source pin is integrally connected to the frame body.
[0008] Optionally, the second source region of the silicon MOS chip is electrically connected to the Kelvin source pin by wire bonding.
[0009] Optionally, when the Kelvin source pin is separated from the frame body, the second source region of the silicon MOS chip is electrically connected to the Kelvin source pin by wire bonding; or, the frame body is electrically connected to the Kelvin source pin by wire bonding.
[0010] Optionally, the frame body includes a hollow pin placement area extending into the interior along the edge, and the Kelvin source pin extends into the pin placement area inside the frame body and is electrically connected to the second source area of the silicon MOS chip or the frame body by wire bonding.
[0011] Optionally, the D-Mode HEMT chip is mounted on the front side of the frame body, and the first drain region, the first source region and the first gate region of the D-Mode HEMT chip are placed on the upper surface of the D-Mode HEMT chip; the second drain region of the silicon MOS chip is placed on the lower surface of the silicon MOS chip, and the second source region and the second gate region of the silicon MOS chip are placed on the upper surface of the silicon MOS chip; the lower surface of the silicon MOS chip is mounted on the first source region of the D-Mode HEMT chip, and the second drain region on the lower surface of the silicon MOS chip is electrically connected to the first source region of the D-Mode HEMT chip.
[0012] Optionally, the D-Mode HEMT chip and the substrate are mounted in parallel on the front side of the frame body, and the first drain region, the first source region and the first gate region of the D-Mode HEMT chip are placed on the upper surface of the D-Mode HEMT chip; the substrate at least includes a first conductive region, the second drain region of the silicon MOS chip is placed on the lower surface of the silicon MOS chip, the second source region and the second gate region of the silicon MOS chip are placed on the upper surface of the silicon MOS chip, and the lower surface of the silicon MOS chip is mounted on the first conductive region of the substrate, so that the second drain region on the lower surface of the silicon MOS chip is electrically connected to the first conductive region of the substrate; the first source region of the D-Mode HEMT chip is electrically connected to the first conductive region by wire bonding.
[0013] Optionally, the Cascode module further includes a lifting unit, which is disposed on the substrate and electrically connected to the D-Mode HEMT chip and / or the silicon MOS chip by wire bonding.
[0014] Optionally, the D-Mode HEMT chip has a plurality of first drain regions; and / or, the D-Mode HEMT chip has a plurality of first gate regions; and / or, the silicon MOS chip has a plurality of second source regions.
[0015] The pin sequence of the gallium nitride device provided by the utility model is the same as the pin sequence of the existing SiC MOS and Si MOS structures, thereby realizing a direct pin-to-pin replacement with the existing mainstream TO247-4L power device. The GaN Cascode module of the utility model uses a low-voltage MOS as a switching device. Compared with SiC MOS or SiMOS of the same specification, the capacitance is relatively small, the switching loss is relatively low, the switching frequency limit is small, and the high-frequency performance of GaN HEMT is better; the gallium nitride device provided by the utility model provides a Kelvin source pin, which effectively improves the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Below, the preferred embodiments of the present invention will be further described in detail with reference to the accompanying drawings, wherein:
[0017] Figure 1 It is a schematic diagram of a 4-pin TO247 package structure in the prior art;
[0018] Figure 2 It is a circuit schematic diagram of a GaN Cascode module (gallium nitride common source and common gate cascade structure) in the prior art;
[0019] Figure 3 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the first embodiment of the utility model;
[0020] Figure 4 is an enlarged view of the layout of the GaN Cascode module 200 inside the package according to one embodiment of the utility model;
[0021] Figure 5 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the second embodiment of the utility model;
[0022] Figure 6 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the third embodiment of the present utility model;
[0023] Figure 7 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the fourth embodiment of the utility model;
[0024] Figure 8 is an enlarged view of the horizontal parallel layout of the GaN Cascode module 200 according to one embodiment of the utility model;
[0025] Fig. 9 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the fifth embodiment of the present utility model;
[0026] Fig.10 is a schematic diagram of the internal structure of the package of the gallium nitride device according to the sixth embodiment of the present utility model;
[0027] Fig.11 is a schematic diagram of a GaN Cascode module according to Embodiment 7 of the present utility model;
[0028] Fig.12 is a schematic diagram of the internal structure of the package of the gallium nitride device according to the seventh embodiment of the present utility model;
[0029] Fig.13 is a flow chart of a method for manufacturing a packaging structure of a gallium nitride device according to an embodiment of the utility model; and
[0030] Fig.14 It is a schematic diagram of a packaging frame structure according to an embodiment of the utility model. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0032] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described in sufficient detail below so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application. In addition, the various structural diagrams in the various diagrams in the present application are not drawn in proportion to the actual size of the device, but are only used to illustrate the composition and positional relationship of the structure.
[0033] The utility model provides a packaging structure of a gallium nitride device, which adopts a 4-pin TO247 packaging method and can directly replace the existing 4-pin TO247 packaged silicon MOS when applied. Compared with silicon MOS of the same specification, it has lower manufacturing cost and better performance.
[0034] Embodiment 1
[0035] Figure 3 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the first embodiment of the utility model. In this embodiment, the gallium nitride device is a GaN Cascode, and the packaging structure includes a TO247 packaging frame 100, a GaN Cascode module 200 and a plastic package (not shown in the figure). Among them, the TO247 packaging frame 100 includes a frame body 101 and four pins 102, which are a drain pin D, a source pin S, a Kelvin source pin KS and a gate pin G arranged in sequence, wherein the source pin S and the Kelvin source pin KS are integrally connected to the metal backplane of the frame body 101, and the drain pin D and the gate pin G are separated from the frame body 101.
[0036] The GaN Cascode module 200 in the first embodiment is composed of a D-Mode HEMT chip 210 and a silicon MOS chip 220 cascaded and stacked on the front of the frame body 101. Figure 4 , Figure 4 It is an enlarged view of the layout of the GaN Cascode module 200 inside the package according to an embodiment of the utility model. Among them, the first drain region D1, the first gate region G1 and the first source region S1 of the D-Mode HEMT chip 210 are respectively located on the upper surface of the chip, the second drain region D2 (shown in the figure) of the silicon MOS chip 220 is located on the lower surface of the chip, and the second gate region G2 and the second source region S2 of the silicon MOS chip 220 are respectively located on the upper surface of the chip. In this embodiment, the upper surface of the D-Mode HEMT chip 210 includes a plurality of first drain regions D1 with smaller areas, a plurality of first gate regions G1 with smaller areas and a first source region S1 with a larger area, the silicon MOS chip 220 is mounted on the first source region S1, and the second drain region D2 on the lower surface of the silicon MOS chip 220 is electrically connected to the first source region S1 through a conductive adhesive.
[0037] Combination Figure 3 and Figure 4 , the multiple first drain regions D1 of the D-Mode HEMT chip 210 are electrically connected to the drain pin D through the lead 300 respectively; the multiple first gate regions G1 of the D-Mode HEMT chip 210 are electrically connected to the frame body 101 through the lead 300 respectively, the second source region S2 of the silicon MOS chip 220 is electrically connected to the frame body 101 and the Kelvin source pin KS through the lead 300 respectively, and the second gate G2 of the silicon MOS chip 220 is electrically connected to the gate pin G through the lead 300.
[0038] Embodiment 2
[0039] Figure 5 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the second embodiment of the utility model. In this embodiment, the gallium nitride device is a GaN Cascode, and its packaging structure includes a TO247 packaging frame 100, a GaN Cascode module 200 and a plastic package (not shown in the figure). The TO247 packaging frame 100 includes a frame body 101 and four pins 102, which are a drain pin D, a source pin S, a Kelvin source pin KS and a gate pin G arranged in sequence, wherein the source pin S is integrally connected to the metal backplane of the frame body 101, and the drain pin D, the Kelvin source pin KS and the gate pin G are separated from the frame body 101.
[0040] The GaN Cascode module 200 in the second embodiment is composed of a D-Mode HEMT chip 210 and a silicon MOS chip 220 cascaded and stacked on the front of the frame body 101. The layout is as follows: Figure 4 As shown, it is the same as the first embodiment, and will not be repeated here. Since the Kelvin source pin KS in the second embodiment is separated from the frame body 101, the Kelvin source pin KS in the second embodiment is electrically connected to other source potential points by means of wire bonding, for example, Figure 5 In the embodiment, the Kelvin source pin KS is electrically connected to the frame body 101 through the lead 300. Of course, it can also be connected to other points of the same potential through the lead 300, such as the second source region S2 of the silicon MOS chip 220, the first gate region G of the D-Mode HEMT chip 210, etc. Figure 5 In the embodiment, the Kelvin source pin KS and the frame body 101 are electrically connected by the lead 300, so that the electrical connection of the Kelvin source pin KS can be achieved using a shorter lead, thereby reducing the parasitic parameters caused by the long lead and avoiding the parasitic parameter problems caused by the lead crossing other electrode areas.
[0041] Embodiment 3
[0042] Figure 6 It is a schematic diagram of the internal structure of the package of the gallium nitride device according to the third embodiment of the utility model. In this embodiment, the gallium nitride device is a GaN Cascode, and its packaging structure includes a TO247 packaging frame 100, a GaN Cascode module 200 and a plastic package (not shown in the figure). The TO247 packaging frame 100 includes a frame body 101 and four pins 102, which are a drain pin D, a source pin S, a Kelvin source pin KS and a gate pin G arranged in sequence, and the frame body includes a hollow pin placement area 103, and the Kelvin source pin KS extends into the pin placement area 103 of the frame body 101, and the Kelvin source pin KS is electrically connected to the second source region S2 of the silicon MOS chip by wire bonding. Of course, the Kelvin source pin KS can also be connected to the frame body 101 by wire bonding.
[0043] Embodiment 4
[0044] Figure 7 FIG. 1 is a schematic diagram of the internal structure of the package of the gallium nitride device according to the fourth embodiment of the present invention. In this embodiment, the TO247 package frame 100 is the same as that in the first embodiment. Figure 3 The TO247 package frame 100 shown is the same, the source pin S and the Kelvin source pin KS are respectively connected to the frame body 101 in one piece, and the drain pin D and the gate pin G are separated from the frame body 101 .
[0045] The gallium nitride device in this embodiment is a GaN Cascode module 200, which is composed of a D-Mode HEMT chip 210 and a silicon MOS chip 220 cascaded and arranged in parallel on the front of the frame body 101. Figure 8 , Figure 8 It is an enlarged view of the horizontal parallel layout of the GaN Cascode module 200 according to the fourth embodiment of the utility model. In this embodiment, the D-Mode HEMT chip 210 and the substrate 230 are mounted in parallel on the front of the frame body 101, and the multiple first drain regions D1, multiple first source regions S1 and multiple first gate regions G1 of the D-Mode HEMT chip 210 are placed on the upper surface of the D-Mode HEMT chip 210; the substrate 230 at least includes a first conductive region 231, the second drain region of the silicon MOS chip 220 is placed on the lower surface of the silicon MOS chip 220, and the multiple second source regions S2 and second gate regions G2 of the silicon MOS chip are placed on the upper surface of the silicon MOS chip 220, and the lower surface of the silicon MOS chip 220 is mounted on the first conductive region 231 of the substrate 230, so that the second drain region on the lower surface of the silicon MOS chip 220 is electrically connected to the first conductive region 231 of the substrate.
[0046] Combination Figure 7 and Figure 8 , the first source region S1 of the D-Mode HEMT chip 210 is electrically connected to the first conductive region 231 through the lead 300. The multiple first drain regions D1 of the D-Mode HEMT chip 210 are electrically connected to the drain pin D through the lead 300, the multiple first gate regions G1 of the D-Mode HEMT chip 210 are electrically connected to the frame body 101 through the lead 300, the second source region S2 of the silicon MOS chip 220 is electrically connected to the frame body 101 through the lead 300, and the second gate G2 of the silicon MOS chip 220 is electrically connected to the gate pin G through the lead 300.
[0047] The substrate 230 in this embodiment is, for example, a ceramic plate, a plate filled with a molding compound, or a glass plate.
[0048] Embodiment 5
[0049] Fig. 9 1 is a schematic diagram of the internal structure of the GaN device package according to the fifth embodiment of the present invention. In this embodiment, the GaN device is a GaN Cascode. In this embodiment, the TO247 package frame 100 is the same as that in the second embodiment. Figure 5The TO247 package frame 100 shown is the same, the source pin S is integrally connected to the frame body 101 , and the drain pin D, the Kelvin source pin KS and the gate pin G are separated from the frame body 101 .
[0050] The GaN Cascode module 200 in this embodiment is composed of a D-Mode HEMT chip 210 and a silicon MOS chip 220 cascaded and arranged in parallel on the front of the frame body 101. Figure 8 And the description of the fourth embodiment. Since the Kelvin source pin KS in this embodiment is separated from the frame body 101, in this embodiment, the Kelvin source pin KS is electrically connected to a second source region S2 of the silicon MOS chip 220 through the lead 300. Of course, the Kelvin source pin KS can also be connected to other points of the same potential through the lead 300, such as the Kelvin source pin KS is electrically connected to the frame body 101 through the lead 300.
[0051] Embodiment 6
[0052] Fig.10 FIG. 1 is a schematic diagram of the internal structure of the GaN device package according to the sixth embodiment of the present invention. In this embodiment, the TO247 package frame 100 is the same as that in the third embodiment. Figure 6 The GaN Cascode module 200 in this embodiment is composed of a D-Mode HEMT chip 210 and a silicon MOS chip 220 cascaded and arranged in parallel on the front of the frame body 101. Figure 8 In this embodiment, the Kelvin source pin KS extends into the pin placement area 103 inside the frame body 101, and the Kelvin source pin KS is electrically connected to the second source region S2 of the silicon MOS chip 220 by wire bonding, or the Kelvin source pin KS is connected to the frame body 101 by wire bonding.
[0053] Embodiment 7
[0054] Fig.11It is a schematic diagram of a GaN Cascode module according to the seventh embodiment of the utility model. The GaN Cascode module 200 in this embodiment also includes a boost unit, such as a resistor 240 in this embodiment, one end of which is electrically connected to the first source of the D-Mode HEMT chip 210, and the other end is electrically connected to the first gate of the D-Mode HEMT chip 210. The resistor 240 added between the silicon MOS chip 220 and the D-Mode HEMT chip 210 can achieve leakage balance, and can ensure that under static shutdown, the voltage between the drain and source of the silicon MOS and between the gate and source of the HEMT will not produce a large overshoot spike, thereby avoiding the avalanche breakdown of the silicon MOS and the mis-conduction of the HEMT caused by the avalanche breakdown of the silicon MOS.
[0055] See also Fig.12 , Fig.12 1 is a schematic diagram of the internal structure of the package of the gallium nitride device according to the seventh embodiment of the present invention. The package frame 100 in the package structure of the gallium nitride device in this embodiment is the same as that in the fifth embodiment, except that a resistor 240 is provided on the substrate 230, and one end of the resistor 240 in this embodiment is electrically connected to the frame body 101 through a lead 300, and the other end is electrically connected to the conductive area 231 on the substrate through a lead 300, and other structures are the same and will not be described in detail.
[0056] This embodiment is only an example of a resistor as a boost unit. The present invention does not exclude other components as boost units, such as capacitors, diodes, or a combination of resistors and capacitors or diodes. For example, Fig.11 On the basis of, a capacitor is connected in parallel at both ends of the resistor 240 to ensure that the voltage between the drain and source of the silicon MOS under dynamic switching behavior does not produce a large overshoot spike, avoiding the avalanche breakdown of the silicon MOS and causing the Hemt to be mis-conducted. For another example, a diode is connected in parallel at both ends of the resistor 240 to achieve a voltage stabilization effect, and two reverse-parallel diodes can be added between the gate and source of the silicon MOS to stabilize the voltage at both ends of the gate and source of the silicon MOS, protecting the gate and source of the device from damage by electrostatic discharge (ESD), thereby improving the ESD protection capability. The aforementioned components for the enhancement unit can be placed on the substrate and electrically connected by wire bonding.
[0057] Similarly, you can also Figure 7 and Fig.10 A lifting unit is added to the packaging structure shown in the figure, which will not be described in detail here.
[0058] In the above embodiments, the number of electrode areas of the same type in each chip is not limited, for example, it can be the same large electrode area, or multiple small electrode areas, which can be determined by the production process of the chip. In addition, it should be noted that although the drain electrode in the silicon MOS chip 220 in the above embodiments is located on the lower surface, it is known to those skilled in the art that the electrode distribution of the silicon MOS chip 220 in the utility model is not limited to the above embodiments, and the three electrodes of the silicon MOS chip 220 can also be located on the upper surface of the chip.
[0059] The material of the lead 300 in the above embodiments is metal, such as aluminum (Al), copper (Cu), etc. The lead 300 can be in the form of a wire or a strip, and the electrical connection method is, for example, metal bonding or welding.
[0060] When mounting the chip, conductive adhesive, non-conductive adhesive or soldering can be used. For example, when mounting the silicon MOS chip 220 on the first source region S1 on the upper surface of the D-Mode HEMT chip 210, conductive adhesive or soldering can be used, which not only realizes chip mounting, but also realizes electrical connection between the second drain of the silicon MOS chip 220 and the first source of the D-Mode HEMT chip 210. For another example, the D-Mode HEMT chip 210 is mounted on the front of the frame body 101 using conductive adhesive or non-conductive adhesive, or the D-Mode HEMT chip 210 is soldered on the front of the frame body 101 using solder.
[0061] On the other hand, the present invention also provides a method for manufacturing a packaging structure of a gallium nitride device, see Fig.13 , Fig.13 The present invention is a flow chart of a method for manufacturing a packaging structure of a gallium nitride device according to an embodiment of the present invention, which includes the following steps:
[0062] Step S11, providing a packaging frame, wherein the packaging frame includes connecting ribs and a plurality of TO247 packaging frame units connected by the connecting ribs, wherein the TO247 packaging frame unit includes a frame body and a drain pin D, a source pin S, a Kelvin source pin S and a gate pin G arranged in sequence.
[0063] Step S12, mounting a Cascode module on the front side of each frame body, wherein the Cascode module is formed by cascading a D-Mode HEMT chip and a silicon MOS chip.
[0064] Step S13, electrically connecting each cascode module and the pins in the TO247 package frame unit thereof by wire bonding.
[0065] Step S14, plastic-encapsulating each TO247 package frame unit so that the pins and the back of the frame body are exposed outside the plastic encapsulation body.
[0066] Step S15, cutting the connection ribs connecting the multiple TO247 package frame units to obtain a single gallium nitride device.
[0067] The packaging frame provided in step S11 is as follows Fig.14 As shown, it includes a plurality of identical first TO247 package frame units. The source pin S of the first TO247 package frame unit is integrally connected to the frame body 101, and the Kelvin source pin KS, the drain pin D and the gate pin G are separated from the frame body 101. The structure obtained after cutting is as shown in FIG. Figure 5 and Fig. 9 The structure of the TO247 package frame is shown.
[0068] The package frame provided in step S11 may also include a plurality of identical second TO247 package frame units, wherein the source pin S and the Kelvin source pin KS of the TO247 package frame unit are respectively connected to the frame body 101, and the drain pin D and the gate pin G are separated from the frame body 101. The structure obtained after cutting is as follows: Figure 3 and Figure 7 The structure of the TO247 package frame is shown.
[0069] The package frame provided in step S11 may also include a plurality of identical third TO247 package frame units, wherein the frame body 101 of the third TO247 package frame unit includes a hollow pin placement area 103 extending into the interior along the edge, and the Kelvin source pin KS extends into the pin placement area 103 inside the frame body 101; the source pin S of the third TO247 package frame unit is integrally connected to the frame body, and the drain pin D and the gate pin G are separated from the frame body 101. The structure after cutting is as follows: Figure 6 and Fig.10 The structure of the TO247 package frame is shown in FIG.
[0070] In step S12, when the Cascode module is mounted on the front of each frame body, the D-Mode HEMT chip 210 and the silicon MOS chip 220 are, for example, Figure 4 The stacked layout shown, or Figure 8 The side-by-side horizontal layout shown.
[0071] For example, for Figure 4In the stacked layout shown, the D-Mode HEMT chip is first mounted on the front side of the frame body using conductive adhesive or non-conductive adhesive, or the D-Mode HEMT chip is soldered to the front side of the frame body using solder, and the first drain region, the first source region and the first gate region of the D-Mode HEMT chip are placed on the upper surface of the D-Mode HEMT chip.
[0072] Then, the lower surface of the silicon MOS chip is mounted on the first source region of the D-Mode HEMT chip by using conductive adhesive, or the lower surface of the silicon MOS chip is welded to the first source region of the D-Mode HEMT chip by using solder, so that the second drain region on the lower surface of the silicon MOS chip is electrically connected to the first source region of the D-Mode HEMT chip, wherein the second drain region of the silicon MOS chip is placed on the lower surface of the silicon MOS chip, and the second source region and the second gate region of the silicon MOS chip are placed on the upper surface of the silicon MOS chip.
[0073] For example, for Figure 8 In the parallel horizontal layout shown, when mounting the Cascode module on the front of each frame body, the D-Mode HEMT chip and the substrate are first mounted on the front of the frame body in parallel using conductive glue or non-conductive glue, and welding can also be used. The first drain region, the first source region and the first gate region of the D-Mode HEMT chip are placed on the upper surface of the D-Mode HEMT chip; the substrate at least includes a first conductive region.
[0074] Then, a conductive adhesive is used to mount the lower surface of the silicon MOS chip on the first conductive area of the substrate, so that the second drain area on the lower surface of the silicon MOS chip is electrically connected to the first conductive area of the substrate; wherein the second drain area of the silicon MOS chip is placed on the lower surface of the silicon MOS chip, and the second source area and the second gate area of the silicon MOS chip are placed on the upper surface of the silicon MOS chip.
[0075] When the Cascode module includes a lifting element such as a resistor, a capacitor, a diode or a combination thereof, the lifting element is adhered to a suitable position on the substrate using a non-conductive adhesive.
[0076] In this embodiment, the frame body is made of metal material, and the D-Mode HEMT chip is directly placed on the frame body, so that the frame body can play a role in heat dissipation.
[0077] In step S13, when each cascode module and its pins in the TO247 package frame unit are electrically connected by wire bonding, the electrical connection relationship in embodiments 1 to 6 can be obtained according to the layout of the D-Mode HEMT chip 210 and the silicon MOS chip 220 during chip mounting and the position relationship between the pins and the frame body. The cascode module may also include components that play a role in boosting, such as resistors, capacitors, diodes or a combination thereof. The structure after wire bonding is as follows: Fig.12 shown.
[0078] In step S14, during the plastic encapsulation, a mold is used to plastic encapsulate the frame body and the pins in each TO247 package frame unit to form a plastic encapsulation body. During the plastic encapsulation, the back of the frame body is exposed outside the plastic encapsulation body to facilitate heat dissipation of the device.
[0079] See also Fig.14 , the pins in the TO247 package frame unit are connected together by the first connecting rib 111, and the pins of two adjacent TO247 package frame units are connected to the frame 113 by the first connecting rib 111 and the second connecting rib 112. In step S15, the frame 13 is cut off horizontally, and the first connecting rib 111 between the pins is cut longitudinally to separate the pins, and the second connecting rib 112 between the two TO247 package frame units is cut longitudinally to obtain a single device.
[0080] The order of the pins of the gallium nitride device provided by the utility model is the same as that of the existing SiC MOS and Si MOS structures, namely D, S, K, and G from left to right, thereby achieving direct pin-to-pin replacement with the existing mainstream TO247-4L power device.
[0081] The gallium nitride device provided by the utility model adopts a GaN Cascode module and uses a low-voltage MOS as a switching device. Compared with SiC MOS or Si MOS of the same specification, the capacitance is relatively small, the switching loss is relatively low, the switching frequency limit is small, and the high-frequency performance of GaN HEMT is better.
[0082] The gallium nitride device provided by the utility model provides a Kelvin pin, and the gate-source voltage (Vgs) has a separate control loop, which avoids the influence of the induced voltage of the inductor on the source electrode on the driving loop, thereby increasing the switching speed and reducing the switching loss. Since the GaN Cascode module uses a low-voltage MOS, the threshold voltage (Vth) is relatively low, and the fluctuation of Vgs will affect the switching performance. After the utility model provides a Kelvin pin, it can significantly reduce the influence of the fluctuation of Vgs on the switching performance, thereby effectively improving the device performance.
[0083] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.
Claims
1. A packaging structure of a gallium nitride device, characterized in that: include: A TO247 package frame, comprising a frame body and a drain pin, a source pin, a Kelvin source pin and a gate pin arranged in sequence, wherein the source pin is integrally connected to the frame body, and the drain pin and the gate pin are separated from the frame body; A Cascode module, wherein the Cascode module is composed of a D-Mode HEMT chip and a silicon MOS chip cascaded and placed on the front of the frame body; the first drain region of the D-Mode HEMT chip is electrically connected to the drain pin by wire bonding; the first gate region of the D-Mode HEMT chip is electrically connected to the frame body by wire bonding; the first source region of the D-Mode HEMT chip is electrically connected to the second drain region of the silicon MOS chip; the second gate region of the silicon MOS chip is electrically connected to the gate pin by wire bonding, and the second source region of the silicon MOS chip is electrically connected to the frame body by wire bonding; as well as The back and pins of the frame body are exposed outside the plastic package body.
2. The packaging structure of the gallium nitride device according to claim 1, characterized in that: The Kelvin source pin is integrally connected to the frame body.
3. The packaging structure of the gallium nitride device according to claim 2, characterized in that: The second source region of the silicon MOS chip is electrically connected to the Kelvin source pin by wire bonding.
4. The packaging structure of the gallium nitride device according to claim 1, characterized in that: When the Kelvin source pin is separated from the frame body, the second source region of the silicon MOS chip is electrically connected to the Kelvin source pin by wire bonding; or, the frame body is electrically connected to the Kelvin source pin by wire bonding.
5. The packaging structure of the gallium nitride device according to claim 4, characterized in that: The frame body includes a hollow pin placement area extending into the interior along the edge, and the Kelvin source pin extends into the pin placement area inside the frame body and is electrically connected to the second source area of the silicon MOS chip or the frame body by wire bonding.
6. The packaging structure of the gallium nitride device according to any one of claims 1 to 5, characterized in that: The D-Mode HEMT chip is mounted on the front side of the frame body, and the first drain region, the first source region and the first gate region of the D-Mode HEMT chip are placed on the upper surface of the D-Mode HEMT chip; The second drain region of the silicon MOS chip is disposed on the lower surface of the silicon MOS chip, and the second source region and the second gate region of the silicon MOS chip are disposed on the upper surface of the silicon MOS chip; The lower surface of the silicon MOS chip is mounted on the first source region of the D-Mode HEMT chip, and the second drain region on the lower surface of the silicon MOS chip is electrically connected to the first source region of the D-Mode HEMT chip.
7. The packaging structure of the gallium nitride device according to any one of claims 1 to 5, characterized in that: The D-Mode HEMT chip and the substrate are mounted in parallel on the front side of the frame body, and the first drain region, the first source region and the first gate region of the D-Mode HEMT chip are placed on the upper surface of the D-Mode HEMT chip; the substrate at least includes a first conductive region, the second drain region of the silicon MOS chip is placed on the lower surface of the silicon MOS chip, the second source region and the second gate region of the silicon MOS chip are placed on the upper surface of the silicon MOS chip, and the lower surface of the silicon MOS chip is mounted on the first conductive region of the substrate, so that the second drain region on the lower surface of the silicon MOS chip is electrically connected to the first conductive region of the substrate; the first source region of the D-Mode HEMT chip is electrically connected to the first conductive region by wire bonding.
8. The packaging structure of the gallium nitride device according to claim 7, characterized in that: The Cascode module further includes a lifting unit, which is disposed on the substrate and is electrically connected to the D-Mode HEMT chip and / or the silicon MOS chip by wire bonding.
9. The packaging structure of the gallium nitride device according to claim 1, characterized in that: The D-Mode HEMT chip has a plurality of first drain regions; and / or, the D-Mode HEMT chip has a plurality of first gate regions; and / or, the silicon MOS chip has a plurality of second source regions.